HiSilicon boosts productivity deploying advanced Cadence simulator

SAN JOSE, USA: Cadence Design Systems Inc. announced that China’s HiSilicon Technologies Co. Ltd achieved dramatic results in its verification flow using the Cadence Virtuoso Accelerated Parallel Simulator.

HiSilicon uses the award-winning simulator to verify its complex ASICs. Used by the world’s leading analog design teams, the Accelerated Parallel Simulator can dramatically speed design cycles while delivering more complete simulation coverage to guard against bugs.

“We recognized the need to conduct faster and more thorough verification of our advanced designs, such as PLLs and ADCs,” said XiaoWei Wang, director of HiSilicon’s Analog Design Department.

“Compared to baseline results from the Cadence Spectre Circuit Simulator, the Accelerated Parallel Simulator has provided from three to 24 times speed-up on various circuits with different CPU configurations, greatly enhancing our simulation capability for large post-layout verification. In general, the Accelerated Parallel Simulator has improved the efficiency of our design verification flow up to 40 percent, exceeding our expectations. Its seamless integration into the Virtuoso IC 6.1 unified custom/analog flow has allowed our engineers to cut the design cycle while increasing simulation coverage.”

Headquartered in Shenzhen, HiSilicon provides ASICs and solutions for communications networks and digital media. These ASICs are widely used in over 100 countries and regions around the world. HiSilicon has design divisions located in Beijing, Shanghai, Silicon Valley (USA) and Sweden.

“The Cadence Virtuoso Accelerated Parallel Simulator delivers next-generation SPICE-accurate simulation that enables design teams to speed the validation process while increasing their confidence that they will achieve first-pass silicon success,” said David Desharnais, group director, product marketing, Silicon Realization at Cadence. “By deploying the product within the framework of the Virtuoso flow, design teams like HiSilicon’s get a custom/analog flow from front-end design to verification that lets them move forward efficiently without risking quality.”

The Virtuoso Accelerated Parallel Simulator supports the EDA360 vision by helping ensure design intent is maintained through broad foundry support, model and circuit qualification. Unified design intent is integral to successful and efficient Silicon Realization, one of the key tenets of EDA360.