FREMONT, USA: The Systems division of Elma Electronic Inc., a leading supplier of chassis, embedded products, and system solutions, now offers the TIC-FEP-VPX3b, an FPGA-based 3U VPX front-end processing board that provides an FMC site coupled to a large capacity Virtex-6 FPGA for extremely flexible I/O.
Designed for digital signal processing (DSP), the versatile TIC-FEP-VPX3b is ideal for applications such as RADAR, sonar, electronic warfare, imaging and communications. The new board offers high performance logic, increased SerDes based I/O and powerful DSP slice resources that help meet higher bandwidth and performance demands, while utilizing up to 25 percent less power.
Supported by low power and high speed GTX transceivers at rates up to 6.5 Gbps, the board enables the application of interfaces used in today's embedded systems. On-board PCIe Gen 1 and Gen 2 protocols, via a hard IP block and Ethernet MAC blocks, allow PCIe x4 and GbE interfaces to be implemented from the FPGA to form data and control planes respectively.
Built to the VPX specifications, the TIC-FEP-VPX3b includes four 4-lane fabric ports on the P1, connected by GTX transceivers to the main FPGA. The four fat pipe channels provide the PCIe x4 and GbE interfaces as well as two x4 expansion ports.
Featuring an on-board Xilinx Virtex-6 FPGA, the board comes with two banks of 40-bit 1.25 GB DDR3 memory with transfer rates of 7.5 Gbps and a Spartan-6 control node, used to load logic images into the main FPGA. The Spartan-6 control node enables 'on the fly' bitstream management for dynamic FPGA configuration. Other resources include zero bus turnaround (ZBT) SRAM with a throughput of 400 MB/sec for expedited read/write processing.
The GTX transceivers can be grouped to form multi-lane Aurora pipes supporting inter-VPX card connection, allowing the FPGA processor boards to be very tightly coupled via point-to-point or mesh topology. The board fits scalable architectures, where more than one FPGA processor is required.
Elma's supporting 3U VPX-300 Reference Development Platform utilizes a backplane architecture (BKP3-CEN09-15.2.17-n) designed specifically for FPGA interconnects. This front-end/back-end topology is part of the VITA 65 OpenVPX specification. In addition to the topology, the RDP provides the 3U VPX FPGA processor and other products compatible with the TIC-FEP-VPX3b FPGA board such as VPX SBCs, control and data plane switches as well as storage modules.
The TIC-FEP-VPX3b is compatible with Xilinx development tools including ISE Design Suite and Platform Cable. The new board supports VxWorks and Linux as standard, with the ability to implement the user's existing source code or third party IP cores.
The board comes in three environmental grades: standard, rugged and conduction-cooled.
Pricing for the TIC-FEP-VPX3b depends on the choice of Xilinx FPGAs and environmental grade. The board is currently shipping.
Thursday, July 21, 2011
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