SAN JOSE, USA: Xilinx Inc. has released the ISE Design Suite 12.3, kicking-off the FPGA leader's roll-out of Intellectual Property (IP) cores that meet the AMBA 4 AXI4 specification for interconnecting functional blocks in System-on-Chip (SoC) design, as well as introducing productivity enhancements to the PlanAhead Design and Analysis cockpit, and Intelligent Clock Gating support for reducing dynamic power consumption in Spartan-6 FPGA designs.
"Xilinx is the first to standardize on the AMBA 4 specification as part of our interconnect strategy to support Plug-and-Play FPGA design. SoC designers who have large investments in AMBA AXI3 and AXI4 interface IP have good reason to use Xilinx programmable platforms compared to alternative FPGA and ASIC solutions," said Vin Ratford, senior VP, Worldwide Marketing at Xilinx.
"The flexibility inherent in the AXI4 interconnect enables it to be tailored for performance and area all while making it easier for customers to integrate IP from different domains and IP providers. It also enables ASIC designers to migrate pre-existing designs and IP to Xilinx FPGAs."
Xilinx's deployment of the AMBA 4 AXI4 specification means customers will have a consistent way to interconnect IP blocks while enabling better use of design resources through the use and reuse of IP, as well as easier integration across IP providers, all in support of Plug-and-Play FPGA design.
In terms of core accessibility and the tools to assemble them, the release of ISE Design Suite 12.3 includes enhancements to the CORE Generator tool that accelerates design time by providing access to highly parameterized IP as well as the Xilinx Platform Studio and System Generator tools that enable designers to quickly configure their system architecture, buses and peripherals.
"The increases in complexity and scale for new designs means that communication and interconnect are critical to system performance," said Michael Dimelow, director of marketing, Processor Division at ARM. "The open nature of the AMBA standard delivers tremendous benefits to system designers by expanding the variety of IP available for implementation in SoC's and FPGAs, and thus accelerating time to market."
"Mercury's commitment to standards and industry leverage has led us to conform to AXI4 because of its broad ecosystem support, time-to-market benefits and alignment to Xilinx's product roadmap," said Charlie Frazer, Director of Silicon IP Engineering at Mercury Computer Systems.
Xilinx's adoption of the AMBA protocol also provides designers access to established ASIC verification methodologies and existing AMBA protocol-based IP, allowing designers to easily make the transition to FPGAs as their SoC platform of choice.
"Cadence has long provided industry-leading AMBA verification solutions for SoC Realization, and our support of AXI4 in collaboration with Xilinx will be welcomed news for SoC designers who rely on Cadence's advanced verification IP and enterprise verification technologies to target their designs to FPGA for prototyping or production," said Michal Siwinski product management group director for System and SoC Realization at Cadence.
"Our collaboration with Xilinx means integrators now have bus functional models they can use with any tool suite to model and verify their designs more easily."
Expanded PlanAhead RTL design, development and analysis cockpit
The ISE Design Suite software's PlanAhead design tool now delivers a seamless "push-button" flow, as well as an advanced visualization and analysis flow.
The PlanAhead tool's cockpit also includes Project Management, Synthesis, CORE Generator integration, Floorplanning, Place-and-Route, ChipScope Pro tool integration and Bitstream generation. The entire Xilinx IP catalog, including AXI4 protocol IP cores, is directly accessible and searchable from the same design cockpit.
Intelligent clock gating support for Spartan-6 FPGAs
The first release of ISE Design Suite 12 in May, 2010 introduced the FPGA industry's first intelligent clock-gating technology with fully automated analysis and fine-grain (logic slice) optimization capabilities specifically developed to reduce the number of transitions, a primary contributing factor of dynamic power dissipation in digital designs.
The technology can reduce dynamic power consumption by as much as 30 percent by using a series of unique algorithms to detect sequential elements ('transitions') within each FPGA logic slice that do not change downstream logic and interconnect when toggled.
The software generates clock-enable logic that automatically shuts down the unnecessary activity at the logic slice level to accumulate power savings without having to shut off an entire clock network. With version 12.3 of the ISE Design Suite, Intelligent Clock Gating supports both the low-cost Spartan-6 FPGA and high-performance Virtex-6 FPGA families.
AMBA 4 AXI4 protocol
The AXI4 protocol is defined by the AMBA interface specification, the de facto industry standard for on-chip communications introduced by ARM more than 15 years ago.
The AMBA 4 specification introduced in March, 2010 was designed by and for the industry with contributions from thirty-five of the industry's leading OEM, EDA and semiconductor vendors including Xilinx.
The AMBA 4 specification includes definition of an expanded family of AXI interconnect protocols including AXI4, AXI4-Lite and AXI4-Stream. The AXI4 protocol defines a Point-to-Point (P2P) interface developed to address system on-chip performance challenges. It supports multiple clock domains, and data up-sizing and down-sizing.
The AXI4 specification also includes features such as address pipelining, out-of -order completion, and multi-threaded transactions. All of these features, when taken together, allow much higher performance systems than those over other bus architectures.
As an example of the benefits to customers, Xilinx's embedded platform Targeted Reference Design converted to AXI4 provides 2X bandwidth over the previous Targeted Reference design. Xilinx's connectivity and DSP platforms Targeted Reference Designs converted to AXI4 achieve the same maximum data throughput with a nominal increase in resources utilized.
ISE Design Suite 12.3 is immediately available for all ISE Editions and list priced starting at $2,995 for the Logic Edition.