NVIDIA uses Mentor’s Olympus-SoC place and route system for leading-edge graphics processors

WILSONVILLE, USA: Mentor Graphics Corp. announced that NVIDIA has adopted the Olympus-SoC product for multi-corner, multi-mode (MCMM) design closure of their high performance graphics processors.

The Olympus-SoC system significantly reduces time to market while improving quality of results with advanced design closure capabilities like synchronized optimization, interconnect re-synthesis and physical SDC, in addition to MCMM closure for very large designs.

“We build some of the world’s largest and highest performance ICs and it’s crucial for us to maintain design schedules in the face of increasing IC complexity,” said Sameer Halepete, vice president of ASIC Engineering at NVIDIA. “We have used Olympus-SoC on multiple GPU tapeouts and are very impressed with the overall quality of results and design schedule savings.”

At the heart of the Mentor Graphics solution is the Olympus-SoC chip assembly flow, which combines the strengths of the conventional hierarchical and flat design flows to deliver high capacity, fast runtime, and reduced memory without sacrificing high quality of results.

The inaccuracies and inefficiencies caused by physical partitioning of designs is eliminated by the Olympus-SoC product’s innovative and scalable architecture that allows designers to load in multi-million gate designs flat, and close timing by working across the physical hierarchies, thereby minimizing ECO iterations.

Analysis and optimizations engines are based on a full chip, signoff-quality STA engine that natively handles timing and leakage power across any number of mode/corner scenarios. The physical SDC generation capability derives accurate block-level timing constraints from actual routes for interface paths. This eliminates the need to over-constrain the block timings with pessimistic estimations and significantly speeds up top-level closure.

Synchronized optimization is another unique feature, which concurrently optimizes all replicated partitions in a full chip context to obtain better overall chip performance while maintaining complete consistency of the design.

Finally, interconnect re-synthesis capability recovers late stage timing by reviewing pin assignment decisions incrementally during full chip optimization, and automatically adjusting pin assignments (location and layer) to improve overall performance.

“We are very pleased with NVIDIA’s success and its decision to standardize on Olympus-SoC for physical implementation and optimization,” said Pravin Madhani, general manager for the Place and Route group at Mentor Graphics.

“Olympus-SoC’s unique architecture, high capacity data model and efficient multi-corner, multi-mode design closure capabilities continue to drive its adoption across various IC growth segments such as mobile, wireless, networking and graphics.”