TSMC selects Anova’s software in Reference Flow 11.0 for full chip statistical leakage power analysis

SANTA CLARA, USA: Anova Solutions Inc. (Anova), an EDA company focusing on timing and power variation analysis, announces its full chip statistical leakage power analysis software, ChronoVA NCS, has been validated by TSMC’s Reference Flow 11.0.

The software provides multi-million gates system-on-chip (SoC) design leakage power statistical results by reading the Switching Activity Interchange Format (SAIF) file and the pre-characterized leakage library database.

Tom Quan, deputy director of design methodology and service marketing at TSMC, said: “The Anova software brings SPICE Monte Carlo transistor-level accuracy on full chip scale. The mean and sigma value results are less than 10 percent comparing with SPICE Monte Carlo. With the pre-characterized cell leakage model, the software can produce the chip leakage power statistical result for million-gate SoC within few minutes. ChronoVA helps quickly and accurately evaluate customer chip’s standby power consumption variation.”

Jun Li, CEO of Anova, added: “The hierarchical approach applied on our S.A.P technology helps to achieve the transistor level accuracy with the gate level speed and capacity on full chip leakage variations analysis. We provide software to generate the cell leakage model; our analysis software can also generate the leakage model for sub blocks, macros and 3rd party IP. We are glad to extend our statistical technologies to full chip power analysis domain on TSMC new design reference flow.”