BANGALORE, INDIA: Magma Design Automation, GLOBALFOUNDRIES and Virage Logic have announced the availability of a proven, Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow.
This automated, comprehensive solution streamlines the design and manufacture of ICs that incorporate Virage Logic's intellectual property (IP) and are manufactured in GLOBALFOUNDRIES' 65LPe 65-nanometer (nm) low-power process technology.
This integrated RTL-to-GDSII reference flow is based on Talus 1.1, the current release of Magma's IC implementation system, and leverages Talus Design for synthesis, Talus Vortex for physical design and Talus Power Pro for power optimization.
The reference flow supports power intent through the UPF standard, incorporating multiple voltage domains, retention cell management, insertion of automatic level shifters and isolation cells, power switches, well tap cells and on-chip variation. Talus 1.1 also supports the CPF standard for power intent.
To validate the flow, a reference design incorporating Virage Logic SiWare standard-cell and SiWare memory IP was implemented in the Talus system using a UPF-compliant low-power design intent specification. The reference design met GLOBALFOUNDRIES' technical specifications including all low-power requirements.
"Creating a comprehensive low-power flow that delivers good performance is a challenging task," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "The Magma-GLOBALFOUNDRIES-Virage Logic collaboration will help designers address these challenges by enabling them to quickly implement their low-power designs within Magma's Talus flow and take advantage of the low-power performance of the GLOBALFOUNDRIES 65LPe process."
"Our customers not only need advanced low-power solutions, they need to hit their critical market windows on time with reliable predictability," said Walter Ng, vice president, IP Ecosystem at GLOBALFOUNDRIES. "The reference low-power design implemented with Magma's Talus system and the Virage Logic library enables our customers to quickly take full advantage of GLOBALFOUNDRIES proven 65LPe process."
"Our mutual customers are increasingly being driven to reduce both dynamic and standby power consumption," said Brani Buric, executive vice president of Marketing and Sales of Virage Logic. "This new Magma-GLOBALFOUNDRIES-Virage Logic 65LPe reference design flow enables them to use the UPF standard along with our SiWareTM Memory and SiWareTM Logic to meet their low-power design requirements."
SiWare Memory compilers and SiWare Logic libraries enable SoC designers to optimize for power, performance, area and yield and are available to customers for the GLOBALFOUNDRIES 65LPe process through Virage Logic's foundry sponsored IP program. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage Logic upon request.