Calypto expands lead in ESL verification with latest SLEC release

DAC 2010, SANTA CLARA, USA: Enabling electronic system level (ESL) design flows for increasingly complex SoC devices, Calypto Design Systems Inc. has announced that its latest SLEC 5.0, release includes breakthrough technology for verifying deep, complex loop structures in ESL flows. SLEC is the industry’s only comprehensive functional verification solution that formally verifies equivalence between ESL models and RTL implementations.

“The accelerating maturity of ESL flows requires Calypto’s R&D team to continuously advance our algorithms to support an expanding set of designs, including those that use loop structures to define complex digital functions,” said Tom Sandoval, CEO of Calypto Design Systems. “The technology breakthroughs in SLEC 5.0 will enable the tool to support new application spaces and provide a significantly improved user experience for our customers.”

SLEC 5.0 includes next generation formal verification algorithms to handle designs with deep, complex loops. Previous algorithms for loop verification relied on expensive and often prohibitive loop unrolling technique that limited capacity and forced users to manage loop sizes by setting static loop bounds.

With Calypto’s latest advances, verification of designs with complex loops will no longer require the user to provide constraints, dramatically improving the user experience and delivering a comprehensive and scalable verification solution for a broader set of design applications.

SLEC 5.0 also includes new features that enable comprehensive verification of designs with large memories. Large arrays in a system level design that model large memories in the corresponding RTL design can stress the capacity boundaries of formal verification methods.

SLEC 5.0 includes new techniques to model memories that reduce their size in SLEC’s database by up to 90 percent and effectively increase the size of the memories that can be handled by SLEC.

The SLEC family of products includes:
SLEC System: Formally verifies equivalence of system-level models and RTL designs.
SLEC System-HLS: Formally verifies that an RTL design generated using high-level synthesis is functionally equivalent to its corresponding system level model.
SLEC RTL: Formally ensures functional equivalence between a golden RTL model and a corresponding RTL model has been sequentially modified to reduce power or improve performance.
SLEC Pro: Comprehensively verifies that an RTL design generated by Calypto’s PowerPro product is functionally equivalent to its corresponding golden RTL model.

Available now, Calypto’s SLEC 5.0 runs on PC platforms running Linux. Pricing for a one-year, time-based license is as follows: SLEC System: $250,000, SLEC System-HLS (add on option to SLEC System): $50,000, SLEC RTL: $175,000, and SLEC Pro: $125,000.