Synopsys announces system-level catalyst program

MOUNTAIN VIEW, USA: Synopsys Inc. has announced its System-Level Catalyst Program to accelerate the adoption of system-level design and verification.

Open to EDA vendors, IP vendors, embedded software companies and service providers, the program is designed to benefit mutual customers by advancing tool and model interoperability as well as availability of system-level models and services.

Members of the System-Level Catalyst Program gain access to Synopsys system-level and rapid prototyping products such as Innovator, DesignWare System-Level Library, System Studio, Synplify DSP and the Confirma platform. System-Level Catalyst Program members may also use the Synopsys System-Level Catalyst logo with their products or services to indicate system-level interoperability.

"Interoperability and model availability have long been inhibitors for the adoption of system-level design flows," said Gary Smith, chief analyst at Gary Smith EDA, a leading provider of market intelligence and advisory services for the global Electronic Design Automation (EDA), Electronic System Level (ESL) design, and related technology markets. "Making system-level model libraries and tools freely available to members as part of the Synopsys System-Level Catalyst program enables further mainstream adoption of ESL solutions."

The System-Level Catalyst Program provides members tool access to validate and demonstrate interoperability or to support customers:

* IP providers and EDA vendors get access to and support for Synopsys tool and library offerings to validate and demonstrate interoperability of system-level models of their IP and their tool solutions.
* Embedded software vendors get access to Synopsys' Innovator and DesignWare System-Level Library to validate and demonstrate interoperability of debuggers.
* Qualifying embedded software developers who specialize in the development of drivers and software for Synopsys DesignWare Cores get access to virtual platforms and Confirma rapid prototyping platforms for software development prior to silicon availability.

Training and services companies can help system-level teams rapidly adopt the best practices for system-level design, virtual platforms, digital signal processing and FPGA based rapid prototyping.

"VDC expects software design and verification to continue to play an increasingly important role in the hardware and system engineering processes. At the same time, software solution providers are looking for improved methods and tools to enable their customers to program to increasingly complex hardware architectures," says Matt Volckmann, Senior Analyst/Program Manager with VDC Research's Embedded Software Practice.

"Synopsys' introduction of the System-Level Catalyst program recognizes the necessity for greater collaboration among software and hardware engineering solution companies and the ongoing endeavor of these organizations to provide their customers with the resources required to further advance engineering productivity."

Founding members of the System-Level Catalyst program include: Agilent EEsof, Altera, ARC International, Carbon Design Systems, Cebatech, ChipVision Design Systems, Cofluent Design, CoWare, CriticalBlue, Doulos, Emsys, Enterpoint, Forte Design Systems, GreenSocs, IBM, Imperas, JEDA Technologies, Jungo, Lauterbach, MCCI, NoBug, SDV Ltd., Steepest Ascent, Synfora, Target Compiler, Tensilica, VaST Systems and Xilinx.

"The system-level market's growth and our customers' adoption of system-level methodologies have been limited by severe market fragmentation and lack of model and tools interoperability," said George Zafiropoulos, vice president of Solutions Marketing at Synopsys. "With the System-Level Catalyst Program Synopsys is helping open up the system-level market to mainstream adoption, enabling new levels of interoperability."