Wednesday, June 3, 2009

SMIC deploys Synopsys HSPICE simulator for 45nm physical IP and standard cell development

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Semiconductor Manufacturing International Corp., one of the leading semiconductor foundries in the world, has adopted Synopsys' HSPICE circuit simulator and WaveView Analyzer for design and verification of its 65nm and 45nm IP blocks, I/O circuitry and standard cell characterization flows.

Taking advantage of the innovations in the 2009.03 release of the HSPICE circuit simulator, SMIC was able to cut simulation runtime in half with improved silicon correlation over their existing solution.

"With HSPICE, we were able to run our analog IP and standard cell circuits two times faster than our existing solution," said Paul Ouyang, vice president of Design Services at SMIC. "In addition, WaveView Analyzer significantly improved our verification productivity by delivering an easy-to-use, feature-rich and high-performance waveform analysis solution. We are now able to instantly render large waveforms and run automatic specification verification functions."

"The 2009.03 release of HSPICE delivers further simulation speed improvements on both single- and multicore computer hardware while maintaining the same trusted silicon-accurate results," said Graham Etchells, director of marketing for the Analog/Mixed-Signal Group at Synopsys. "Continuing innovations in HSPICE, WaveView Analyzer and other AMS circuit simulation solutions enable foundries worldwide to accelerate development of advanced process nodes."

The HSPICE simulator is widely recognized as the "gold standard" for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With more than 25 years of successful design tapeouts, the HSPICE simulator is one of the fastest and most trusted circuit simulators.

HSPICE is an integral component of Synopsys' Discovery Verification Platform, which offers high-performance functional and mixed-signal verification to enable designers to achieve the highest throughput and accuracy for complex mixed-signal system-on-chip (SoC) designs.

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