eInfochips' DDR2 SDRAM SystemVerilog memory model generator tool

AHMEDABAD, INDIA: eInfochips, Inc. has announced the availability of a DDR2 SDRAM SystemVerilog Memory Model Generator. This HVL-based tool is an integrated solution to generate behavioral models for all leading memory vendors, such as Micron, Samsung, Hynix and Elpida, thereby shortening verification time and maximizing memory coverage.

“eInfochips strives to market solutions that add value to the design process,” states Sribash Dey, VP, North America Sales at eInfochips. “By offering high-quality simulation models and verification environments, we believe the DDR2 SDRAM memory model generator tool will reduce overall verification time and reduce development cost.”

With eInfochips’ DDR2 SDRAM model generator, it is possible to configure parameters of DDR2 SDRAM memory such as memory size, data width, clock rate, cycle time, CAS latency and data rate.

Key features of memory generator tool
The DDR2 SDRAM memory generator is a TCL/TK-based tool that supports leading memory vendors and preserves a large library of part numbers for each supported memory vendor. The tool can be operated in two modes -- Typical Mode or Custom Mode. In the Typical Mode, a user may choose vendors and part numbers to generate the memory model. In the Custom Mode, a user may create a customized behavioral model from scratch by configuring the parameters of DDR2 SDRAM through the configuration selection algorithm (CSA).

Key features of generated behavioral models
The behavioral models are compliant to JEDEC standard JESD79 – 2D and ready to be plugged into a verification environment. The models offer built-in coverage and can be configured to turn on/off initialization, enable/disable DDR2 interface checkers and coverage.

Deliverables include verified SystemVerilog DDR2 SDRAM generator encrypted code, a user guide and release notes.

DDR2 SDRAM SystemVerilog memory generator tool is now available and comes with support.