SAN JOSE, USA: CoWare Inc., a leading supplier of Electronic System Virtualization software and services, announced the availability of a new Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect, enabling early and efficient optimization of next-generation SoC architectures using ARM AMBA-based virtual platforms.
CoWare virtual platforms for architecture design are the virtualized representation of an electronic system used for the purpose of system-level performance analysis and architecture optimization.
The new flow provides system architects with the ability to efficiently capture the dynamic performance workloads of each application subsystem of a multi-function SoC in the form of transaction traffic, months before software is available and with minimum modeling effort using a well-defined, repeatable methodology.
CoWare is the leading global supplier of electronic system virtualization solutions for software development, platform architecture design and platform verification of ARM-based platforms. CoWare combines ARM instruction-accurate processor models and implementation-accurate Carbonized ARM models within one standards-based SystemC design environment.
The CoWare solutions enable engineers to take full advantage of the capabilities of the entire range of ARM system elements in the context of the actual design; from ARM memory controllers and interconnects to application and embedded processors and embedded firmware.
“CoWare has been the leader in electronic system virtualization solutions for ARM technology-based platforms for more than 10 years now,” said Johannes Stahl, vice president of marketing and business development at CoWare. “This new flow captures the production-proven design methods successfully deployed by CoWare customers to analyze and improve next-generation system performance and cost sooner by using transaction traffic generation, while retaining full support in the same environment for the HW-SW performance validation of early architectural decisions using cycle-accurate processor models and software, as they become available throughout the development process.”
The new Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect is enabled by CoWare’s advanced system-level design features, including:
* Trace- and task-driven generation of transaction traffic, enabling creation of performance workload models reflecting the application performance workloads of the multi-function use-cases for interconnect and memory subsystem analysis;
* Integrated graphical environment for transaction tracing and statistical port analysis enabling platform model validation and system-level performance measurement of transaction count, transaction throughput, and transaction latency;
* Support for simulation and analysis of multiple TLM protocols at mixed levels of abstraction, including TLM-2.0 and cycle-accurate AHB, APB, and AXI communication protocols, and user-defined data collection based on SCV transaction recording;
* Scripting support for simulation sweeping of traffic scenarios and IP parameters across multiple simulations enabling design space exploration, sensitivity analysis using spreadsheets, and root cause analysis;
* CoStart services for rapid end-user ramp-up with AXI-based designs.
CoWare Platform Architect tool and IP model enhancements and CoWare CoStart services are available immediately for use with the 2009.1.1 release.