Arteris and Duolog streamline SOC integration design flow

Design Automation Conference 2009, SAN JOSE, USA: Arteris Inc., the leading developer of Network on Chip (NoC) solutions and Duolog, a provider of SoC integration tools, announced the integration of Duolog design tools with Arteris’ NoC solution to provide designers a more streamlined and efficient way to integrate multiple semiconductor intellectual property (IP) blocks on a single system on chip (SoC) device.

The integration leverages Arteris’ NoC solution for enabling high-performance on-chip interconnect and communications, and Duolog’s Socrates Chip Integration Platform, which is a suite of tools for capturing, viewing and validating various elements of the infrastructure of complex SoCs.

The integration uses the industry standard IP-XACT format, a standard way to describe and handle IP from multiple sources. Using the Arteris NoCcompiler tool, SoC designers can quickly configure, instantiate, and connect NoC IP units to generate specific NoC instances, including full RTL and verification infrastructures. As part of this NoC IP instance generation, NoCcompiler generates an IP-XACT description which includes high-level interfaces, ports and memory map data.

The Duolog system uses the IP-XACT description to allow designers to capture the software view of the system from low-level IP registers and bitfields to the full system-level memory map.

Its Socrates Bitwise register management tool not only captures the complete memory map infrastructure but provides real-time views from any point on the memory map. It generates a wide range of collateral including documentation, hardware design and verification infrastructures and software API models.

“With this integration, we have been able to add a new register to an IP block to automatically generate a new software API and corresponding documentation at the chip level, all in less than a minute. For this level of turnaround time we need to ensure we clearly understand the NoC memory mapping, which is what our close collaboration with Arteris has allowed,” said Ray Bulger, CEO of Duolog.

“We have worked closely with Arteris and several of our customers to ensure that we align on the memory map content via the IP-XACT standard and have proved that this level of tool coupling can significantly improve the efficiency of streamlining our mutual customers’ IP integration flow.”

The streamlined flow also incorporates Duolog’s Socrates Weaver, a rules-based assembly engine that enables rapid and robust interface and port-level connectivity to ensure that the chip integration can happen sooner and more predictably.

“The integration of our NoC generation system with Duolog’s viewing and validation capabilities provides a robust and efficient way to integrate complex SoCs,” said Charlie Janac, CEO of Arteris.

“Our customers can use the Arteris NoC IP and tools to rapidly generate NoC instance IPs to achieve their system performance goals. By combining our NoC approach with Duolog’s tools, customers can integrate the Arteris NoC Instance IPs with the rest of the SoC to produce earlier software and hardware deliveries. By using standards such as IP-XACT to package the NoC IPs, it is an extremely interoperable approach that allows the use of a wide variety of IP.”

The integrated Arteris/Duolog solution will be demonstrated at the 2009 Design Automation Conference in San Francisco (July 26-31) in the Duolog Booth #2028.