NVIDIA adopts Synopsys IC Validator for sign-off physical verification

MOUNTAIN VIEW, USA: Synopsys Inc. announced that NVIDIA has adopted Synopsys' recently announced IC Validator physical verification solution.

The IC Validator DRC/LVS solution has been specifically developed for advanced designs at 45nm and below to offer in-design physical verification as well as signoff. As the inventor of the Graphics Processing Unit (GPU) and the world leader in visual computing technologies, NVIDIA designs multi-billion transistor processors that require the highest level of tool performance and productivity. By achieving near-linear scalability, such as the 20x speedup observed by NVIDIA using 25 CPUs, IC Validator provides accelerated time to tapeout.

"We continue to push design complexity to meet our customers' visual computing needs. To validate such large designs in a timely fashion, we require a high-performance, high-capacity physical verification engine. IC Validator demonstrated that we can verify our largest designs overnight using our standard hardware configurations," said James Chen, manager of VLSI technology at NVIDIA. "In addition, the flexibility offered by IC Validator's highly programmable language will help us customize design flows to improve productivity. Working closely with our foundry partners, we are deploying IC Validator for our designs."

IC Validator has been architected to address the challenges physical designers of complex designs at advanced process nodes face today. IC Validator delivers the high accuracy necessary for leading-edge process nodes, excellent scalability for efficient utilization of available hardware, superior ease-of-use for the physical designer, and high programmability for easier runset development.

The solution deploys intelligent auto detection techniques to identify available hardware resources by taking advantage of existing compute job scheduler configurations. This includes configuring an intelligent mix of distributed processing and multithreading to provide the industry's best scalability without special hardware setup.

For the runset writers and CAD managers, IC Validator offers a flexible programming language that can cut runset size from 2-10x, lowering the cost of setting up, maintaining and modifying the physical verification environment.

Already in production at a world-leading IDM and qualified at leading foundries, IC Validator offers incremental capabilities, significant automation and innovative features such as DRC error classification, multi-user collaboration, customized reporting and on-the-fly error reporting.

"As a leading semiconductor company focused on cutting-edge designs, NVIDIA has repeatedly set the bar for physical verification tool performance, capacity and programmability," said Antun Domic, senior vice president and general manager, Implementation Group at Synopsys. "NVIDIA's adoption of IC Validator is a significant endorsement of its benefits and Synopsys' technology addressing the requirements for the industry's most advanced designs."