WILSONVILLE, USA: Mentor Graphics Corp. announced that the Catapult C Synthesis tool has been extended to support control logic and manage low power design requirements, thus enabling full-chip high-level synthesis (HLS).
This breakthrough technology allows designers to use pure ANSI C++ for both algorithmic blocks and control logic blocks. Extending the Catapult C tool’s capabilities to full-chip high-level synthesis is critical due to the rapid growth in design size and complexity, which requires engineers to design hardware functionality at higher levels of abstraction.
Control logic synthesis and algorithmic synthesis have traditionally been addressed using different languages, formalisms and abstractions. The latest advances in the Catapult C Synthesis tool unifies these two domains, allowing users to describe control logic along with algorithmic behavior in a single and coherent model leveraging standard ANSI C++.
At the heart of this innovation is a new synthesizable C++ construct, which allows designers to easily specify asynchronous data communication, allowing full control over concurrent hardware creation. This pivotal mechanism allows interfacing algorithmic representations driven by the dataflow with control-dominated blocks synchronized by clocks.
The result is a coding style familiar to hardware designers, letting users easily express communication, priority and task coordination within an abstract representation of concurrency. The new approach formalizes a modeling style, which provides the necessary accuracy for control oriented tasks, while preserving the abstraction beneficial for algorithmic subsystems.
The synthesis process is complemented by a patent-pending and fully automated verification flow which for the first time lets users validate the detailed RTL-level block interactions at the C level.
Tight integration between verification and synthesis has proved a necessity to realizing the full potential of HLS. A common pitfall found with other HLS tools is developing high-level synthesis in isolation, which results in overly complex verification of the RTL output.
"Our digital broadcasting ICs typically consist of a complex mix of compute intensive algorithmic units and control dominated blocks," said Professor Schlicht, Head of Department, Fraunhofer Institute for Integrated Circuits.
"The new Catapult extensions for control-logic synthesis provide us with the capability to develop an increasing portion of the overall system using high-level synthesis from C++. This allows us to extend our C++ based implementation flow beyond the pure signal processing blocks."
In addition to support for control logic, the Catapult C Synthesis tool has added innovative technology for low power design by automating two prevailing design techniques: multi-level clock gating and interfacing to dynamic power and clock management units.
The Catapult C tool will analyze deep cones of logic to find gateable clocks, an otherwise error-prone and manual task typically done by backend low power experts.
This new and unique optimization delivers near 100% perfect clock gating by operating at the flop level, maximizing power savings by locally inferring the gating logic surrounding the targeted registers.
To help further reduce power, the Catapult C Synthesis tool also exports real-time information on the state of all system blocks. This information is relayed to power management units leveraging dynamic frequency and voltage scaling heuristics to achieve system-wide power savings.
As expected, dynamic power savings is design and test vector dependent; measurements on more than 300 customer designs showed improvements ranging from 10 percent to 90 percent, with an average improvement of 40 percent.
"The control logic extensions of Catapult C now let us develop a larger part of our systems with HLS," said Emmanuel Liegeon, Deputy Manager of Digital ASIC & FPGA Design Group, Thales Alenia Space. "As we develop more and more of the system in HLS, it becomes paramount to get power right. The latest enhancements in Catapult C for low power are delivering the optimizations we need."
Catapult C
The Catapult C Synthesis tool is the first product to automatically generate control and algorithmic RTL multi-block designs from a pure ANSI C++ source where both the core algorithm and interface are untimed.
This productivity improvement gives designers time and freedom to automatically perform detailed design exploration of different micro-architectural options and interface scenarios to quickly achieve fully optimized hardware designs.
The Catapult C Synthesis 2009a release is available to customers in July. The Catapult C product family ranges from $140,000 to $390,000.
Showing posts with label low power design. Show all posts
Showing posts with label low power design. Show all posts
Monday, June 29, 2009
Friday, May 15, 2009
LSI GbE PHY reduces power, cost of server and switch systems
BANGALORE, INDIA: LSI Corp. today announced a new generation of gigabit Ethernet (GbE) PHY silicon technology for server, desktop, mobile and networking switch applications. Now in its fourth generation, the LSI Energy-Efficient GbE PHY provides the industry’s lowest-power GbE technology in the smallest size, enabling OEMs to dramatically reduce chip count, energy consumption and bill of materials cost.
Escalating power costs and upcoming ENERGY STAR compliance guidelines from the US Environmental Protection Agency and Department of Energy are driving IT and telecommunications equipment manufacturers to build more power-efficient products.
Substantial economies in energy consumption can be achieved by the deployment of “multi-rate” devices, which are capable of ramping down during periods of inactivity. The LSI Energy-Efficient GbE PHY transitions to low-power mode in the absence of data traffic, yet immediately returns to full speed when traffic resumes.
Since the online traffic continues to escalate, both high performance and low power consumption are essential to the mass deployment of next-generation, energy-efficient Ethernet networks. The LSI GbE PHY is capable of reducing Ethernet switch power consumption by more than 30 percent, and it is available now for implementation in custom integrated designs. It is also backward compatible with existing Ethernet standards, which allows for rapid migration.
"Private enterprises and government agencies can meet the demands of growing network traffic and impending federal guidelines by accelerating their plans to upgrade to high-performance, low-energy networks,” said Jim Anderson, vice president of geographic sales and marketing, Semiconductor Solutions Group, LSI. “Our customers are implementing the new LSI GbE PHY to meet those demands today.”
Escalating power costs and upcoming ENERGY STAR compliance guidelines from the US Environmental Protection Agency and Department of Energy are driving IT and telecommunications equipment manufacturers to build more power-efficient products.
Substantial economies in energy consumption can be achieved by the deployment of “multi-rate” devices, which are capable of ramping down during periods of inactivity. The LSI Energy-Efficient GbE PHY transitions to low-power mode in the absence of data traffic, yet immediately returns to full speed when traffic resumes.
Since the online traffic continues to escalate, both high performance and low power consumption are essential to the mass deployment of next-generation, energy-efficient Ethernet networks. The LSI GbE PHY is capable of reducing Ethernet switch power consumption by more than 30 percent, and it is available now for implementation in custom integrated designs. It is also backward compatible with existing Ethernet standards, which allows for rapid migration.
"Private enterprises and government agencies can meet the demands of growing network traffic and impending federal guidelines by accelerating their plans to upgrade to high-performance, low-energy networks,” said Jim Anderson, vice president of geographic sales and marketing, Semiconductor Solutions Group, LSI. “Our customers are implementing the new LSI GbE PHY to meet those demands today.”
Friday, December 26, 2008
Rapidly growing local market bring new opportunities for EDA in India
Those following the EDA industry are well aware that its been an industry in some trouble right through this year.
If you visited EDA Consortium's web site, this becomes clear. In Q1-08, the global EDA industry revenue for Q1 2008 declined 1.2 percent to $1,350.7 million compared to $1,366.8 million in Q1 2007.
Later, the EDA industry revenue for Q2 2008 declined 3.7 percent to $1357.4 million compared to $1408.8 million in Q2 2007, as reported by the EDA Consortium.
I am still waiting to see how the Q3 results shape up. My guess is, it would be even lower than Q2, unless there are a few surprises!
The EDA market in India, as per the ISA F&S Report 2005, was US$110m. The latest figures are not yet available, though I would believe the Indian EDA industry is likely to do better than the global industry, unless, there have been some slowdown effects here as well.
I had an interesting discussion with Jaswinder Ahuja, Corporate Vice President and Managing Director, Cadence Design Systems (I) Pvt. Ltd and Chairman, India Semiconductor Association (ISA), on the (dipping?) fortunes of the EDA industry lately.
According to Ahuja, 2008 has been a challenging year. The global financial crisis has impacted several industries and the EDA industry was no exception. Due to the overall downturn in the economy, companies are being more cautious and are delaying purchase decisions, a move that is impacting the overall EDA industry.
Coming to the drivers for EDA in India this year, there are a few key ones! First, the design centres have gained expertise and are now doing cutting-edge designs out of India. They have moved up the value chain from doing block-level design to increasingly owning up end-to-end design and design starts.
Second, several Indian design services companies have made significant acquisitions, showing that their businesses have not just taken root, but also flourished. MindTree Consulting’s acquisition of TES PV and Wipro’s acquisition of Oki's wireless chip design arm are cases in point, added Ahuja.
He said: "The Indian EDA industry has been growing and we will see more technology adoptions and proliferations in India Design Centers. Also, the rapidly growing local market is unfolding new opportunities."
EDA outlook 2009
Going forward, market pressures and design complexities are just some of the issues design teams face today. Cadence's customers, for instance, would like to plan in the context of IP selection, run analysis around power, performance and cost perspectives. Design predictability will be a priority, said Ahuja.
The key focus areas for the EDA industry will be new design for manufacturing technologies as designs move to advanced nodes; verification and verification IPs and multicore processing support for EDA flows as a result of increased integration.
Also, SaaS is likely to gain traction as companies are compelled to consider flexible engagement models to access state-of-the art design environments that help design teams reduce risk and cost, yet increase time-to-productivity.
Are there any opportunities for EDA folks in solar? Ahuja disclosed that in a recent poll by ISA, to the question 'Solar PV has potential in India', almost 90 percent of respondents replied Agree or Strongly Agree.
With the worldwide focus on alternative energy systems, India has witnessed several companies announcing investments in PV segment. This is good news for the Indian semiconductor ecosystem.
Cadence has a broad portfolio of technologies that addresses the needs of different players in the ecosystem.
Low power initiatives
Low power has always been a key focus area in semiconductors. According to Ahuja, power efficient design is gaining importance across the design chain and EDA companies will have to look closely at 'green' technologies.
Energy efficiency at the system and application level for wired and wireless products will be one of the focus areas. Emerging technologies that allow applications and systems developers to evaluate how their programs use power both individually and in a dynamic, multi-application model of the end system will help expand the role of EDA into system-level design.
The Power Forward Initiative (PFI), an industry alliance comprising of companies across the semiconductor design chain will work towards a more systematic, integrated approach to low-power design.
Outlook 2009
With the new year about to start in less than a week's time, the impact of the financial crisis will see an increased demand for mid-range product technology as consumers shift spend toward 'essential', rather than 'desirable' electronic products.
As per Ahuja, globally, semiconductor companies are focusing on their core strengths, consolidating and realigning resources. Across sectors, they will look for systems that marry functionality with cost efficiencies.
"Growth for semiconductor companies will come from energy related and low-power technologies that are able to drive market share shifts," he noted.
If you visited EDA Consortium's web site, this becomes clear. In Q1-08, the global EDA industry revenue for Q1 2008 declined 1.2 percent to $1,350.7 million compared to $1,366.8 million in Q1 2007.
Later, the EDA industry revenue for Q2 2008 declined 3.7 percent to $1357.4 million compared to $1408.8 million in Q2 2007, as reported by the EDA Consortium.
I am still waiting to see how the Q3 results shape up. My guess is, it would be even lower than Q2, unless there are a few surprises!
The EDA market in India, as per the ISA F&S Report 2005, was US$110m. The latest figures are not yet available, though I would believe the Indian EDA industry is likely to do better than the global industry, unless, there have been some slowdown effects here as well.
I had an interesting discussion with Jaswinder Ahuja, Corporate Vice President and Managing Director, Cadence Design Systems (I) Pvt. Ltd and Chairman, India Semiconductor Association (ISA), on the (dipping?) fortunes of the EDA industry lately.According to Ahuja, 2008 has been a challenging year. The global financial crisis has impacted several industries and the EDA industry was no exception. Due to the overall downturn in the economy, companies are being more cautious and are delaying purchase decisions, a move that is impacting the overall EDA industry.
Coming to the drivers for EDA in India this year, there are a few key ones! First, the design centres have gained expertise and are now doing cutting-edge designs out of India. They have moved up the value chain from doing block-level design to increasingly owning up end-to-end design and design starts.
Second, several Indian design services companies have made significant acquisitions, showing that their businesses have not just taken root, but also flourished. MindTree Consulting’s acquisition of TES PV and Wipro’s acquisition of Oki's wireless chip design arm are cases in point, added Ahuja.
He said: "The Indian EDA industry has been growing and we will see more technology adoptions and proliferations in India Design Centers. Also, the rapidly growing local market is unfolding new opportunities."
EDA outlook 2009
Going forward, market pressures and design complexities are just some of the issues design teams face today. Cadence's customers, for instance, would like to plan in the context of IP selection, run analysis around power, performance and cost perspectives. Design predictability will be a priority, said Ahuja.
The key focus areas for the EDA industry will be new design for manufacturing technologies as designs move to advanced nodes; verification and verification IPs and multicore processing support for EDA flows as a result of increased integration.
Also, SaaS is likely to gain traction as companies are compelled to consider flexible engagement models to access state-of-the art design environments that help design teams reduce risk and cost, yet increase time-to-productivity.
Are there any opportunities for EDA folks in solar? Ahuja disclosed that in a recent poll by ISA, to the question 'Solar PV has potential in India', almost 90 percent of respondents replied Agree or Strongly Agree.
With the worldwide focus on alternative energy systems, India has witnessed several companies announcing investments in PV segment. This is good news for the Indian semiconductor ecosystem.
Cadence has a broad portfolio of technologies that addresses the needs of different players in the ecosystem.
Low power initiatives
Low power has always been a key focus area in semiconductors. According to Ahuja, power efficient design is gaining importance across the design chain and EDA companies will have to look closely at 'green' technologies.
Energy efficiency at the system and application level for wired and wireless products will be one of the focus areas. Emerging technologies that allow applications and systems developers to evaluate how their programs use power both individually and in a dynamic, multi-application model of the end system will help expand the role of EDA into system-level design.
The Power Forward Initiative (PFI), an industry alliance comprising of companies across the semiconductor design chain will work towards a more systematic, integrated approach to low-power design.
Outlook 2009
With the new year about to start in less than a week's time, the impact of the financial crisis will see an increased demand for mid-range product technology as consumers shift spend toward 'essential', rather than 'desirable' electronic products.
As per Ahuja, globally, semiconductor companies are focusing on their core strengths, consolidating and realigning resources. Across sectors, they will look for systems that marry functionality with cost efficiencies.
"Growth for semiconductor companies will come from energy related and low-power technologies that are able to drive market share shifts," he noted.
Monday, December 8, 2008
Altera strategy to partner with Indian design services firms
Turning my attention to the programmable logic market, I took advantage of my recent meeting with Jordan Plofsky, Senior Vice President Market, Altera Corp., during the Altera SOPC conference.
Programmable logic consumption in India has been estimated at between $20-$25 million in 2008, largely driven by strong growth in communications infrastructure and increased spending in the military sector. The Indian programmable logic market is likely to grow at a CAGR of 25 percent over the next three years.
Altera's India strategy
In this context, it will be interesting to note Altera's strategy within the Indian semiconductor industry.
Plofsky says that as multinational companies are transferring more design work to their R&D teams in India, local companies are expanding their range of products, and independent design service companies are capturing a bigger piece of the outsourced design pie, Altera forecasts the increased need for high quality application support.
He says: "Unlike other companies who have design services operations in India, which compete with the local independent design services, our strategy is to partner with the local India design services industry. We are expanding our direct and indirect support channels to provide higher quality services to our customers here."
Altera is also supporting the development of the education sector in India, which is modernizing to turn out well trained engineers to satisfy the appetite of the industry. "We also run industrial workshops and seminars, like the recent SOPC World in Bangalore and New Delhi, to educate the design community on the direction of semiconductor technology," adds Plofsky.
Altera has also set up Altera Joint Laboratories in leading universities across India to provide a better platform for undergraduates to grasp basics of programmability.
Role in solar?
With investments in solar/PV happening, is there a role for Altera and other FPGA companies? This is a question that I invariably ask everyone in the semiconductor industry!
According to Plofsky, one of the promising applications is smart metering. It is the practice of getting the users and the infrastructure to be power aware and then using different usage patterns to lower energy usage and energy costs by applying smart algorithms.
Addressing low-power design
Power consumption has always been a big concern for designers in all markets and Altera has a number of different solutions.
In the CPLD area, Altera announced its zero power MAX IIZ devices in late 2007. Offering the highest density and I/O count in packages as small as 5x5mm, compared to macrocell-based CPLDs, MAX IIZ devices allow designers to meet changing functional requirements and lower power while saving board space.
Consuming 75 percent less power than competing FPGAs, the Altera Cyclone III devices are the industry's first and only 65-nm low-cost FPGA family, and offer digital system designers an unprecedented combination of density, power and cost.
To address the low-power demands of high density customers, the Stratix III and Stratix IV family members feature Altera's patented Programmable Power Technology. This power-saving technology optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design. And in addition these designs can be converted to HardCopy ASIC devices that can reduce power consumption by 50-70 percent.
As for new products in the LTE, TD-SCDMA and NFC spaces, Plofsky says that with the new 40-nm devices, Altera is uniquely positioned to deliver solutions that provide the density, performance and power for these emerging applications. The combination of DSP blocks, memory and transceivers was optimized for these communication applications.
Roadmap beyond
Altera just announced its 40nm devices in May and it is said to be on target to deliver those devices by the end of 2008.
Adds Plofsky: "We have already started development work on smaller process geometries with test chips in fab now, but it is too early to go into any family detail at this time."
Programmable logic consumption in India has been estimated at between $20-$25 million in 2008, largely driven by strong growth in communications infrastructure and increased spending in the military sector. The Indian programmable logic market is likely to grow at a CAGR of 25 percent over the next three years.
Altera's India strategy
In this context, it will be interesting to note Altera's strategy within the Indian semiconductor industry.
Plofsky says that as multinational companies are transferring more design work to their R&D teams in India, local companies are expanding their range of products, and independent design service companies are capturing a bigger piece of the outsourced design pie, Altera forecasts the increased need for high quality application support.
He says: "Unlike other companies who have design services operations in India, which compete with the local independent design services, our strategy is to partner with the local India design services industry. We are expanding our direct and indirect support channels to provide higher quality services to our customers here."
Altera is also supporting the development of the education sector in India, which is modernizing to turn out well trained engineers to satisfy the appetite of the industry. "We also run industrial workshops and seminars, like the recent SOPC World in Bangalore and New Delhi, to educate the design community on the direction of semiconductor technology," adds Plofsky.
Altera has also set up Altera Joint Laboratories in leading universities across India to provide a better platform for undergraduates to grasp basics of programmability.
Role in solar?
With investments in solar/PV happening, is there a role for Altera and other FPGA companies? This is a question that I invariably ask everyone in the semiconductor industry!
According to Plofsky, one of the promising applications is smart metering. It is the practice of getting the users and the infrastructure to be power aware and then using different usage patterns to lower energy usage and energy costs by applying smart algorithms.
Addressing low-power design
Power consumption has always been a big concern for designers in all markets and Altera has a number of different solutions.
In the CPLD area, Altera announced its zero power MAX IIZ devices in late 2007. Offering the highest density and I/O count in packages as small as 5x5mm, compared to macrocell-based CPLDs, MAX IIZ devices allow designers to meet changing functional requirements and lower power while saving board space.
Consuming 75 percent less power than competing FPGAs, the Altera Cyclone III devices are the industry's first and only 65-nm low-cost FPGA family, and offer digital system designers an unprecedented combination of density, power and cost.
To address the low-power demands of high density customers, the Stratix III and Stratix IV family members feature Altera's patented Programmable Power Technology. This power-saving technology optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design. And in addition these designs can be converted to HardCopy ASIC devices that can reduce power consumption by 50-70 percent.
As for new products in the LTE, TD-SCDMA and NFC spaces, Plofsky says that with the new 40-nm devices, Altera is uniquely positioned to deliver solutions that provide the density, performance and power for these emerging applications. The combination of DSP blocks, memory and transceivers was optimized for these communication applications.
Roadmap beyond
Altera just announced its 40nm devices in May and it is said to be on target to deliver those devices by the end of 2008.
Adds Plofsky: "We have already started development work on smaller process geometries with test chips in fab now, but it is too early to go into any family detail at this time."
Saturday, October 11, 2008
TI's TPS62601 converter for telecom apps
This August, Texas Instruments India (TII) announced the industry's smallest and thinnest 500-mA, step-down DC/DC converter solution, the TPS62601 converter, for space-constrained applications.
According to TI, It gives portable designers the ability to add more features and functions on a handheld device. The high-efficiency power management IC is the first 6-MHz, 500-mA converter to achieve a 13-mm2 solution size with an ultra-thin 0.6-mm total height.
I caught up with Ramprasad Ananthaswamy, Director, Power Management Products, Texas Instruments India, to find out a bit more about this so-called industry's smallest and thinnest converter solution, and its essential design trends.
So what exactly is the TPS62601 power converter targeted toward? According to Ananthaswamy, the TPS62601, a high-efficiency power management IC is the first 6-MHz, 500-mA converter to achieve a 13mm2 solution size with an ultra-thin 0.6-mm total height.
The TPS62601 converter achieves up to 89-percent power efficiency and only 30-uA typical operating quiescent current, all from a 0.9x1.3mm chip scale package roughly the size of a flake of pepper. The synchronous, switch-mode device’s fixed frequency of 6 MHz allows the use of only one 0.47-uH inductor with a height of 0.6 m and two low-cost ceramic capacitors, without compromising performance and efficiency.
The device supports applications, such as memory modules, GPS modules, Bluetooth and Wi-Fi modules or other wireless micro-modules used in ultra-thin smart phones, digital still cameras, portable disk drives and media players.
Applications areas of this device include: Smart and media phones; Cell phones; Media players; Mobile Internet devices; DSCs; and Other portable communications devices.
This chip will help powering sources such as: WLAN modules; WiFi modules; Bluetooth modules; Memory modules; and Generic micro modules.
Essential design trends
There is a need to understand the essential design trends of the TPS62601 that makes it unique. Ananthaswamy added that the TPS62601 can deliver DC voltage regulation accuracy of +/- 1.5 percent. In addition, its excellent load transient response, wide input voltage range of 2.3V to 5.5V and 1.8V of output allows the device to effectively support single-rail voltage requirements as designers add new features and functions.
The converter also applies energy-saving techniques to help maximize battery run-time. For example, the converter automatically enters a power save mode during light-load operating conditions via an automatic pulse frequency modulation and pulse width modulation switching feature. In shutdown mode, the device’s current consumption is reduced to less than 1 uA.
Size and high-performance are important. The converter achieves up to 89-percent power efficiency and only 30-uA typical operating quiescent current, from a small chip scale package.
A high switching frequency of 6MHz reduces the size of the external components used around this chip, thereby reducing the total size of the power solution. A low quiescent current of 30 uA also makes it very attractive for portable applications requiring long run times.
Helping portable designers
Let us understand how the TPS62601 will actually enable the portable designers to add more features and functions on to a handheld device. Ananthaswamy says: "Portable system designers continue to desire more features on their devices, which require smaller, efficient DC/DC converters to maintain long battery life and system run-times. As the size of the total power solution is small, more PCB space becomes available for additional features that need to get added on to the cell phone. The TPS62601 gives portable designers access to the smallest, thinnest 500-mA DC/DC solution, which simplifies design and reduces board space and time-to-market."
The converter also applies energy-saving techniques to help maximize battery run-time. For example, the converter automatically enters a power save mode during light-load operating conditions via an automatic pulse frequency modulation and pulse width modulation switching feature. In shutdown mode, the device’s current consumption is reduced to less than 1uA.
Power management
How well does the TPS62601 tackle power management issues? The biggest issue inside feature rich cell phones today is thermal management. This power converter, consuming only 30uA for its own operation, manages the thermal problem through efficient power conversion. "Better efficiency means less heat," added Ramaswamy.
Energy-saving techniques
Elaborate on the energy-saving techniques that can help maximize battery run-time, he said: "Globally, switching regulators are efficient means of power conversion. This device is a buck derived switching regulator that efficiently converts the single cell Li-ion battery voltage to the one that is required by the various multimedia rich cell phone chips, like applications processors, GPS modules, digital multimedia broadcast chips, camera engines, WiFi etc.
"It can power all of these chips, while consuming as little as 30uA for its own operation. Depending on the input to output voltage ration, the conversion efficiency can also reach close to 90 percent. Less consumption, better conversion efficiencies, etc., all of these result in longer battery run times."
Is it then safe to say that the maximizing battery run-time problem has been tackled with the TPS62601? Not exactly!!
According to Ramaswamy, the TPS62601 addresses part of the battery run-time issue. "With this initiative, TI has gone a step ahead in making the battery last longer," he noted.
Making power converters efficient is only a part of the battery run-time issue. Along with making power converters efficient, one also has to look at how much power is consumed by the various chips that are used in a cell phone, the operating system that runs the cell phone and the overall power saving features that are built into the cell phone system. The speaker volume settings, backlight brightness settings and the duration of the backlight and some of the other user friendly settings have an effect on the battery run times.
According to TI, It gives portable designers the ability to add more features and functions on a handheld device. The high-efficiency power management IC is the first 6-MHz, 500-mA converter to achieve a 13-mm2 solution size with an ultra-thin 0.6-mm total height.
I caught up with Ramprasad Ananthaswamy, Director, Power Management Products, Texas Instruments India, to find out a bit more about this so-called industry's smallest and thinnest converter solution, and its essential design trends.So what exactly is the TPS62601 power converter targeted toward? According to Ananthaswamy, the TPS62601, a high-efficiency power management IC is the first 6-MHz, 500-mA converter to achieve a 13mm2 solution size with an ultra-thin 0.6-mm total height.
The TPS62601 converter achieves up to 89-percent power efficiency and only 30-uA typical operating quiescent current, all from a 0.9x1.3mm chip scale package roughly the size of a flake of pepper. The synchronous, switch-mode device’s fixed frequency of 6 MHz allows the use of only one 0.47-uH inductor with a height of 0.6 m and two low-cost ceramic capacitors, without compromising performance and efficiency.
The device supports applications, such as memory modules, GPS modules, Bluetooth and Wi-Fi modules or other wireless micro-modules used in ultra-thin smart phones, digital still cameras, portable disk drives and media players.
Applications areas of this device include: Smart and media phones; Cell phones; Media players; Mobile Internet devices; DSCs; and Other portable communications devices.
This chip will help powering sources such as: WLAN modules; WiFi modules; Bluetooth modules; Memory modules; and Generic micro modules.
Essential design trends
There is a need to understand the essential design trends of the TPS62601 that makes it unique. Ananthaswamy added that the TPS62601 can deliver DC voltage regulation accuracy of +/- 1.5 percent. In addition, its excellent load transient response, wide input voltage range of 2.3V to 5.5V and 1.8V of output allows the device to effectively support single-rail voltage requirements as designers add new features and functions.
The converter also applies energy-saving techniques to help maximize battery run-time. For example, the converter automatically enters a power save mode during light-load operating conditions via an automatic pulse frequency modulation and pulse width modulation switching feature. In shutdown mode, the device’s current consumption is reduced to less than 1 uA.
Size and high-performance are important. The converter achieves up to 89-percent power efficiency and only 30-uA typical operating quiescent current, from a small chip scale package.
A high switching frequency of 6MHz reduces the size of the external components used around this chip, thereby reducing the total size of the power solution. A low quiescent current of 30 uA also makes it very attractive for portable applications requiring long run times.
Helping portable designers
Let us understand how the TPS62601 will actually enable the portable designers to add more features and functions on to a handheld device. Ananthaswamy says: "Portable system designers continue to desire more features on their devices, which require smaller, efficient DC/DC converters to maintain long battery life and system run-times. As the size of the total power solution is small, more PCB space becomes available for additional features that need to get added on to the cell phone. The TPS62601 gives portable designers access to the smallest, thinnest 500-mA DC/DC solution, which simplifies design and reduces board space and time-to-market."
The converter also applies energy-saving techniques to help maximize battery run-time. For example, the converter automatically enters a power save mode during light-load operating conditions via an automatic pulse frequency modulation and pulse width modulation switching feature. In shutdown mode, the device’s current consumption is reduced to less than 1uA.
Power management
How well does the TPS62601 tackle power management issues? The biggest issue inside feature rich cell phones today is thermal management. This power converter, consuming only 30uA for its own operation, manages the thermal problem through efficient power conversion. "Better efficiency means less heat," added Ramaswamy.
Energy-saving techniques
Elaborate on the energy-saving techniques that can help maximize battery run-time, he said: "Globally, switching regulators are efficient means of power conversion. This device is a buck derived switching regulator that efficiently converts the single cell Li-ion battery voltage to the one that is required by the various multimedia rich cell phone chips, like applications processors, GPS modules, digital multimedia broadcast chips, camera engines, WiFi etc.
"It can power all of these chips, while consuming as little as 30uA for its own operation. Depending on the input to output voltage ration, the conversion efficiency can also reach close to 90 percent. Less consumption, better conversion efficiencies, etc., all of these result in longer battery run times."
Is it then safe to say that the maximizing battery run-time problem has been tackled with the TPS62601? Not exactly!!
According to Ramaswamy, the TPS62601 addresses part of the battery run-time issue. "With this initiative, TI has gone a step ahead in making the battery last longer," he noted.
Making power converters efficient is only a part of the battery run-time issue. Along with making power converters efficient, one also has to look at how much power is consumed by the various chips that are used in a cell phone, the operating system that runs the cell phone and the overall power saving features that are built into the cell phone system. The speaker volume settings, backlight brightness settings and the duration of the backlight and some of the other user friendly settings have an effect on the battery run times.
Monday, September 22, 2008
Despite EDA challenges, Mentor keeps faith on India
Great! All of these EDA firms, despite their current financial woes, remain strong and bullish on India! Mentor Graphics is no exception in this case!
It is well documented that the global EDA industry, along with the global semiconductor industry, has not had a smooth ride this year. However, this situation has only made both the industries work harder toward restoring some recovery.
Thanks to Veeresh Shetty, a dear friend, and Marcom Manager-Pacrim South, Mentor Graphics, I had the pleasure of meeting up with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics Corp., during the recently held EDA Tech Forum in Bangalore.
We discussed a range of issues, such as the state of the EDA industry, Mentor's focus on India, and low-power design challenges. I did not discuss the proposed acquisition of Mentor by Cadence, as I feel it is no point in going over what was never on the cards, at least, for now.
According to Sawicki, Mentor Graphics is very optimistic about semiconductors and electronics, especially in India. "The EDA industry is currently having a pretty challenging environment. The recession in 2002 was the deepest in its history," he says.
"We (the EDA industry) haven't had the growth rates we would like. However, we have done better. We have re-invented Mentor," adds Sawicki. "We have now invested more in back-and-route ICs, which is about 40 percent of our revenue. Our product portfolio is the youngest within the company." He adds that the recession has been more in semiconductors. However, take out memory, and the scenario changes.
The drive of the semiconductor industry toward smaller and smaller features sizes requires more sophisticated correction methods to guarantee the final tolerances for the etched features in both wafer manufacturing and mask making.
Flat growth likely for EDA
Commenting on EDA industry's growth, Sawicki, adds that growth will be flat in 2008. Interestingly, the growth rate for EDA was 10 percent during the last two years. He notes: "EDA always does best when it delivers new technology. There are two reasons. One, on the manufacturing side of things. The extra results will be completely delivered by the software."
The other reason is that the aspects of manufacturing power and manageability will assume great importance. "Finally, the ESL space also provides the potential for growth. It also brings out a whole new design capability," he notes.
Given the global semiconductor scenario, Mentor is also looking at other markets outside semiconductors, especially automotive. Sawicki adds that this quarter, 20 percent of Mentor's business has been from the automotive segment.
There have been several global initiatives aimed at consolidation in the recent past. Sawicki says: "Consolidation should not be looked at as a goal. We also do acquisitions in the technology space. It augments a strong position."
So what are some of the other challenges facing the industry? Sawicki lists those as the economics of the industry itself, especially the design and verification costs.
On low power design, Sawicki agrees that there has been a transition of electronics from the US to Asia. "You have got to handle far lower power downward. We can reduce leakage current by 20-30 percent. Looking forward, how do you tie in ESL with physical design? When doing ESL, you can do architectural exploration. I will have my ESL to drive the place-and-route tool. I can get fast execution as well as low leakage power."
He advises that India has the ability to go beyond the innovation that has been happening.
Mentor in India
Mentor Graphics has three sites in India. It has R&D centers in Hyderabad and Noida, near New Delhi, and a sales and support office in Bangalore. The Hyderabad R&D center handles system design, while the Noida R&D center takes care of the front-end side, such as functional verification products.
Raghu Panicker, sales director, India, Mentor Graphics, says that the company has been very bullish on India. "We do not see any lull anywhere. Lot of design starts are happening here, in India," he adds.
I will continue my conversation with Joseph Sawicki in the next blog!
It is well documented that the global EDA industry, along with the global semiconductor industry, has not had a smooth ride this year. However, this situation has only made both the industries work harder toward restoring some recovery.
Thanks to Veeresh Shetty, a dear friend, and Marcom Manager-Pacrim South, Mentor Graphics, I had the pleasure of meeting up with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics Corp., during the recently held EDA Tech Forum in Bangalore.We discussed a range of issues, such as the state of the EDA industry, Mentor's focus on India, and low-power design challenges. I did not discuss the proposed acquisition of Mentor by Cadence, as I feel it is no point in going over what was never on the cards, at least, for now.
According to Sawicki, Mentor Graphics is very optimistic about semiconductors and electronics, especially in India. "The EDA industry is currently having a pretty challenging environment. The recession in 2002 was the deepest in its history," he says.
"We (the EDA industry) haven't had the growth rates we would like. However, we have done better. We have re-invented Mentor," adds Sawicki. "We have now invested more in back-and-route ICs, which is about 40 percent of our revenue. Our product portfolio is the youngest within the company." He adds that the recession has been more in semiconductors. However, take out memory, and the scenario changes.
The drive of the semiconductor industry toward smaller and smaller features sizes requires more sophisticated correction methods to guarantee the final tolerances for the etched features in both wafer manufacturing and mask making.
Flat growth likely for EDA
Commenting on EDA industry's growth, Sawicki, adds that growth will be flat in 2008. Interestingly, the growth rate for EDA was 10 percent during the last two years. He notes: "EDA always does best when it delivers new technology. There are two reasons. One, on the manufacturing side of things. The extra results will be completely delivered by the software."
The other reason is that the aspects of manufacturing power and manageability will assume great importance. "Finally, the ESL space also provides the potential for growth. It also brings out a whole new design capability," he notes.
Given the global semiconductor scenario, Mentor is also looking at other markets outside semiconductors, especially automotive. Sawicki adds that this quarter, 20 percent of Mentor's business has been from the automotive segment.
There have been several global initiatives aimed at consolidation in the recent past. Sawicki says: "Consolidation should not be looked at as a goal. We also do acquisitions in the technology space. It augments a strong position."
So what are some of the other challenges facing the industry? Sawicki lists those as the economics of the industry itself, especially the design and verification costs.
On low power design, Sawicki agrees that there has been a transition of electronics from the US to Asia. "You have got to handle far lower power downward. We can reduce leakage current by 20-30 percent. Looking forward, how do you tie in ESL with physical design? When doing ESL, you can do architectural exploration. I will have my ESL to drive the place-and-route tool. I can get fast execution as well as low leakage power."
He advises that India has the ability to go beyond the innovation that has been happening.
Mentor in India
Mentor Graphics has three sites in India. It has R&D centers in Hyderabad and Noida, near New Delhi, and a sales and support office in Bangalore. The Hyderabad R&D center handles system design, while the Noida R&D center takes care of the front-end side, such as functional verification products.
Raghu Panicker, sales director, India, Mentor Graphics, says that the company has been very bullish on India. "We do not see any lull anywhere. Lot of design starts are happening here, in India," he adds.
I will continue my conversation with Joseph Sawicki in the next blog!
Friday, September 12, 2008
Synopsys' Dr Chi-Foon Chan on India, low power design and solar
There have been reports about the troubles within the EDA industry in recent times, especially those related with quarter sales. Interestingly, Synopsys has been the one sailing along fine! If that's not enough, it made its intention known of playing a role on the solar/PV segment, an area where lot of investments have been happening!
Given this scenario, I was fortuitous enough, rather, extremely lucky to be able to get into a conversation with Dr. Chi-Foon Chan, President and Chief Operating Officer, Synopsys Inc., during his recent visit to India.
On the state of the global semiconductor industry, he said, it was somewhere now in the low 10s [well below 10 percent]. The EDA industry is currently tracking below that level. However, Synopsys has been growing at around 10 percent. He said, "The technology challenges today are very high."
Synopsys has a substantial number of R&D population based out of India. Giving his assessment of the Indian semiconductor industry, Dr. Chan added: "Our main interest in India is largely talent and the academia. India can very well get more into the product development side. Even the outsourcing of designs have increased. Our capabilities, of the Indian team, have also increased."
As with any good semiconductor ecosystem, the Indian industry also needs a proactive industry association, a role played to near perfection by the ISA (India Semiconductor Association). Acknowledging the ISA's role, Dr. Chan said, "The ISA has also formed a very cohesive team."
There is little doubt about India's growing importance in technology strengths and managerial leadership. Dr. Chan added: "We are more on the high-end side and also track what others design. In India, the profiles of designs are definitely high-end in nature. This is largely due to the presence of a large number of MNCs. A very high percentage of designs are in the 45nm and 65nm process technology nodes."
There is another significant indicator of India's growing importance, and that is the huge rise in the attendance of the SNUG. In 2000, this event attracted 180 people. However, in 2008, the SNUG attracted over 2,000 people.
Moving India to next level
Given the very high level of commitment on Synopsys' part toward India, there was a need to find out from Dr. Chan what exactly India needs to do to move to the next level in the value chain in the semiconductor ecosystem.
He advised: "India can do two to three things. One, for the system to grow, you need the government, academia and industry to grow together. India has all of the ingredients required to drive products."
Comparing India with China, he highlighted the fact that while in China, the local consumption was higher than local supply, that was not the case with India!
"Therefore, looking at merely the local market is not the only thing. Products developed here can also be targeted at the Middle East and Southeast Asia." He was quite forthright in his analysis, adding: "Industries start when you find markets. The skill sets are already present here. There can well be multiple startups."
Dr. Chan also touched upon the fab vs. fabless issue, noting that there could well be more of fabless companies in India. "Building a fab requires lot of capital. Also, consolidation will continue to happen."
What role does Dr. Chan see Synopsys playing in the Indian context? He said: "Synopsys will continue to be a catalyst for the industry. A healthy design industry in India continues to help us. We also work well with the Indian universities. Having more people from the universities will always help. We also invest a lot in application support. The application team also trains others. I now look forward to seeing more fabless companies here and India to become even more global."
On low power design
India is also a centre of expertise in low power design, given that low power is hugely important in today's electronics ecosystem. Dr. Chan commented that low power has always been the number one design issue. It cannot be taken care of at one single stage.
He added: "A slightly new concept that has emerged is low-power verification. There are so many schemes for attacking low power, such as multiple voltage islands. We (Synopsys) are spending a lot of effort in low power.
"As a designer, you require detailed analysis. Low-power verification is now coming up. Another area is testing. As an example, if so much power is required, how do you have the power cut from the tool you are using to test? From a Synopsys point of view, we are involved in several points, such as front-end synthesis, testing, sign-off, verification, etc. We are trying to put in a whole lot of methodologies."
Synopsys in solar
EDA may be able to help by lowering power requirements and leakage on better products. Especially, the Synopsys' TCAD product can be used to create more efficient and effective solar cells. Now, this is not a new development anymore. Synopsys, along with Magma, have already made known their intentions about setting foot in the solar/PV space.
On the TCAD, Dr. Chan said: "We have a very strong position in the TCAD, commercially. Now, it is one of our most critical elements in high-performance. Our TCAD is among the strongest in the EDA industry.
"In solar, it does not have to be a complicated place-and-route, etc. From an entire solar industry point of view, we have now used some effort from TCAD into this space. Heat transfer issues, etc., are more in the EDA space."
I will continue my conversation with Synopsys on its solar initiative sometime later. Keep watching this space, folks
Given this scenario, I was fortuitous enough, rather, extremely lucky to be able to get into a conversation with Dr. Chi-Foon Chan, President and Chief Operating Officer, Synopsys Inc., during his recent visit to India.On the state of the global semiconductor industry, he said, it was somewhere now in the low 10s [well below 10 percent]. The EDA industry is currently tracking below that level. However, Synopsys has been growing at around 10 percent. He said, "The technology challenges today are very high."
Synopsys has a substantial number of R&D population based out of India. Giving his assessment of the Indian semiconductor industry, Dr. Chan added: "Our main interest in India is largely talent and the academia. India can very well get more into the product development side. Even the outsourcing of designs have increased. Our capabilities, of the Indian team, have also increased."
As with any good semiconductor ecosystem, the Indian industry also needs a proactive industry association, a role played to near perfection by the ISA (India Semiconductor Association). Acknowledging the ISA's role, Dr. Chan said, "The ISA has also formed a very cohesive team."
There is little doubt about India's growing importance in technology strengths and managerial leadership. Dr. Chan added: "We are more on the high-end side and also track what others design. In India, the profiles of designs are definitely high-end in nature. This is largely due to the presence of a large number of MNCs. A very high percentage of designs are in the 45nm and 65nm process technology nodes."
There is another significant indicator of India's growing importance, and that is the huge rise in the attendance of the SNUG. In 2000, this event attracted 180 people. However, in 2008, the SNUG attracted over 2,000 people.
Moving India to next level
Given the very high level of commitment on Synopsys' part toward India, there was a need to find out from Dr. Chan what exactly India needs to do to move to the next level in the value chain in the semiconductor ecosystem.
He advised: "India can do two to three things. One, for the system to grow, you need the government, academia and industry to grow together. India has all of the ingredients required to drive products."
Comparing India with China, he highlighted the fact that while in China, the local consumption was higher than local supply, that was not the case with India!
"Therefore, looking at merely the local market is not the only thing. Products developed here can also be targeted at the Middle East and Southeast Asia." He was quite forthright in his analysis, adding: "Industries start when you find markets. The skill sets are already present here. There can well be multiple startups."
Dr. Chan also touched upon the fab vs. fabless issue, noting that there could well be more of fabless companies in India. "Building a fab requires lot of capital. Also, consolidation will continue to happen."
What role does Dr. Chan see Synopsys playing in the Indian context? He said: "Synopsys will continue to be a catalyst for the industry. A healthy design industry in India continues to help us. We also work well with the Indian universities. Having more people from the universities will always help. We also invest a lot in application support. The application team also trains others. I now look forward to seeing more fabless companies here and India to become even more global."
On low power design
India is also a centre of expertise in low power design, given that low power is hugely important in today's electronics ecosystem. Dr. Chan commented that low power has always been the number one design issue. It cannot be taken care of at one single stage.
He added: "A slightly new concept that has emerged is low-power verification. There are so many schemes for attacking low power, such as multiple voltage islands. We (Synopsys) are spending a lot of effort in low power.
"As a designer, you require detailed analysis. Low-power verification is now coming up. Another area is testing. As an example, if so much power is required, how do you have the power cut from the tool you are using to test? From a Synopsys point of view, we are involved in several points, such as front-end synthesis, testing, sign-off, verification, etc. We are trying to put in a whole lot of methodologies."
Synopsys in solar
EDA may be able to help by lowering power requirements and leakage on better products. Especially, the Synopsys' TCAD product can be used to create more efficient and effective solar cells. Now, this is not a new development anymore. Synopsys, along with Magma, have already made known their intentions about setting foot in the solar/PV space.
On the TCAD, Dr. Chan said: "We have a very strong position in the TCAD, commercially. Now, it is one of our most critical elements in high-performance. Our TCAD is among the strongest in the EDA industry.
"In solar, it does not have to be a complicated place-and-route, etc. From an entire solar industry point of view, we have now used some effort from TCAD into this space. Heat transfer issues, etc., are more in the EDA space."
I will continue my conversation with Synopsys on its solar initiative sometime later. Keep watching this space, folks
Thursday, August 14, 2008
Xilinx on microprocessor trends, solar/PV
This semicon blog will basically examine the key trends in microprocessors, as well as whether companies such as Xilinx -- a key player in FPGAs -- has any kind of role to play in the solar/PV domain.
For the record, this is the concluding part of the discussion with Vincent Ratford, Senior Vice President, Solutions Development Group, Xilinx.
First, on to solar/PV! We have been reading and hearing a lot about the rapid advances being made in solar/PV. With so much investments in solar/PV happening globally, is there a role for Xilinx to play in this segment?
Ratford said: "Perhaps! Our devices are great for prototyping new ideas and often find their way into new markets. In base stations, our devices are used to reduce the power up to 50 percent. In signal processing applications, we have a decided performance/power advantage vs. discrete signal processors. Many of these 'Green' applications require some form of signal and embedded processing." Interesting, and this point needs some further examination!
Another area of main concern within the global semiconductor industry is low-power design. According to Ratford, there are a variety of ways to save system power.
He added: "We are designing features in our new products that will reduce active and standby power. We also have power-estimation and optimization tools. I would say, there is a lot more to be done in this area at all levels, software, IP and silicon."
Ratford was however, tight-lipped about Xilinx's product roadmap beyond the Virtex V. Obviously, we need to remain very tuned toward this!
Key microprocessor trends
Now this is another interesting area. A few weeks ago, I had received a great article from Texas Instruments, which mentioned about five key microprocessor trends today.
Microprocessors have always been among the key areas of interest for semiconductor design and development. On being quizzed on what could be the five major trends for microprocessors, Xilinx's Ratford said: "For our embedded customers it is:
* Rising adoption of Linux.
* Increasing use of multi-core and some multi-processing.
* Accelerating trend to increase the connectivity, bandwidth and reduce the latency between the processor and the FPGA.
* Improve the OOBE (Out of the Box Experience) for non-FPGA developers.
* Reduce power.
Before signing off, my thoughts also veered toward LTE and TD-SCDMA, one 4G and the other, a 3G technology. Both these technologies have been very much in the news lately, especially, TD-SCDMA, which is currently in use at the Beijing Olympics.
As expected, Xilinx has also forayed into both LTE and TD-SCDMA spaces!
Ratford said: "Yes, we have complete reference designs for LTE and TD-SCDMA and have secured most of the prototype sockets for these air interface standards with Virtex-5. We have a very strong IP portfolio for the radio shelf and baseband and our Sytem Generator and AccelDSP tools are used extensively."
For the record, this is the concluding part of the discussion with Vincent Ratford, Senior Vice President, Solutions Development Group, Xilinx.
First, on to solar/PV! We have been reading and hearing a lot about the rapid advances being made in solar/PV. With so much investments in solar/PV happening globally, is there a role for Xilinx to play in this segment?
Ratford said: "Perhaps! Our devices are great for prototyping new ideas and often find their way into new markets. In base stations, our devices are used to reduce the power up to 50 percent. In signal processing applications, we have a decided performance/power advantage vs. discrete signal processors. Many of these 'Green' applications require some form of signal and embedded processing." Interesting, and this point needs some further examination!
Another area of main concern within the global semiconductor industry is low-power design. According to Ratford, there are a variety of ways to save system power.
He added: "We are designing features in our new products that will reduce active and standby power. We also have power-estimation and optimization tools. I would say, there is a lot more to be done in this area at all levels, software, IP and silicon."
Ratford was however, tight-lipped about Xilinx's product roadmap beyond the Virtex V. Obviously, we need to remain very tuned toward this!
Key microprocessor trends
Now this is another interesting area. A few weeks ago, I had received a great article from Texas Instruments, which mentioned about five key microprocessor trends today.
Microprocessors have always been among the key areas of interest for semiconductor design and development. On being quizzed on what could be the five major trends for microprocessors, Xilinx's Ratford said: "For our embedded customers it is:
* Rising adoption of Linux.
* Increasing use of multi-core and some multi-processing.
* Accelerating trend to increase the connectivity, bandwidth and reduce the latency between the processor and the FPGA.
* Improve the OOBE (Out of the Box Experience) for non-FPGA developers.
* Reduce power.
Before signing off, my thoughts also veered toward LTE and TD-SCDMA, one 4G and the other, a 3G technology. Both these technologies have been very much in the news lately, especially, TD-SCDMA, which is currently in use at the Beijing Olympics.
As expected, Xilinx has also forayed into both LTE and TD-SCDMA spaces!
Ratford said: "Yes, we have complete reference designs for LTE and TD-SCDMA and have secured most of the prototype sockets for these air interface standards with Virtex-5. We have a very strong IP portfolio for the radio shelf and baseband and our Sytem Generator and AccelDSP tools are used extensively."
Tuesday, July 1, 2008
Tackling low-power design issues -- Synopsys
Managing power efficiently is not a choice, but an imperative. Semiconductor content is increasing everywhere, and in fact, consumers and globalization are driving the semiconductor content in electronic systems.
A glance at the ecosystem pyramid reveals that the global electronics industry stands at US$3,200 billion, semiconductors at US$274 billion, equipment and materials at US$86 billion, and EDA at US$4.4 billion. EDA is at the heart of the electronics industry.
Subhash Bal, country director, Synopsys (India) EDA Software Pvt. Ltd, says that for low power imperatives, it is important to look at systemic factors. Energy usage and carbon emissions, especially, have been growing alarmingly, and will continue to do so for quite some time. This is largely due to uncontrolled consumption of devices and other electronic equipment. "We need to support energy usage without carbon emissions. In that respect, solar is a good solution," he adds.
Computing is energy intensive by nature. Consider these stats -- approximately 1 billion of the world's PCs are switched on for nine hours per day, requiring 95,000MW. And of the US$250 billion spent globally each year powering computers, about 85 percent of that energy is wasted, while the computer stands idle.
Today, more devices and gadgets are being introduced, with more features and at lower prices. All of these devices demand a huge amount of battery power. Speed increases at the expense of energy consumption. Leakage has also become a major issue. There is therefore a growing need to solve power-related problems.
The Synopsys Sentaurus
Synopsys' Sentaurus optimizes a device's power. It also addresses photovoltaics. The Sentaurus process is an advanced 1D, 2D, and 3D process simulator for developing and optimizing silicon and compound semiconductor process technologies.
Created by combining features from Synopsys and former ISE TCAD products, together with a wide range of new features and capabilities, Sentaurus is a new-generation process simulator for addressing the challenges found in current and future process technologies. "The Sentaurus takes care of the processing part. It does modeling, 2D/3D simulation, etc. It can be applied to both semiconductors and solar," says Bal.
Eclypse low-power solution
Synopsys' goal is to deliver the most comprehensive solution, enabling designers to build the most advanced, low power chips and systems in the world. In the hope of achieving this, it has introduced the Eclypse low-power solution. Sharat D Kaul, sales and marketing manager, Synopsys India, highlights the fact that the Eclypse looks at the design side specifically.
The silicon-level concerns include factors such as more functionality, more computing power, limited power budget, design complexity, verification complexity, testing, reliability and schedule. System-level concerns include factors such as battery life, system cooling, reliability, packaging cost, operating cost, air conditioning cost, carbon footprint and green initiatives. Most design teams are both overwhelmed and under prepared.
The Eclypse low power solution is aimed at addressing such needs. It provides an alignment of technology, IP, methodology, services and industry standards -- geared to meet the challenges of advanced low power designs.
Eclypse supports the industry-standard Unified Power Format (UPF) language, used to capture low power design requirements. It offers low power education programs, end-to-end UPF support, multi-voltage verification with assertions, automated clock tree synthesis, and automated power switch optimization.
A glance at the ecosystem pyramid reveals that the global electronics industry stands at US$3,200 billion, semiconductors at US$274 billion, equipment and materials at US$86 billion, and EDA at US$4.4 billion. EDA is at the heart of the electronics industry.
Subhash Bal, country director, Synopsys (India) EDA Software Pvt. Ltd, says that for low power imperatives, it is important to look at systemic factors. Energy usage and carbon emissions, especially, have been growing alarmingly, and will continue to do so for quite some time. This is largely due to uncontrolled consumption of devices and other electronic equipment. "We need to support energy usage without carbon emissions. In that respect, solar is a good solution," he adds.
Computing is energy intensive by nature. Consider these stats -- approximately 1 billion of the world's PCs are switched on for nine hours per day, requiring 95,000MW. And of the US$250 billion spent globally each year powering computers, about 85 percent of that energy is wasted, while the computer stands idle.
Today, more devices and gadgets are being introduced, with more features and at lower prices. All of these devices demand a huge amount of battery power. Speed increases at the expense of energy consumption. Leakage has also become a major issue. There is therefore a growing need to solve power-related problems.
The Synopsys Sentaurus
Synopsys' Sentaurus optimizes a device's power. It also addresses photovoltaics. The Sentaurus process is an advanced 1D, 2D, and 3D process simulator for developing and optimizing silicon and compound semiconductor process technologies.
Created by combining features from Synopsys and former ISE TCAD products, together with a wide range of new features and capabilities, Sentaurus is a new-generation process simulator for addressing the challenges found in current and future process technologies. "The Sentaurus takes care of the processing part. It does modeling, 2D/3D simulation, etc. It can be applied to both semiconductors and solar," says Bal.
Eclypse low-power solution
Synopsys' goal is to deliver the most comprehensive solution, enabling designers to build the most advanced, low power chips and systems in the world. In the hope of achieving this, it has introduced the Eclypse low-power solution. Sharat D Kaul, sales and marketing manager, Synopsys India, highlights the fact that the Eclypse looks at the design side specifically.
The silicon-level concerns include factors such as more functionality, more computing power, limited power budget, design complexity, verification complexity, testing, reliability and schedule. System-level concerns include factors such as battery life, system cooling, reliability, packaging cost, operating cost, air conditioning cost, carbon footprint and green initiatives. Most design teams are both overwhelmed and under prepared.
The Eclypse low power solution is aimed at addressing such needs. It provides an alignment of technology, IP, methodology, services and industry standards -- geared to meet the challenges of advanced low power designs.
Eclypse supports the industry-standard Unified Power Format (UPF) language, used to capture low power design requirements. It offers low power education programs, end-to-end UPF support, multi-voltage verification with assertions, automated clock tree synthesis, and automated power switch optimization.
Wednesday, June 18, 2008
EDA as DNA of growth
The EDA industry today is abuzz with the proposed takeover bid by Cadence Design Systems for Mentor Graphics, and the reported rejection of that bid by Mentor.
This is a consolidation within the EDA industry waiting to happen. My gut feeling is that it will happen, though it may take some more time.
Those in the semiconductor space are well aware of the role EDA plays as far as chip designing is concerned. With India's growing might in semiconductors, the EDA companies in India are witnessing consumption rising than ever before.
I recently happened to get into a discussion with Rahul Arya, Marketing Director, Cadence Design Systems (I) Pvt. Ltd, on how the industry has been performing, and how are the EDA companies addressing the design challenges, a few days before the Cadence-Mentor story surfaced.
Following the semiconductor industry trends, the consumption of EDA technologies is growing in regions outside of the US and Europe. According to Arya, the size of the EDA market worldwide is estimated to be about US $5 billion today.
The top three EDA companies -- Cadence, Mentor and Synopsys -- command three-quarters share of the entire EDA market worldwide. Imagine, what it would do to the EDA industry and to Cadence, if Cadence were to take over Mentor!
EDA in India
Coming to the status of the EDA industry in India, it is a pretty good reflection of what's happening worldwide. The industry in India is growing and it is healthy. As per the ISA F&S Report 2005, the EDA market in India was estimated at US$110m.
The reasons for this growth are multiple. For instance, Cadence's customers are growing and hence, so is Cadence. "With all of the major semiconductor MNCs having expanded their footprints by setting up India design centers, more EDA software is getting consumed in India. Indian design services are also growing. Also, some startups are coming up, like Cosmic Circuits, Sankalp, etc., and they are gaining momentum," added Arya.
So how exactly are the EDA companies addressing 45nm (and 32nm) design challenges? If you look at the work being done in India, it is now pretty cutting edge, and very comparable to the rest of the world.
Arya added: "Our customers are looking for the 3Cs -- complexity, cost and convergence. The end users are asking for more features. For example, in their mobile or any other electronic device, which is driving our customers to pack in more functionality on the chips.
"Our customers have multiple challenges at 45nm and below, notably low power, analog-mixed signal and Design for Manufacturing (DFM)."
Challenges in 45nm and below
And what are those? As the industry pushes toward smaller process geometries, the existing design infrastructure must be upgraded holistically to automate power-lowering design techniques. Most power-control methods in use today are manual and implemented ad hoc, leading to an increased risk and cost.
Across the design and manufacturing chain, an urgent need has emerged for an automated, power-aware design infrastructure. To facilitate and support a new era of low-power design innovation, Cadence has formed the Power Forward Initiative (PFI).
Drawing from the collective expertise of leading technology companies, the Power Forward Initiative will create a more systematic, integrated approach to low-power design, providing a platform for higher-level exploration and IP re-use.
The PFI members are already at work on validating the Common Power Format (CPF), a new open specification language that captures all power-specific design, constraint, and functionality requirements, such as multi-supply voltage and power shutoff, in a single file.
Arya noted: "By linking design, verification, and implementation domains, the Common Power Format enables automation of power-reduction techniques and increases predictability. No longer constrained by the risk of low yield or costly re-spins, design teams can focus their time and resources on what matters most —- innovation. Achieving both functional and structural verification before incurring manufacturing costs, and with greater time-to-market opportunities, companies across the design and manufacturing chain can adopt new process geometries and start low-power design projects profitably.
On the subject of DFM, EDA companies are trying their utmost to improve yield. Cadence is trying to bring lot of analysis early in the cycle. The designer has more visibility on those effects, before they get manufactured. It has a host of technology offerings to enable the designers make early decisions.
For example, Cadence has recently worked with TSMC on 9.0 reference flow. It has also worked with ARM on a low-power methodology. The idea is that an industry-wide collaboration will ensure that EDA companies like Cadence are able to provide value to customers.
As customers grapple with technology and time-to-market challenges, the EDA industry will be the DNA of growth.
This is a consolidation within the EDA industry waiting to happen. My gut feeling is that it will happen, though it may take some more time.
Those in the semiconductor space are well aware of the role EDA plays as far as chip designing is concerned. With India's growing might in semiconductors, the EDA companies in India are witnessing consumption rising than ever before.
I recently happened to get into a discussion with Rahul Arya, Marketing Director, Cadence Design Systems (I) Pvt. Ltd, on how the industry has been performing, and how are the EDA companies addressing the design challenges, a few days before the Cadence-Mentor story surfaced.
Following the semiconductor industry trends, the consumption of EDA technologies is growing in regions outside of the US and Europe. According to Arya, the size of the EDA market worldwide is estimated to be about US $5 billion today.
The top three EDA companies -- Cadence, Mentor and Synopsys -- command three-quarters share of the entire EDA market worldwide. Imagine, what it would do to the EDA industry and to Cadence, if Cadence were to take over Mentor!
EDA in India
Coming to the status of the EDA industry in India, it is a pretty good reflection of what's happening worldwide. The industry in India is growing and it is healthy. As per the ISA F&S Report 2005, the EDA market in India was estimated at US$110m.
The reasons for this growth are multiple. For instance, Cadence's customers are growing and hence, so is Cadence. "With all of the major semiconductor MNCs having expanded their footprints by setting up India design centers, more EDA software is getting consumed in India. Indian design services are also growing. Also, some startups are coming up, like Cosmic Circuits, Sankalp, etc., and they are gaining momentum," added Arya.
So how exactly are the EDA companies addressing 45nm (and 32nm) design challenges? If you look at the work being done in India, it is now pretty cutting edge, and very comparable to the rest of the world.
Arya added: "Our customers are looking for the 3Cs -- complexity, cost and convergence. The end users are asking for more features. For example, in their mobile or any other electronic device, which is driving our customers to pack in more functionality on the chips.
"Our customers have multiple challenges at 45nm and below, notably low power, analog-mixed signal and Design for Manufacturing (DFM)."
Challenges in 45nm and below
And what are those? As the industry pushes toward smaller process geometries, the existing design infrastructure must be upgraded holistically to automate power-lowering design techniques. Most power-control methods in use today are manual and implemented ad hoc, leading to an increased risk and cost.
Across the design and manufacturing chain, an urgent need has emerged for an automated, power-aware design infrastructure. To facilitate and support a new era of low-power design innovation, Cadence has formed the Power Forward Initiative (PFI).
Drawing from the collective expertise of leading technology companies, the Power Forward Initiative will create a more systematic, integrated approach to low-power design, providing a platform for higher-level exploration and IP re-use.
The PFI members are already at work on validating the Common Power Format (CPF), a new open specification language that captures all power-specific design, constraint, and functionality requirements, such as multi-supply voltage and power shutoff, in a single file.
Arya noted: "By linking design, verification, and implementation domains, the Common Power Format enables automation of power-reduction techniques and increases predictability. No longer constrained by the risk of low yield or costly re-spins, design teams can focus their time and resources on what matters most —- innovation. Achieving both functional and structural verification before incurring manufacturing costs, and with greater time-to-market opportunities, companies across the design and manufacturing chain can adopt new process geometries and start low-power design projects profitably.
On the subject of DFM, EDA companies are trying their utmost to improve yield. Cadence is trying to bring lot of analysis early in the cycle. The designer has more visibility on those effects, before they get manufactured. It has a host of technology offerings to enable the designers make early decisions.
For example, Cadence has recently worked with TSMC on 9.0 reference flow. It has also worked with ARM on a low-power methodology. The idea is that an industry-wide collaboration will ensure that EDA companies like Cadence are able to provide value to customers.
As customers grapple with technology and time-to-market challenges, the EDA industry will be the DNA of growth.
Sunday, June 1, 2008
Top semicon articles of 2008
A very kind reader left a comment yesterday that he (or she?) spent three hours on my blog! I am simply overwhelmed and humbled!!
It has really been a pleasure writing and maintaining a semicon blog! Plenty such are around carrying very valuable information, and I salute those bloggers.
It is really tough to contend with all the other technology-related information, but then, semicon has its own charm, and its own set of dedicated readers -- who DO go on to become extremely loyal.
I am even more touched by another request by a friend to list all the top articles I've written this year. Wow!!
It is very difficult for me to say, which ones are the best! However, I am listing the articles here. They all link back to CIOL. Of course, I've blogged here first, so, those who are familiar with my blog pieces, will identify them immediately.
Here goes then -- starting from the latest back down to very late last year -- in terms of relevance. Enjoy!
Semi trends 2008: Fab spend lower, ASPs stabilizing
The call on global fab spend was for a 10 percent reduction, and this is now getting to be closer to 20 percent.
UK, India aim for semicon collaboration
ISA-UKTI study examines collaboration scope between India and UK in design, applications and devices.
Dubai an emerging silicon frontier
The government of Dubai has set up the Dubai Silicon Oasis Authority (DSOA) as the engine for propelling Dubai into the knowledge economy.
Be parallel, or perish!
Parallelism offers new doors, and creativity is required to open these new doors, says Intel.
Altera first @ 40nm FPGAs
The company has announced two product lines -- the Stratix IV FPGAs and the HardCopy IV ASICs.
Semicon likely to grow 12pc in 2008
If there will be an economic recession, the chip industry (but not all firms) is in the best shape possible to weather the ensuing storm.
India's growing might in global semicon
India is fast becoming the world's destination, and increasingly the source too, for semiconductors.
Fascinating developments in 22nm!
These augur well for the global semiconductor industry, even though the field could get much narrower.
Indian design services to touch $10.96bn by 2010
Total design services market in India is said to have grown at 21 percent year on year.
NXP India achieves RF CMOS in single chip
The entire analog and RF work done has been in Bangalore by NXP's single-chip design team.
LabVIEW 8.5 delivers power of multicore processors
With LabVIEW, designers and engineers can assign different tasks on different cores -- which are independent.
Multi-nationalization of product development process
Indian designers lead in transaction level design, and can play big role in EDA.
Can we expect exciting times in 2008? Some trends
Blurring lines between PMPs and PNDs, semicon rush or hush; Netscape's end -- all are in store!
Semicon outlook 2008: Global market likely to grow 6-11 percent in 2008
Some predictions are for 2008 to be flat year or a year of negative growth; EDA to grow 7.8pc!
That's about it! If there's anything I've missed out, kindly let me know. Thanks for all your continuing support, dear readers. It is very humbling and touching.
It has really been a pleasure writing and maintaining a semicon blog! Plenty such are around carrying very valuable information, and I salute those bloggers.
It is really tough to contend with all the other technology-related information, but then, semicon has its own charm, and its own set of dedicated readers -- who DO go on to become extremely loyal.
I am even more touched by another request by a friend to list all the top articles I've written this year. Wow!!
It is very difficult for me to say, which ones are the best! However, I am listing the articles here. They all link back to CIOL. Of course, I've blogged here first, so, those who are familiar with my blog pieces, will identify them immediately.
Here goes then -- starting from the latest back down to very late last year -- in terms of relevance. Enjoy!
Semi trends 2008: Fab spend lower, ASPs stabilizing
The call on global fab spend was for a 10 percent reduction, and this is now getting to be closer to 20 percent.
UK, India aim for semicon collaboration
ISA-UKTI study examines collaboration scope between India and UK in design, applications and devices.
Dubai an emerging silicon frontier
The government of Dubai has set up the Dubai Silicon Oasis Authority (DSOA) as the engine for propelling Dubai into the knowledge economy.
Be parallel, or perish!
Parallelism offers new doors, and creativity is required to open these new doors, says Intel.
Altera first @ 40nm FPGAs
The company has announced two product lines -- the Stratix IV FPGAs and the HardCopy IV ASICs.
Semicon likely to grow 12pc in 2008
If there will be an economic recession, the chip industry (but not all firms) is in the best shape possible to weather the ensuing storm.
India's growing might in global semicon
India is fast becoming the world's destination, and increasingly the source too, for semiconductors.
Fascinating developments in 22nm!
These augur well for the global semiconductor industry, even though the field could get much narrower.
Indian design services to touch $10.96bn by 2010
Total design services market in India is said to have grown at 21 percent year on year.
NXP India achieves RF CMOS in single chip
The entire analog and RF work done has been in Bangalore by NXP's single-chip design team.
LabVIEW 8.5 delivers power of multicore processors
With LabVIEW, designers and engineers can assign different tasks on different cores -- which are independent.
Multi-nationalization of product development process
Indian designers lead in transaction level design, and can play big role in EDA.
Can we expect exciting times in 2008? Some trends
Blurring lines between PMPs and PNDs, semicon rush or hush; Netscape's end -- all are in store!
Semicon outlook 2008: Global market likely to grow 6-11 percent in 2008
Some predictions are for 2008 to be flat year or a year of negative growth; EDA to grow 7.8pc!
That's about it! If there's anything I've missed out, kindly let me know. Thanks for all your continuing support, dear readers. It is very humbling and touching.
Sunday, May 18, 2008
Top 10 global semicon predictions -- where are we today
It is always interesting to write semicon blogs! Lots of people come up to me with their own comments, insights, requests, etc. One such request came from a friend in Taiwan, who's involved with the semiconductor industry.I was asked forthrightly what I thought of the top 10 global predictions, which I had blogged/written about some time back late last year.
Top 10 semicon predictions
For those who came in late, here are the 10 global predictions on semiconductors made at that time (late December 2007.
1. Semiconductor firms may have to face a recession year in an election year.
2. DRAM market looks weak in 2008.
3. NAND market will remain hot.
4. Power will remain a major issue.
5. EDA has to catch up.
6. Need to solve embedded (software crisis?) dilemma.
7. Consolidation in the fab space.
8. Capital equipment guys will continue to move to other market.
9. Spend on capital equipment to drop.
10. Mini fabs in developing countries.
Well, lot of water has flowed since those predictions were made. Let's see how things stand, as of now. The updated predictions would look something like these:
1. There have been signs of recession, but the industry has faced it well, so far. In fact, Future Horizons feels that if there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm.
2. Memory market is changing slightly as well, though people are very cautious. According to Converge, memory market prices appear to be stabilizing. iSuppli has predicted a poor year for DRAM though!
3. NAND Flash could show some recovery later this year. Yes, Q1-08 QoQ sales seems to have slipped, but the market remains hopeful of a recovery. Even iSuppli warned of NAND Flash slowdown in 2008, while Apple slashed its NAND order forecast significantly for 2008! Keep those fingers crossed!!
4. Power remains a big issue, and will continue to be so. This will remain as we move up newer technology process nodes.
5. EDA is seemingly catching up with 45nm designs. Magma, Synopsys, and the other leading EDA vendors are said to be playing big roles in 45nm designs.
6. Fabless companies are gaining in strength. No doubt about it! The 2007 semicon rankings show that. Also, Qualcomm is now the leader in the top wireless semicon suppliers, displacing Texas Instruments.
7. There have been consilidations (or long term alliances) in: a) fab space b) DRAM space. In the fab space, Intel, Samsung and TSMC have combined to go with 450mm wafer fab line by 2012. And in the DRAM space, there have been new camps, such as Elpida-Qimonda, and Nanya-Micron partnering to take on Samsung. With the global semiconductor market seeing steady decline in growth rate, which would continue, look forward to more consolidations.
8. Investments in photovoltaics (PV) have eased the pressure on capital equipment makers and spend somewhat. In fact, 2007 will be remembered as the year when the PV industry emerged as a key opportunity for subsystems suppliers and provided a timely boost in sales for those companies actively addressing this market. Perhaps, here lies an opportunity for India.
9. Mini fabs -- these are yet to happen; so far talks only. In India, a single silicon wafer fab has yet to start functioning, even though it has been quite a while since the semicon policy was announced. Conversely, some feel that India should focus on design, rather than go after something as mature as having wafer fabs. However, several solar fabs -- from Moser Baer, Videocon, Reliance, etc., are quite likely.
10. Moving to 45nm from 32nm is posing more design challenges than thought. This is largely due to the use of new materials. Well, 45nm will herald a totally different structure -- metal gate/high-k/thin FET/deep trench design, etc. It will herald a new way of system design as well.
Now, I am not a semicon expert by any long distance, and welcome comments, suggestions, improvements from you all.
Thursday, April 24, 2008
Apple shocks industry with PA Semi buy!
According to The Unofficial Apple Web Blog (TUAW), Apple has stunned the industry by acquiring P.A. Semi, a Santa Clara based chip company founded by Dan Dobberpuhl, the former lead designer of the DEC Alpha and StrongARM processors, for US $278 million.
The Computerworld Blog reported that Apple had 'shocked' everyone with this move. P.A. Semi is a fabless chip designer that specializes in super low power PowerPC processors.
This move surely raises questions about Apple's future association with Intel, which has been courting Apple since long to adopt its Atom low-power processor family. It also remains to be seen whether Apple will use these super low power PowerPC processors in embedded devices, such as high end iPhones, iPods, etc.
Interestingly, the PA Semi Web site is displaying a message: This account has surpassed its bandwidth allocation at the present time. You may reach the account administrator. Maybe, too many folks are trying to access the site to find out more about this company.
The Apple buyout of PA Semi was possibly first reported by Forbes. Since then a whole lot of articles have appeared on the Web.
According to the site, Apple spokesman Steve Dowling reportedly said, "Apple buys smaller technology companies from time to time, and we generally do not comment on our purposes and plans." He is also said to have declined to comment on the value of the deal, which a person familiar with the deal suggested was done for $278 million in cash.
Apple later announced its quarterly earnings Wednesday. As per Apple's financial results for fiscal 2008 second quarter ended March 29, 2008, the company posted $7.51 billion revenue and net quarterly profit of $1.05 billion, or $1.16 per diluted share.
These results compare to revenue of $5.26 billion and net quarterly profit of $770 million, or $.87 per diluted share, in the year-ago quarter. Gross margin was 32.9 percent, down from 35.1 percent in the year-ago quarter. International sales accounted for 44 percent of the quarter's revenue.
Apple shipped 2,289,000 Macintosh computers during the quarter, representing 51 percent unit growth and 54 percent revenue growth over the year-ago quarter. It sold 10,644,000 iPods during the quarter, representing 1 percent unit growth and 8 percent revenue growth over the year-ago quarter. Quarterly iPhone sales were 1,703,000.
As per another Forbes reports, Apple has promised to sell 10 million iPhones in 2008 on a call with analysts Wednesday. Watch this space, as Apple is surely going to be in news for most of this year.
The Computerworld Blog reported that Apple had 'shocked' everyone with this move. P.A. Semi is a fabless chip designer that specializes in super low power PowerPC processors.
This move surely raises questions about Apple's future association with Intel, which has been courting Apple since long to adopt its Atom low-power processor family. It also remains to be seen whether Apple will use these super low power PowerPC processors in embedded devices, such as high end iPhones, iPods, etc.
Interestingly, the PA Semi Web site is displaying a message: This account has surpassed its bandwidth allocation at the present time. You may reach the account administrator. Maybe, too many folks are trying to access the site to find out more about this company.
The Apple buyout of PA Semi was possibly first reported by Forbes. Since then a whole lot of articles have appeared on the Web.
According to the site, Apple spokesman Steve Dowling reportedly said, "Apple buys smaller technology companies from time to time, and we generally do not comment on our purposes and plans." He is also said to have declined to comment on the value of the deal, which a person familiar with the deal suggested was done for $278 million in cash.
Apple later announced its quarterly earnings Wednesday. As per Apple's financial results for fiscal 2008 second quarter ended March 29, 2008, the company posted $7.51 billion revenue and net quarterly profit of $1.05 billion, or $1.16 per diluted share.
These results compare to revenue of $5.26 billion and net quarterly profit of $770 million, or $.87 per diluted share, in the year-ago quarter. Gross margin was 32.9 percent, down from 35.1 percent in the year-ago quarter. International sales accounted for 44 percent of the quarter's revenue.
Apple shipped 2,289,000 Macintosh computers during the quarter, representing 51 percent unit growth and 54 percent revenue growth over the year-ago quarter. It sold 10,644,000 iPods during the quarter, representing 1 percent unit growth and 8 percent revenue growth over the year-ago quarter. Quarterly iPhone sales were 1,703,000.
As per another Forbes reports, Apple has promised to sell 10 million iPhones in 2008 on a call with analysts Wednesday. Watch this space, as Apple is surely going to be in news for most of this year.
Wednesday, April 2, 2008
Staying ahead of clock a habit at Magma!
EDA is a complex industry to be in, what with process geometries changing all the time and EDA firms compelled to keep up with those changes. Magma Design Automation Inc. has been one of those, which has kept ahead of the changes and also managed good growth. In other words, Magma has managed to beat the clock consistently and stayed ahead, and continues to do so.
According to Rajeev Madhavan, chairman and CEO, Magma Design Automation Inc.. Magma has been outperforming the EDA industry by 2x globally. He touched upon the drive toward consumerization. Whle it was driven by PCs during the 1980s, mobile phones and PDAs are now the growth drivers for the common man. The consumer space is driving semiconductor applications as well. These are in form of devices with smaller form factors, where power is an important issue.
As an example, Madhavan highlighted the fact that 75 percent of the chips in the iPhone type of complex cell phone has been done using Magma. "We enable such points to happen. Consumer applications are driving EDA, and we are providing that change."
According to him, India is a major center for Magma. An entire business line of products are now being driven out of India. The physical verification units – DRC, etc., -- are all done here. Magma is consistently developing new products and product lines. Any MNC in India has an opportunity to build relationships with the EDA powerhouse.
EDA is all about integration. With operating margins getting slimmer, most companies have been moving to Fab-Lite. India has great expertise in design knowledge. India should shift its focus on developing the intellectual knowledge side, contended Madhavan. As for fabs, as and when those happen in India, they will definitely create jobs. "Fab-lite is actually good for EDA. It means more design productivity. Leading firms such as TI, NVIDIA, Broadcom, etc., are our customers," he said.
Magma is now looking at more value addition and faster development. It has covered the entire EDA domain. Magma has a culture of rewriting its software a lot more and also covers all new process geometries. According to Madhavan, Magma is constantly in touch with leading foundries such as TSMC.
It is said that right now, around 75 percent of the chips in 45nm currently use Magma. Magma is also working with a customer in 32nm. Madhavan said: "You have to develop the tools as the processes change. At Magma, we need smart people who can understand electrical engineering and computer science. Growth comes in identifying and building the talent pools.”
As for product lines developed in India, Magma's Quartz Formal has been developed largely in India. Most of the development work is happening in NOIDA, near Delhi. Work on DRC is being done out of Bangalore. “Every single product from Magma has some footprint in India,” he said. The complexities of chips have been growing and those require more automation.
Magma intends to grow from $178 million to $211 million during 2008. Madhavan felt that as the eco-system units come up in India, the company can move forward. Magma is hopeful that more design companies will be getting into India.
90nm designs major in India
Ricky Bedi, Senior Director, Application Engineering, Magma Design Automation India Pvt Ltd, added that the EDA industry had moved on from being optimizers. India too has to now move forward from being outsourcers to enablers.
He said, "When that happens, India will play a bigger role and offer more services. For example, Wipro, etc., are now doing full turnkey solutions." Magma India is now working with over 32 universities, regional engineering colleges (RECs), IITs, etc. The intent is to facilitate VLSI programs in all of those places.
However, he agreed that the innovation has not really kicked off in the country. As of now, 90nm designs are in the majority in India, and in comparison, 65nm designs are lesser. Magma has already gone into 45nm, and even into 32nm. Bedi said: "Right now, yield is imperative in 45nm. Innovation will continue in the smaller geometries. Innovation has to focus more on predictability, etc."
There is another trend worth mentioning -- about re-usable IPs. According to Magma, there will be even more of re-usable IPs. As the designs themselves get complex, designers need to achieve those in shorter timeframes as the time-to-market (TTM) is crucial. Replication of blocks is also happening. Implementation of re-usable IPs will go up a notch, added Bedi.
While the EDA tools are now catching up with the advances in semiconductors, it has not been smooth sailing for language. Bedi added: "As far as language is concerned, language itself does not blend so easily. It takes great effort to move from Verilog to VHDL."
Yatin Trivedi, director, Industry Partnership Program, Design Implementation Business Unit, Magma Design Automation Inc., touched upon the aspect of power. He said: "In the EDA format, it is important that the power format is accepted by as many vendors. The difference should be in the usage, not the format. In any design flow -- from RTL to GDS -- any design that is implemented must be simulated. Power information is now an integral part of the design. Leakage can destroy a die."
According to Rajeev Madhavan, chairman and CEO, Magma Design Automation Inc.. Magma has been outperforming the EDA industry by 2x globally. He touched upon the drive toward consumerization. Whle it was driven by PCs during the 1980s, mobile phones and PDAs are now the growth drivers for the common man. The consumer space is driving semiconductor applications as well. These are in form of devices with smaller form factors, where power is an important issue.
As an example, Madhavan highlighted the fact that 75 percent of the chips in the iPhone type of complex cell phone has been done using Magma. "We enable such points to happen. Consumer applications are driving EDA, and we are providing that change."
According to him, India is a major center for Magma. An entire business line of products are now being driven out of India. The physical verification units – DRC, etc., -- are all done here. Magma is consistently developing new products and product lines. Any MNC in India has an opportunity to build relationships with the EDA powerhouse.
EDA is all about integration. With operating margins getting slimmer, most companies have been moving to Fab-Lite. India has great expertise in design knowledge. India should shift its focus on developing the intellectual knowledge side, contended Madhavan. As for fabs, as and when those happen in India, they will definitely create jobs. "Fab-lite is actually good for EDA. It means more design productivity. Leading firms such as TI, NVIDIA, Broadcom, etc., are our customers," he said.
Magma is now looking at more value addition and faster development. It has covered the entire EDA domain. Magma has a culture of rewriting its software a lot more and also covers all new process geometries. According to Madhavan, Magma is constantly in touch with leading foundries such as TSMC.
It is said that right now, around 75 percent of the chips in 45nm currently use Magma. Magma is also working with a customer in 32nm. Madhavan said: "You have to develop the tools as the processes change. At Magma, we need smart people who can understand electrical engineering and computer science. Growth comes in identifying and building the talent pools.”
As for product lines developed in India, Magma's Quartz Formal has been developed largely in India. Most of the development work is happening in NOIDA, near Delhi. Work on DRC is being done out of Bangalore. “Every single product from Magma has some footprint in India,” he said. The complexities of chips have been growing and those require more automation.
Magma intends to grow from $178 million to $211 million during 2008. Madhavan felt that as the eco-system units come up in India, the company can move forward. Magma is hopeful that more design companies will be getting into India.
90nm designs major in India
Ricky Bedi, Senior Director, Application Engineering, Magma Design Automation India Pvt Ltd, added that the EDA industry had moved on from being optimizers. India too has to now move forward from being outsourcers to enablers.
He said, "When that happens, India will play a bigger role and offer more services. For example, Wipro, etc., are now doing full turnkey solutions." Magma India is now working with over 32 universities, regional engineering colleges (RECs), IITs, etc. The intent is to facilitate VLSI programs in all of those places.
However, he agreed that the innovation has not really kicked off in the country. As of now, 90nm designs are in the majority in India, and in comparison, 65nm designs are lesser. Magma has already gone into 45nm, and even into 32nm. Bedi said: "Right now, yield is imperative in 45nm. Innovation will continue in the smaller geometries. Innovation has to focus more on predictability, etc."
There is another trend worth mentioning -- about re-usable IPs. According to Magma, there will be even more of re-usable IPs. As the designs themselves get complex, designers need to achieve those in shorter timeframes as the time-to-market (TTM) is crucial. Replication of blocks is also happening. Implementation of re-usable IPs will go up a notch, added Bedi.
While the EDA tools are now catching up with the advances in semiconductors, it has not been smooth sailing for language. Bedi added: "As far as language is concerned, language itself does not blend so easily. It takes great effort to move from Verilog to VHDL."
Yatin Trivedi, director, Industry Partnership Program, Design Implementation Business Unit, Magma Design Automation Inc., touched upon the aspect of power. He said: "In the EDA format, it is important that the power format is accepted by as many vendors. The difference should be in the usage, not the format. In any design flow -- from RTL to GDS -- any design that is implemented must be simulated. Power information is now an integral part of the design. Leakage can destroy a die."
Monday, January 14, 2008
Power awareness critical for chip designers
The holy grail of electronics -- low-power design, or having the requisite power awareness is extremely critical for chip designers working on both high-performance applications and portable applications. For one, it determines the battery lifetime of a device, besides determining the cooling and energy costs. It is said that several of today's chip designs are limited in terms of power and still require maximum performance.
Touching on the global factors, S.N. Padmanabhan, Senior Vice President, Mindtree Consulting, said the Kyoto Protocol mandates energy conservation efforts.
Low-power design challenges
Asia, as we all know, has been emerging as a major energy consuming society. Shortage of electricity is becoming a major concern. There is a huge strain on nations to meet the rising needs/halt rise. There is also a rapid increase in all types of electronic goods in growing economies. As a result, increased efficiencies and reduced consumption should be beneficial as a whole!
In the Indian context, the country has around 125 million televisions sets, 5 million automatic washing machines, 10 million white goods, 200+ million other electronics, over 90 million cell phones and 50 million land lines, etc. A 1W reduction in white goods and TVs would lead to a saving of 140 Mi Watts of power! And, a 10 mW reduction in phones will save 1.4 Mi Watts!! Therefore, it makes even more sense to go low power!
Mindtree's Padmanabhan said IC power budgets have come down drastically. It is <2W for four out of five chips designed. There has also been a simultaneous manipulation of multiple parameters (P=CV2f). Next, there are several leakage issues in 65nm and smaller geometries, which can no longer be ignored.
Add to all of these are factors that there is a lack of availability of comprehensive tools and techniques, as well as analog designs. In such a scenario, designers need to be very clear about their objectives -- is it achieving lowering average power, lowering the maximum peak power or lowering energy.
Jayanta Kumar Lahiri, Director, ARM, pointed out challenges associated with batteries. Battery storage has been a limiting factor. Battery energy doubles in a decade and surely, does not follow the Moore’s law. Next, there have hardly been major changes in the basic battery technology. The energy density/size safe handling are limiting factors as well for batteries.
He added that the low-power challenge is four-fold in the VLSI domain. These are -- leakiness; more integration means more W/cm^2; EDA tools not that good in low power domain and does not co-relate sometimes with the silicon, and variability of device parameters make things worse.
Toshiyuki Saito, Senior Manager, Design Engineering Division NEC Electronics Japan, said low power is necessary for customer's success -- in form of heat suppress for wired systems and improved battery life time for mobile systems. It also brings cost competitiveness for SoC suppliers in terms of packaging cost, and development cost and turnaround time. Finally, it would contribute to preserving the global environment.
Addressing low power challenges
What are semiconductor and EDA companies doing to address the low-power design challenges? Padmanabhan said several techniques were being employed at the circuit level. However, each one of those had limitations.
These include AVS -- which provides maximum savings, reduces speed, but may need compensation; clock gating -- which does not help to reduce leakage and needs additional gates; and adaptive clock scaling -- which needs sophistication and is not very simple; and finally, the use of multi threshold cells for selective trade-off.
Emerging techniques include efficient RTL synthesis techniques, which is fast, but leaky, vs. slow and low power; power aware resource sharing, which is planning to be done at the architectural level and synthesis, but is not as widely used as other techniques; and power gating methodology -- which makes use of sleep transistors, has coarse and fine grained methods, reduces dynamic and leakage power, and also exploits idle times of the circuit.
He added that power optimization should start at the architecture and design stages. Maximum optimization can be achieved at the system level. Also, the evolving power optimization tools and methodologies required collaborative approaches.
Power Forward Initiative
Pankaj Mayor, Group Director, Industry Alliances, Cadence Design Systems, said low power imperative is driving the semiconductor and EDA industries. He said, "design-based low power solution is the only answer!" Traditional design-based solutions are fragmented. Basic low power design techniques, such as area optimization, multi-Vt optimization and clock gating were automated in the 1990s.
There has since been an impact of advanced low-power techniques. These advanced techniques include multi-supply voltage (MSV), power shut-off (PSO), dynamic and adaptive voltage frequency scaling (DVFS and AVS), and substrate biasing. Cadence's low-power solution uses advanced techniques.
According to Mayor, the Power Forward Initiative (PFI) has created an ecosystem as well. The Power Forward Initiative includes Cadence and 23 other companies across the design chain, as of the end of December 2007.
The year 2007 also saw a continued Power Forward industry momentum. In Q1-07, Common Power Format or CPF became the Si2 [Silicon Integration Initiative] standard. The Cadence Low Power Solution production released V 1.0 in this quarter as well. In H2-07, the industry has seen over 100 customers adopting CPF-based advanced low power solution as well as ~50 tapeouts.
CPF allows holistic automation and validation at every design step. Arijit Dutta, Manager, Design Methodology, Freescale Semiconductor exhibited the advantages of using the CPF in wireless, networking and automotive verticals at Freescale.
Touching on the global factors, S.N. Padmanabhan, Senior Vice President, Mindtree Consulting, said the Kyoto Protocol mandates energy conservation efforts.
Low-power design challenges
Asia, as we all know, has been emerging as a major energy consuming society. Shortage of electricity is becoming a major concern. There is a huge strain on nations to meet the rising needs/halt rise. There is also a rapid increase in all types of electronic goods in growing economies. As a result, increased efficiencies and reduced consumption should be beneficial as a whole!
In the Indian context, the country has around 125 million televisions sets, 5 million automatic washing machines, 10 million white goods, 200+ million other electronics, over 90 million cell phones and 50 million land lines, etc. A 1W reduction in white goods and TVs would lead to a saving of 140 Mi Watts of power! And, a 10 mW reduction in phones will save 1.4 Mi Watts!! Therefore, it makes even more sense to go low power!
Mindtree's Padmanabhan said IC power budgets have come down drastically. It is <2W for four out of five chips designed. There has also been a simultaneous manipulation of multiple parameters (P=CV2f). Next, there are several leakage issues in 65nm and smaller geometries, which can no longer be ignored.
Add to all of these are factors that there is a lack of availability of comprehensive tools and techniques, as well as analog designs. In such a scenario, designers need to be very clear about their objectives -- is it achieving lowering average power, lowering the maximum peak power or lowering energy.
Jayanta Kumar Lahiri, Director, ARM, pointed out challenges associated with batteries. Battery storage has been a limiting factor. Battery energy doubles in a decade and surely, does not follow the Moore’s law. Next, there have hardly been major changes in the basic battery technology. The energy density/size safe handling are limiting factors as well for batteries.
He added that the low-power challenge is four-fold in the VLSI domain. These are -- leakiness; more integration means more W/cm^2; EDA tools not that good in low power domain and does not co-relate sometimes with the silicon, and variability of device parameters make things worse.
Toshiyuki Saito, Senior Manager, Design Engineering Division NEC Electronics Japan, said low power is necessary for customer's success -- in form of heat suppress for wired systems and improved battery life time for mobile systems. It also brings cost competitiveness for SoC suppliers in terms of packaging cost, and development cost and turnaround time. Finally, it would contribute to preserving the global environment.
Addressing low power challenges
What are semiconductor and EDA companies doing to address the low-power design challenges? Padmanabhan said several techniques were being employed at the circuit level. However, each one of those had limitations.
These include AVS -- which provides maximum savings, reduces speed, but may need compensation; clock gating -- which does not help to reduce leakage and needs additional gates; and adaptive clock scaling -- which needs sophistication and is not very simple; and finally, the use of multi threshold cells for selective trade-off.
Emerging techniques include efficient RTL synthesis techniques, which is fast, but leaky, vs. slow and low power; power aware resource sharing, which is planning to be done at the architectural level and synthesis, but is not as widely used as other techniques; and power gating methodology -- which makes use of sleep transistors, has coarse and fine grained methods, reduces dynamic and leakage power, and also exploits idle times of the circuit.
He added that power optimization should start at the architecture and design stages. Maximum optimization can be achieved at the system level. Also, the evolving power optimization tools and methodologies required collaborative approaches.
Power Forward Initiative
Pankaj Mayor, Group Director, Industry Alliances, Cadence Design Systems, said low power imperative is driving the semiconductor and EDA industries. He said, "design-based low power solution is the only answer!" Traditional design-based solutions are fragmented. Basic low power design techniques, such as area optimization, multi-Vt optimization and clock gating were automated in the 1990s.
There has since been an impact of advanced low-power techniques. These advanced techniques include multi-supply voltage (MSV), power shut-off (PSO), dynamic and adaptive voltage frequency scaling (DVFS and AVS), and substrate biasing. Cadence's low-power solution uses advanced techniques.
According to Mayor, the Power Forward Initiative (PFI) has created an ecosystem as well. The Power Forward Initiative includes Cadence and 23 other companies across the design chain, as of the end of December 2007.
The year 2007 also saw a continued Power Forward industry momentum. In Q1-07, Common Power Format or CPF became the Si2 [Silicon Integration Initiative] standard. The Cadence Low Power Solution production released V 1.0 in this quarter as well. In H2-07, the industry has seen over 100 customers adopting CPF-based advanced low power solution as well as ~50 tapeouts.
CPF allows holistic automation and validation at every design step. Arijit Dutta, Manager, Design Methodology, Freescale Semiconductor exhibited the advantages of using the CPF in wireless, networking and automotive verticals at Freescale.
Friday, December 21, 2007
Top 10 global semiconductor trends for 2008
It is really difficult to stick your neck out and predict. That's what makes the analyst's jobs so difficult. Things happen and pass you by so quickly. For instance, as an example, who would have thought that Samsung would face a substantial blackout that would halt six chip production lines in a complex operated by the world's largest flash memory producer?
Plans for the fab in India are now well under way. There have been questions like, do we need fabs? The year 2008 is the year of presidential elections and the Summer Olympics. Will we really see a recession in 2008? Here are some of the trends that are visible for 2008. Would love to hear from you.
1. Semiconductor firms may have to face a recession year in an election year
Yes, strange as it may sound, this just might happen! Concerns about consumer spending, caused by higher oil prices, mortgage crisis in the US and fears of a possible recession have made analysts more cautious, albeit optimistic. Analysts are wary of an impending recession in semiconductors during 2008. That, it should fall in the year of the US presidential elections makes it all the more intriguing. The nervousness is already showing in the slowing down of some markets.
2. DRAM market looks weak in 2008
Will DRAM prices rebound? Remains to be seen, although DRAMeXchange says that Taiwanese suppliers are likely to have their output to trim by 10-25 percent during February (Chinese New Year) as they usually plan for an average of 3-7 days of annual facility maintenance during this period. DRAMeXchange regards this as a possible catalyst for a price rebound in near term. Analysts haven't helped either, with some saying DRAM will be on the slow side or even negative in H1-08.
3. NAND market will remain hot
You can bet, it will! Analysts remain upbeat for a positive NAND market in 2008. The reason being – new applications such as wireless USB, increase in cell phones memory capacities, higher content in portable media players, etc. We hope it is not a flash in the pan. There are rumors of another iPhone along the way!
4. Power will remain major issue
This isn't going to change anytime soon! Power awareness is crucial for portable applications. It determines battery lifetime, and there's an increased amount of computation involved as well. Power awareness is extremely crucial for high-performance applications. It determines cooling and energy costs. Many chip designs today are power limited and still require maximum performance.
5. EDA has to catch up
And fast! Analysts at a recent webcast hosted by Semiconductor International elaborated how the EDA industry was in a position of lag in the market. The DFM issue is increasingly becoming more complex. There is said to be a move to restrict the design rules that is in place now for 45nm. We are likely to see major changes in 32nm. That will have an impact on the EDA tools.
6. Need to solve the embedded dilemma
It is said that in 2007, the cost of designing or developing the embedded software for an SoC actually passed the cost of designing the SoC itself! We seem to be in the middle of a software crisis that is going to hit the entire electronics industry in the next five to six years.
7. Consolidation in the fab space
Some of the other older IDMs and fabs are said to be actually shutting down and going over to the foundries and process wafers for less than what they can do on their own. In this respect, we are seeing a lot of consolidation within the fab space. The mid-level players are consolidating. The customer base is clearly narrowing. The field is narrowing in 65nm and 45nm, and as we get to below 45nm, the field is going to get much, much narrower.
8. Capital equipment guys will continue to move to other markets
The best example, you can think of, is Applied Materials, which is into innovative equipment, service and software products for fabrication of chips, flat panel displays, solar photovoltaic cells, flexible electronics and energy efficient glass. Even the smaller guys are moving into LEDs or MEMS markets. That tells us what these companies are thinking about the semiconductors market.
9. Spend on capital equipment to drop
Gartner is expecting the long overdue capital spending correction in DRAM market to push the capital equipment market into contraction. Another slow year from foundry, along with concerns of US economic recession, adding to the downside. However, NAND spend should ramp up.
10. Mini fabs in developing countries
India has announced fab plans. There have also been talks of mega fabs and mini fabs elsewhere. There are going to be different types of fabs! With globalization, lot of countries may decide they want to have a fab. The market's going to change.
However, bear in mind that the outlook on new fab starts appears weaker, as many companies have cut back on spending to wait for the market to improve. After a forecasted 8 percent YoY increase in fab construction spending in 2007, levels are likely to be flat in 2008.
Plans for the fab in India are now well under way. There have been questions like, do we need fabs? The year 2008 is the year of presidential elections and the Summer Olympics. Will we really see a recession in 2008? Here are some of the trends that are visible for 2008. Would love to hear from you.
1. Semiconductor firms may have to face a recession year in an election year
Yes, strange as it may sound, this just might happen! Concerns about consumer spending, caused by higher oil prices, mortgage crisis in the US and fears of a possible recession have made analysts more cautious, albeit optimistic. Analysts are wary of an impending recession in semiconductors during 2008. That, it should fall in the year of the US presidential elections makes it all the more intriguing. The nervousness is already showing in the slowing down of some markets.
2. DRAM market looks weak in 2008
Will DRAM prices rebound? Remains to be seen, although DRAMeXchange says that Taiwanese suppliers are likely to have their output to trim by 10-25 percent during February (Chinese New Year) as they usually plan for an average of 3-7 days of annual facility maintenance during this period. DRAMeXchange regards this as a possible catalyst for a price rebound in near term. Analysts haven't helped either, with some saying DRAM will be on the slow side or even negative in H1-08.
3. NAND market will remain hot
You can bet, it will! Analysts remain upbeat for a positive NAND market in 2008. The reason being – new applications such as wireless USB, increase in cell phones memory capacities, higher content in portable media players, etc. We hope it is not a flash in the pan. There are rumors of another iPhone along the way!
4. Power will remain major issue
This isn't going to change anytime soon! Power awareness is crucial for portable applications. It determines battery lifetime, and there's an increased amount of computation involved as well. Power awareness is extremely crucial for high-performance applications. It determines cooling and energy costs. Many chip designs today are power limited and still require maximum performance.
5. EDA has to catch up
And fast! Analysts at a recent webcast hosted by Semiconductor International elaborated how the EDA industry was in a position of lag in the market. The DFM issue is increasingly becoming more complex. There is said to be a move to restrict the design rules that is in place now for 45nm. We are likely to see major changes in 32nm. That will have an impact on the EDA tools.
6. Need to solve the embedded dilemma
It is said that in 2007, the cost of designing or developing the embedded software for an SoC actually passed the cost of designing the SoC itself! We seem to be in the middle of a software crisis that is going to hit the entire electronics industry in the next five to six years.
Analysts are wary of an impending recession in semiconductors during 2008
7. Consolidation in the fab space
Some of the other older IDMs and fabs are said to be actually shutting down and going over to the foundries and process wafers for less than what they can do on their own. In this respect, we are seeing a lot of consolidation within the fab space. The mid-level players are consolidating. The customer base is clearly narrowing. The field is narrowing in 65nm and 45nm, and as we get to below 45nm, the field is going to get much, much narrower.
8. Capital equipment guys will continue to move to other markets
The best example, you can think of, is Applied Materials, which is into innovative equipment, service and software products for fabrication of chips, flat panel displays, solar photovoltaic cells, flexible electronics and energy efficient glass. Even the smaller guys are moving into LEDs or MEMS markets. That tells us what these companies are thinking about the semiconductors market.
9. Spend on capital equipment to drop
Gartner is expecting the long overdue capital spending correction in DRAM market to push the capital equipment market into contraction. Another slow year from foundry, along with concerns of US economic recession, adding to the downside. However, NAND spend should ramp up.
10. Mini fabs in developing countries
India has announced fab plans. There have also been talks of mega fabs and mini fabs elsewhere. There are going to be different types of fabs! With globalization, lot of countries may decide they want to have a fab. The market's going to change.
However, bear in mind that the outlook on new fab starts appears weaker, as many companies have cut back on spending to wait for the market to improve. After a forecasted 8 percent YoY increase in fab construction spending in 2007, levels are likely to be flat in 2008.
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