MOUNTAIN VIEW, USA: Synopsys Inc. today announced that the Common Platform technology alliance, a unique technology collaboration between IBM, Chartered Semiconductor Manufacturing and Samsung Electronics, has qualified IC Validator for 32-nanometer (nm) process design rule checking on Common Platform technology.
Synopsys and the Common Platform companies are continuing with the collaboration to complete the qualification of IC Validator at 28nm on Common Platform technology. IC Validator, the newest addition to the Galaxy Implementation Platform, is a full signoff DRC/LVS solution.
In addition, the IC Validator has been uniquely architected as an ideal add-on to IC Compiler for in-design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow.
This qualification enables Common Platform customers to deploy IC Validator into production use at 32nm and see benefits from the productivity advantages of in-design physical verification in conjunction with the IC Compiler place and route solution.
"We believe that in-design physical verification is essential to significantly reduce physical verification turnaround time given the complexities at emerging nodes," said Henry Law, vice president, design services division for Chartered, on behalf of the Common Platform alliance companies.
"Architected for 45nm and below process nodes, IC Validator offers a highly flexible programming language that makes runset creation at these complex nodes easy and concise. Our qualification of IC Validator confirmed its signoff accuracy and productivity benefits of in-design physical verification. Given the observed benefits, we are committed to qualifying IC Validator for the Common Platform 28nm process node."
Prevalent approaches to physical design and verification can be described as "implement-then-verify" and result in multiple iterations between design and signoff. In-design physical verification accelerates design closure by enabling sign-off quality rule checking and fixing during the design process, avoiding late stage surprises that can jeopardize project schedules.
Other benefits include incremental processing, automatic error detection and fixing, near-linear scalability across multiple CPU cores and the elimination of expensive stream-outs and stream-ins. IC Validator also offers significant automation and innovative features such as DRC error classification or DRC waiver, multi-user collaboration, customized reporting and on-the-fly error reporting that can further improve physical verification turnaround time.
While in-design physical verification is facilitated by seamless integration with IC Compiler, IC Validator's foundry-endorsed, signoff-accurate engine is its core strength. Powered by its hybrid data and command-processing engine, IC Validator is a full signoff DRC/LVS tool offering the high accuracy necessary for leading-edge process nodes, excellent scalability for efficient utilization of available hardware and high programmability for easier runset development.
For runset writers and CAD managers, IC Validator offers a flexible programming language that can cut runset size from 2 to 10x, lowering the cost of setting up, maintaining and modifying the physical verification environment.
"Common Platform technology companies have always been at the forefront in defining high-productivity flows for advanced processes," said Bijan Kiani, vice president of product marketing, design and manufacturing products at Synopsys.
"This qualification marks an important milestone in supporting leading-edge technology from the Common Platform alliance and will bring IC Validator's unique value proposition to our mutual customers and partners. We look forward to our continued collaboration towards the 28-nm qualification."
Showing posts with label Synopsys. Show all posts
Showing posts with label Synopsys. Show all posts
Wednesday, September 30, 2009
Wednesday, September 23, 2009
Synopsys unveils StarRC custom parasitic extraction solution
MOUNTAIN VIEW, USA: Synopsys Inc. has announced its StarRC Custom parasitic extraction solution for analog mixed-signal (AMS) and custom digital IC design.
By combining the gold standard Star-RCXT extraction technologies and the Raphael NXT 3D fast field solver into a single, unified extraction solution, the StarRC Custom solution offers high performance runtime with tuned accuracy to meet the analysis demands of high-sensitivity custom circuits.
This comprehensive offering includes optimized links with Synopsys' technology-leading CustomSim circuit simulator which can boost simulation runtime by up to 10X while preserving signoff accuracy. Additionally, StarRC Custom provides seamless integration with Synopsys' Galaxy Custom Designer implementation solution to improve designer productivity.
"The widespread use of custom circuits in today's complex system-on-chip (SoC) designs is creating a severe simulation and signoff bottleneck," said Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys.
"Increasing transistor count combined with the modeling of more complex parasitic effects is resulting in transistor-level simulation runtimes doubling and quadrupling. To address this challenge, Synopsys took a unique approach with StarRC Custom by focusing not only on extraction runtime and accuracy, but also on optimizing the extraction data to improve overall transistor-level simulation throughput."
StarRC Custom solution is built on the Star-RCXT gold standard technology and environment, enabling custom IC designers to get the instant benefit of Star-RCXT's broadest qualification in the industry for 65-nm and 45-nm process nodes. Star-RCXT is already in use by more than 40 leading semiconductor companies at 45-nm and trusted on more than 140 tapeouts at 16 foundries.
StarRC Custom provides the foundation of an expanded Synopsys extraction tools suite, which includes StarRC and StarRC Ultra. The next-generation StarRC and StarRC Ultra solutions offer versatile solutions for full-chip, gate-level and transistor-level designs as well as technologies to support advanced analysis capabilities.
The tools incorporate technologies such as hierarchical extraction, feature-scale chemical-mechanical polishing (CMP) effects modeling and variation-aware extraction to enable designers to achieve signoff accuracy while meeting their stringent tapeout schedules.
StarRC Custom is in limited customer availability now, with general customer availability planned in December 2009.
By combining the gold standard Star-RCXT extraction technologies and the Raphael NXT 3D fast field solver into a single, unified extraction solution, the StarRC Custom solution offers high performance runtime with tuned accuracy to meet the analysis demands of high-sensitivity custom circuits.
This comprehensive offering includes optimized links with Synopsys' technology-leading CustomSim circuit simulator which can boost simulation runtime by up to 10X while preserving signoff accuracy. Additionally, StarRC Custom provides seamless integration with Synopsys' Galaxy Custom Designer implementation solution to improve designer productivity.
"The widespread use of custom circuits in today's complex system-on-chip (SoC) designs is creating a severe simulation and signoff bottleneck," said Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys.
"Increasing transistor count combined with the modeling of more complex parasitic effects is resulting in transistor-level simulation runtimes doubling and quadrupling. To address this challenge, Synopsys took a unique approach with StarRC Custom by focusing not only on extraction runtime and accuracy, but also on optimizing the extraction data to improve overall transistor-level simulation throughput."
StarRC Custom solution is built on the Star-RCXT gold standard technology and environment, enabling custom IC designers to get the instant benefit of Star-RCXT's broadest qualification in the industry for 65-nm and 45-nm process nodes. Star-RCXT is already in use by more than 40 leading semiconductor companies at 45-nm and trusted on more than 140 tapeouts at 16 foundries.
StarRC Custom provides the foundation of an expanded Synopsys extraction tools suite, which includes StarRC and StarRC Ultra. The next-generation StarRC and StarRC Ultra solutions offer versatile solutions for full-chip, gate-level and transistor-level designs as well as technologies to support advanced analysis capabilities.
The tools incorporate technologies such as hierarchical extraction, feature-scale chemical-mechanical polishing (CMP) effects modeling and variation-aware extraction to enable designers to achieve signoff accuracy while meeting their stringent tapeout schedules.
StarRC Custom is in limited customer availability now, with general customer availability planned in December 2009.
Tuesday, September 1, 2009
Ubixum achieves product-ready design at First Silicon with Synopsys Galaxy Custom Designer solution
MOUNTAIN VIEW, USA: Synopsys Inc. announced that Ubixum has used Synopsys' Galaxy Custom Designer implementation solution to successfully design its latest advanced image sensor chip.
The chip has been verified to be product-ready with first silicon. Custom Designer is a modern-era custom implementation solution that delivers superior ease-of-use and leverages Synopsys' Galaxy Implementation Platform to provide a unified solution for custom and digital designs. The Custom Designer tool set enabled Ubixum to achieve higher productivity and better integration with their optimized design process.
"Synopsys' comprehensive custom implementation and simulation solutions, methodologies and support played a critical role in helping us to achieve first-silicon success," said Keith Fife, cofounder of Ubixum.
"The use of Custom Designer running natively on the OpenAccess database allowed us to easily integrate our own tools and to access the design through our own API. Custom Designer can handle very large designs with many complex polygon shapes found in our custom devices. Its ability to properly handle and display large arrays has been important to our productivity. We have already started to use Custom Designer for our next product."
Ubixum turned to Custom Designer for its modern architecture and completeness that delivers productivity with a familiar user interface while integrating a common use model for simulation, analysis, parasitic extraction and physical verification.
Custom Designer is built natively on the OpenAccess database for legacy designs and offers unprecedented openness and interoperability with process design kits (PDKs) from leading foundries. Key modules include a schematic editor featuring on-canvas editing and dynamic net highlighting.
The simulation environment provides a common use model allowing access to Synopsys simulators, including the HSPICE, CustomSim and Custom WaveView simulators. In addition, the results from Hercules DRC/LVS and Star-RCXT parasitic extraction are dynamically available within Custom Designer.
"Galaxy Custom Designer continues to meet the demands of our customers as design challenges continue to increase. Ubixum's successful design underscores Synopsys' commitment to deliver solutions that address our customers' design challenges and meet their productivity needs," said Bijan Kiani, vice president of Product Marketing for Design and Manufacturing Tools at Synopsys.
"We congratulate Ubixum on their first-pass silicon success, and we plan to continue working closely with them for the mutual benefit of both companies by extending the advanced design capabilities of Galaxy Custom Designer."
The chip has been verified to be product-ready with first silicon. Custom Designer is a modern-era custom implementation solution that delivers superior ease-of-use and leverages Synopsys' Galaxy Implementation Platform to provide a unified solution for custom and digital designs. The Custom Designer tool set enabled Ubixum to achieve higher productivity and better integration with their optimized design process.
"Synopsys' comprehensive custom implementation and simulation solutions, methodologies and support played a critical role in helping us to achieve first-silicon success," said Keith Fife, cofounder of Ubixum.
"The use of Custom Designer running natively on the OpenAccess database allowed us to easily integrate our own tools and to access the design through our own API. Custom Designer can handle very large designs with many complex polygon shapes found in our custom devices. Its ability to properly handle and display large arrays has been important to our productivity. We have already started to use Custom Designer for our next product."
Ubixum turned to Custom Designer for its modern architecture and completeness that delivers productivity with a familiar user interface while integrating a common use model for simulation, analysis, parasitic extraction and physical verification.
Custom Designer is built natively on the OpenAccess database for legacy designs and offers unprecedented openness and interoperability with process design kits (PDKs) from leading foundries. Key modules include a schematic editor featuring on-canvas editing and dynamic net highlighting.
The simulation environment provides a common use model allowing access to Synopsys simulators, including the HSPICE, CustomSim and Custom WaveView simulators. In addition, the results from Hercules DRC/LVS and Star-RCXT parasitic extraction are dynamically available within Custom Designer.
"Galaxy Custom Designer continues to meet the demands of our customers as design challenges continue to increase. Ubixum's successful design underscores Synopsys' commitment to deliver solutions that address our customers' design challenges and meet their productivity needs," said Bijan Kiani, vice president of Product Marketing for Design and Manufacturing Tools at Synopsys.
"We congratulate Ubixum on their first-pass silicon success, and we plan to continue working closely with them for the mutual benefit of both companies by extending the advanced design capabilities of Galaxy Custom Designer."
Wednesday, August 26, 2009
Renesas selects Synopsys Proteus OPC for 45-nm node production
MOUNTAIN VIEW, USA: Synopsys Inc. announced that Renesas Technology Corp., the world's No.1 supplier of microcontrollers and one of the world's premier semiconductor system solutions providers for mobile, automotive and PC/AV (Audio Visual) markets, has adopted Synopsys Proteus OPC for 45-nanometer (nm) production.
With the introduction of 45-nm and below technologies, the demand for optical proximity correction (OPC) becomes greater due to design complexity and layer volume, making time to market and cost of ownership critical factors in OPC vendor selection. Proteus OPC is the industry's most cost-effective solution, since its highly scalable engine runs on standard hardware.
"At Renesas, we are faced with the challenge to tape out large volumes of 45-nm designs with severe schedule constraints," said Hitoshi Sugihara, department manager, DFM & Digital EDA Technology Dept., Design and Development Unit at Renesas Technology Corp. "We selected Proteus OPC since it meets our technology, schedule, and costs requirements. This decision will enable us to sustain our leadership in microcontrollers and semiconductor system solutions."
Proteus delivers near-linear scalability so that designers can efficiently utilize hundreds of cores, allowing them to balance turnaround-time with cost. Proteus is the only tool that enables users to effectively manage technology requirements, turnaround time and cost through the inclusion of both frequency- and space-domain simulation engines.
With this capability, users can deploy the more accurate frequency-domain engine for the most critical layers and utilize the faster space-domain engine for the non-critical layers. ProGen, Proteus' highly customizable solution calibrates a single model that is utilized by both the space- and frequency-domain engines.
"As a leading semiconductor system solutions provider focusing on cutting-edge designs, Renesas has a critical need for an OPC solution that reduces turnaround time and cost," said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. "Renesas' adoption of Synopsys Proteus OPC is proof that Synopsys' technology is the best solution to address these advanced design requirements."
With the introduction of 45-nm and below technologies, the demand for optical proximity correction (OPC) becomes greater due to design complexity and layer volume, making time to market and cost of ownership critical factors in OPC vendor selection. Proteus OPC is the industry's most cost-effective solution, since its highly scalable engine runs on standard hardware.
"At Renesas, we are faced with the challenge to tape out large volumes of 45-nm designs with severe schedule constraints," said Hitoshi Sugihara, department manager, DFM & Digital EDA Technology Dept., Design and Development Unit at Renesas Technology Corp. "We selected Proteus OPC since it meets our technology, schedule, and costs requirements. This decision will enable us to sustain our leadership in microcontrollers and semiconductor system solutions."
Proteus delivers near-linear scalability so that designers can efficiently utilize hundreds of cores, allowing them to balance turnaround-time with cost. Proteus is the only tool that enables users to effectively manage technology requirements, turnaround time and cost through the inclusion of both frequency- and space-domain simulation engines.
With this capability, users can deploy the more accurate frequency-domain engine for the most critical layers and utilize the faster space-domain engine for the non-critical layers. ProGen, Proteus' highly customizable solution calibrates a single model that is utilized by both the space- and frequency-domain engines.
"As a leading semiconductor system solutions provider focusing on cutting-edge designs, Renesas has a critical need for an OPC solution that reduces turnaround time and cost," said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. "Renesas' adoption of Synopsys Proteus OPC is proof that Synopsys' technology is the best solution to address these advanced design requirements."
Friday, August 21, 2009
University of Southampton receives Charles Babbage Grant from Synopsys
MOUNTAIN VIEW, USA: Synopsys Inc. today announced that the School of Electronics and Computer Science (ECS) at the University of Southampton is the first Western European university to receive the Charles Babbage Grant from Synopsys.
Through the grant, ECS receives licenses of Synopsys' comprehensive electronic design automation (EDA) software and intellectual property. The grant also enabled the University to set up a brand new laboratory for virtual learning.
The Virtual Learning Environment focuses on integrated circuit design and also involves a new range of courses on advanced system-on-chip (SoC) design, with support and faculty training from Synopsys. The grant has enabled ECS to install new computer hardware in the virtual learning laboratory to support up to 20 students.
Synopsys software provides students and researchers the opportunity to utilize industrial tools for logic and physical synthesis, circuit simulation, nanometer device modeling and fabrication process modeling. Synopsys software serves as the foundation for an industry design flow where students get real-world, hands-on experience building and testing their designs.
"The School of Electronics and Computer Science is the largest of its kind in the UK with a long tradition of research in electronic engineering and computer science. This grant enables us to continue that tradition with the latest leading-edge commercial tools," said Dr. Matt Swabey, electronics teaching fellow at ECS.
"We can now give our students real quantitative experience in modeling SoCs, enabling them to modify and try out designs to achieve defined goals. This ability will be enormously valuable to our students."
Access to industrial design tools for advanced research and microelectronic design is a common challenge facing universities today. Synopsys helps resolve this issue through initiatives like the Charles Babbage Grant and its Worldwide University Program, which provide select universities with design software for modern electronic design flows and leading IC fabrication processes.
Previous grant recipients in the USA include Case Western Reserve University, Purdue University and Syracuse University.
John Chilton, Senior Vice President of Marketing & Strategic Development at Synopsys, formally opened the lab during an August 17th ceremony at the University of Southampton attended by students and faculty.
"Synopsys selected the University of Southampton because of its global reputation for leading-edge research and its academic focus on engineering and computer science," commented Chilton. "Through this grant, Synopsys enables the University to further its reputation as a leading academic institution and to give its students access to the latest tools and equipment, supporting their educational experience and preparing them for future roles in industry, academia or government."
Through the grant, ECS receives licenses of Synopsys' comprehensive electronic design automation (EDA) software and intellectual property. The grant also enabled the University to set up a brand new laboratory for virtual learning.
The Virtual Learning Environment focuses on integrated circuit design and also involves a new range of courses on advanced system-on-chip (SoC) design, with support and faculty training from Synopsys. The grant has enabled ECS to install new computer hardware in the virtual learning laboratory to support up to 20 students.
Synopsys software provides students and researchers the opportunity to utilize industrial tools for logic and physical synthesis, circuit simulation, nanometer device modeling and fabrication process modeling. Synopsys software serves as the foundation for an industry design flow where students get real-world, hands-on experience building and testing their designs.
"The School of Electronics and Computer Science is the largest of its kind in the UK with a long tradition of research in electronic engineering and computer science. This grant enables us to continue that tradition with the latest leading-edge commercial tools," said Dr. Matt Swabey, electronics teaching fellow at ECS.
"We can now give our students real quantitative experience in modeling SoCs, enabling them to modify and try out designs to achieve defined goals. This ability will be enormously valuable to our students."
Access to industrial design tools for advanced research and microelectronic design is a common challenge facing universities today. Synopsys helps resolve this issue through initiatives like the Charles Babbage Grant and its Worldwide University Program, which provide select universities with design software for modern electronic design flows and leading IC fabrication processes.
Previous grant recipients in the USA include Case Western Reserve University, Purdue University and Syracuse University.
John Chilton, Senior Vice President of Marketing & Strategic Development at Synopsys, formally opened the lab during an August 17th ceremony at the University of Southampton attended by students and faculty.
"Synopsys selected the University of Southampton because of its global reputation for leading-edge research and its academic focus on engineering and computer science," commented Chilton. "Through this grant, Synopsys enables the University to further its reputation as a leading academic institution and to give its students access to the latest tools and equipment, supporting their educational experience and preparing them for future roles in industry, academia or government."
Thursday, August 20, 2009
Synopsys announces financial results for Q3 2009
MOUNTAIN VIEW, USA: Synopsys Inc. today reported results for its third quarter ended July 31, 2009.
For the third quarter of fiscal 2009, Synopsys reported revenue of $345.2 million compared to $344.1 million for the third quarter of fiscal 2008.
"Synopsys again made excellent progress towards delivering on our year's objectives," said Aart de Geus, chairman and CEO of Synopsys. "We are actively working with customers to help them successfully navigate the economic recovery, and are positioning ourselves for even greater strength in the future."
GAAP results
On a generally accepted accounting principles (GAAP) basis, net income for the third quarter of fiscal 2009 was $47.4 million, or $0.32 per share, compared to $57.7 million, or $0.39 per share, for the third quarter of fiscal 2008, which included a $17.3 million tax benefit associated with the settlement of an IRS tax issue for fiscal years 2000 and 2001.
Non-GAAP results
On a non-GAAP basis, net income for the third quarter of fiscal 2009 was $68.3 million, or $0.47 per share, compared to non-GAAP net income of $64.5 million, or $0.44 per share, for the third quarter of fiscal 2008.
Financial targets
Synopsys also provided its financial targets for the fourth quarter and full fiscal year 2009. These targets constitute forward-looking information and are based on current expectations.
Fourth Quarter of Fiscal Year 2009 Targets:
Revenue: $335 million - $343 million
GAAP expenses: $297 million - $313 million
Non-GAAP expenses: $272 million - $282 million
Other income and expense: $0 - $3 million
Tax rate applied in non-GAAP net income calculations: approximately 26 percent
Fully diluted outstanding shares: 146 million - 149 million
GAAP earnings per share: $0.14 - $0.21
Non-GAAP earnings per share: $0.29 - $0.33
Revenue from backlog: greater than 90 percent
Full-Year Fiscal Year 2009 Targets:
Revenue: approximately $1.357 billion - $1.365 billion
Other income and expense: $11 million - $14 million
Tax rate applied in non-GAAP net income calculations: approximately 27 percent
Fully diluted outstanding shares: 144 million - 146.5 million
GAAP earnings per share: $1.16 - $1.23
Non-GAAP earnings per share: $1.71 - $1.75
Cash flow from operations: $190 million-$210 million (excludes potential impact of a tentative settlement with the Internal Revenue Service, described below).
In the second quarter, the company reached a tentative settlement with the IRS that would resolve a dispute regarding its 2002-2004 returns, primarily associated with the acquisition of Avant!.
The tentative settlement is subject to further approval by the government. If approved, we expect it to result in a cash payment to the IRS of approximately $50 million, most likely within the next 12 months. If the tentative settlement is approved, this payment would be fully offset by tax reductions in future years.
For the third quarter of fiscal 2009, Synopsys reported revenue of $345.2 million compared to $344.1 million for the third quarter of fiscal 2008.
"Synopsys again made excellent progress towards delivering on our year's objectives," said Aart de Geus, chairman and CEO of Synopsys. "We are actively working with customers to help them successfully navigate the economic recovery, and are positioning ourselves for even greater strength in the future."
GAAP results
On a generally accepted accounting principles (GAAP) basis, net income for the third quarter of fiscal 2009 was $47.4 million, or $0.32 per share, compared to $57.7 million, or $0.39 per share, for the third quarter of fiscal 2008, which included a $17.3 million tax benefit associated with the settlement of an IRS tax issue for fiscal years 2000 and 2001.
Non-GAAP results
On a non-GAAP basis, net income for the third quarter of fiscal 2009 was $68.3 million, or $0.47 per share, compared to non-GAAP net income of $64.5 million, or $0.44 per share, for the third quarter of fiscal 2008.
Financial targets
Synopsys also provided its financial targets for the fourth quarter and full fiscal year 2009. These targets constitute forward-looking information and are based on current expectations.
Fourth Quarter of Fiscal Year 2009 Targets:
Revenue: $335 million - $343 million
GAAP expenses: $297 million - $313 million
Non-GAAP expenses: $272 million - $282 million
Other income and expense: $0 - $3 million
Tax rate applied in non-GAAP net income calculations: approximately 26 percent
Fully diluted outstanding shares: 146 million - 149 million
GAAP earnings per share: $0.14 - $0.21
Non-GAAP earnings per share: $0.29 - $0.33
Revenue from backlog: greater than 90 percent
Full-Year Fiscal Year 2009 Targets:
Revenue: approximately $1.357 billion - $1.365 billion
Other income and expense: $11 million - $14 million
Tax rate applied in non-GAAP net income calculations: approximately 27 percent
Fully diluted outstanding shares: 144 million - 146.5 million
GAAP earnings per share: $1.16 - $1.23
Non-GAAP earnings per share: $1.71 - $1.75
Cash flow from operations: $190 million-$210 million (excludes potential impact of a tentative settlement with the Internal Revenue Service, described below).
In the second quarter, the company reached a tentative settlement with the IRS that would resolve a dispute regarding its 2002-2004 returns, primarily associated with the acquisition of Avant!.
The tentative settlement is subject to further approval by the government. If approved, we expect it to result in a cash payment to the IRS of approximately $50 million, most likely within the next 12 months. If the tentative settlement is approved, this payment would be fully offset by tax reductions in future years.
Tuesday, August 18, 2009
State of the global EDA industry: Dr. Pradip Dutta, Synopsys
A few weeks ago, I was fortunate enough to be able to speak with Dr. Pradip Dutta Corporate Vice President and Managing Director, and Treasurer, regarding the state of the global EDA industry and in India. What followed was a very interesting conversation, some of which is reproduced here!Any sign of improvements in EDA?
To start with, the state of the global EDA industry is well knowm, and it has also seen revenue drops Q-on-Q in the past. Are there any signs of improvement?
According to Dr. Dutta, the last several quarters in the semiconductor industry have been extremely challenging as consumer demand for electronic products has declined with the heavy stress on the global economy.
"While we are starting to see signs of the semiconductor industry rebounding off the bottom with inventory replenishment and an uptick in end demand for key consumer items such as PCs and mobile phones, the environment is expected to remain difficult at least well into next year.
"During this time, the challenge for the semiconductor industry and its suppliers will be to find the next level of efficiency. The good news is that across a broad field of applications, semiconductors are a key enabler to future prosperity. Green solutions, low-cost netbooks, advances in connectivity and evolving products like the Kindle are just a few examples of areas that could help drive future development.
"The long-term ramifications of this scenario on the EDA industry are starting to become visible. More than ever, customers want to get their products out on time, and get it right with high quality.
"In addition to some immediate cost-cutting to respond to the crisis, most semiconductor and design businesses are re-focusing their market strategies, streamlining their operations, de-risking their supplier and partner relationships, and in some cases actively pursuing consolidation opportunities to drive economic efficiency.
"This situation presents as an opportunity for EDA companies to focus on important product developments that can enable leading semiconductor design and manufacturing companies to not only create more advanced devices, but to simultaneously lower risks and cut costs. In today’s economy, companies need to find ways to manage expenses while still investing in the future so they don’t just survive the recession, they emerge from it stronger."
State of the Indian EDA industry
Obviously, it would be interesting to see how is the Indian EDA industry holding up in these times.
Dr. Dutta said that the Indian EDA industry is a combination of catering to global semiconductor players and addressing the needs of a domestic market that is slowly developing. The global players that operate out of India are rapidly moving up the value chain in terms of owning and architecting the next generation chips. This leads to an enormous opportunity for EDA companies to get associated at the front end of tool decisions.
"As you are aware, the level of technology that is being witnessed in the chips that are getting designed here is absolutely bleeding edge. The EDA companies are therefore paying concomitant attention to robust application support and in-house R&D effort. It has to be a full package here and now to address these kinds of customer requirements.
"Beyond the global players, India is seeing a few, but committed fabless design companies coming up in recent times. In addition to that, the Indian government is showing a lot of interest in country-specific programs, primarily in defense areas that require EDA support.
"We have also recently seen media reports about an "India Chip" being conceived at the central government level for domestic security applications. The ISA is working toward a blueprint for targeting semiconductors into a national agenda and hopefully, many ideas for systems and corresponding chips that will emanate from it to keep EDA companies interested," he added.
Technology challenges facing EDA
I also prompted Dr. Dutta to touch upon the technology challenges that the EDA industry is currently facing.
He said: "The EDA industry has traditionally addressed challenges in delivering best quality of results and shortest time to market. These challenges are now joined by controlling costs that could spiral out of control without advanced automation.
"The advanced state of semiconductor manufacturing today has exacerbated and expanded these challenges to unprecedented levels. The complexity of chips has grown to 100s of millions of transistors. Just managing data of this size is a challenge!
"Power has emerged as the dominant constraint over the traditional constraints of speed and area. The progression of Moore’s Law has resulted in some deposition layers of only five atoms, and as a result, previously second and third order physical effects must be thoroughly accounted for, along with their interactions. Finally, the tiniest manufacturing variabilities can now have a significant impact on yield, and systemic yield issues must be accounted for in design with a strong tie between design and manufacturing.
"In verification, the cost of fixing a missed bug and the opportunity cost are very high. While verification has long been a bottleneck to getting product development done on time, we have recently seen the verification challenge really expand. Verification used to be about RTL verification and circuit simulation. Today there’s a growing focus on software-to-silicon verification, encompassing a full range of challenges that also includes embedded software, system validation and integration testing.
"On the design side, energy has become a big focus. Scrutiny is being placed on energy consumption at every level, including consumer and industrial electronics. EDA companies preparing for success beyond the downturn are developing end-to-end solutions that can help their semiconductor industry customers optimize designs for low power.
"The combination of increasing IC complexity and shrinking semiconductor features is driving exponential demand for design and manufacturing-related compute resources. IC design companies are looking for ways to easily maximize the throughput of their multi-core compute infrastructure and improve overall time to results. EDA solutions employing advanced parallel, threaded and other optimized compute technologies can help IC design companies boost performance and productivity and accelerate design throughput.
"Today's IC design landscape is characterized by escalating design challenges on the one hand, and enormous pressure to control costs and speed time-to-market on the other. IC design companies are relying on their EDA vendors to help resolve this dichotomy."
EDA in areas of modeling and photomask correction
How and where does EDA fit into the big picture, particularly in the areas of modeling and photomask correction? This, I believe is part of Dr. Aart de Geus’ vision.
Dr. Dutta highlighted that nowadays, semiconductor manufacturers face unprecedented challenges in addressing the fast-rising cost and complexity of semiconductor process development and manufacturing.
To fulfill the demand for lower cost and more functional products, successive generations of semiconductor processes are subjected to scaling and integration of heterogeneous device types -- such as core logic MOSFETs, embedded Flash memory and high-voltage devices -- that require substantial investment in fabrication equipment and wafer experimental trials to meet product requirements.
Moreover, once the new process enters manufacturing, it is critical to achieve high manufacturing yield as rapidly as possible to maximize or even ensure profitability for the products built on the new process.
To help overcome these challenges, semiconductor manufacturers increasingly rely on simulation tools to guide equipment selection and wafer experimentation during process development, allowing them to reduce development cost and time. In addition, they deploy computational lithography and mask synthesis tools in production to improve the resolution of the lithography process.
Accellera-SPIRIT merger and impact on EDA industry
Fairly recently, Accellera and SPIRIT announced a merger. How will this union improve the development of language-based and IP standards.
According to Dr. Dutta, the co-ordination of activities between Accellera and SPIRIT will be more powerful for future standards that should include increased focus on system-level design and verification. Accellera has always focused on language-based standards, while SPIRIT focused on IP usage. Combining the two for system-level design is a big win-win for all ESL users.
"We think that this merger will also spawn new products with consistent interoperability among multiple design paradigms. At Synopsys, we are facilitating interoperability through the recently announced System-Level Catalyst program. We think that the ESL design methodologies will be successful.
"In addition, a certain amount of overlap always exists between independent standards efforts. This merger will help minimize the duplication of certain overheads and facilitate consistent technical discussion between the two efforts."
In that case, will this union be now able to keep up with the various developments in higher process nodes?
He added that Wwith the migration toward more advanced process nodes, device counts will continue to increase. As a result of this complexity, the cost of managing design and verification will also rise. Therefore, new paradigms that leverage existing methodologies must evolve. Both, language-based and IP-based approaches have been successful so far.
"We expect that the Accellera/SPIRIT merger will create a new generation of standards enabling newer methodologies to deal with these complexities. While it is possible that a revolutionary approach will be developed in the future, it is likely that this evolutionary approach will appeal to most designers because it leverages the existing skill-set and infrastructure."
You can also read the full interview on ISA's web site.
Thursday, August 13, 2009
Synopsys' HDMI IP solution for 90nm to 40nm process technologies
MOUNTAIN VIEW, USA: Synopsys Inc. today announced the broad availability of silicon-proven High-Definition Multimedia Interface (HDMI) transmitter and receiver digital controllers and PHY IP solutions as part of Synopsys' DesignWare IP portfolio.
Synopsys' DesignWare IP for the HDMI interface is compliant to the standard specification and supports High-bandwidth Digital Content Protection (HDCP). Synopsys also provides a roadmap for HDMI 1.4 with product availability anticipated at the end of 2009.
The IP is available in leading process technologies from 90-nm down to 40-nm, and includes sample software drivers for system development. Synopsys' HDMI IP solution is differentiated in terms of feature set, available process nodes and worldwide technical support.
The DesignWare HDMI IP offering includes a comprehensive set of IP deliverables that helps designers quickly embed this complex interface into next generation multimedia SoCs with less risk. Furthermore, the DesignWare HDMI IP solution provides differentiated features including:
* Superior analog front end to support longer HDMI cables, while maintaining high performance.
* Configurable RTL allow designers to optimize gate count and power consumption by choosing only the features required in their application.
* Built-in (on-die) termination resistors for lower bill-of-materials.
* Numerous optional features as well as a choice of various video and audio interfaces for ease of integration.
"HDMI is one of fastest growing multimedia interfaces and is gaining wide-spread acceptance as the standard for communicating between high-performance digital devices," said Paul O'Donovan, principal analyst at Gartner.
"Our research indicates exponential growth in the number of HDMI ports for mobile/portable markets such as camcorders and cameras. HDMI IP will play a key role in enabling designers to integrate the HDMI interface in their next-generation systems."
"Valens continues to develop next generation products for the high definition home entertainment market, and we chose Synopsys to provide us with a high-quality, compliant HDMI IP solution that would help us quickly implement the latest functionality into our advanced SoCs," said Massad Eyal, vice president of research and development R&D at Valens Semiconductor.
"Synopsys' silicon-proven DesignWare HDMI IP enables us to deliver compelling products to the market faster and with significantly less risk."
"HDMI has emerged as the de-facto multimedia interface standard for high-definition consumer electronics and mobile devices," said John Koeter, vice president of marketing for the Solutions Group.
"With Synopsys' extensive customer base, established sales and support infrastructure, and vast porting capabilities, designers can turn to a trusted HDMI IP solution that can be integrated into their SoC with less risk and improved time-to-market."
The DesignWare HDMI 1.3 Transmit and Receive Controllers and PHY IP are available now in leading 90-nm, 65-nm, 45-nm, and 40-nm process technologies. The DesignWare HDMI 1.4 IP solution is currently in development and anticipated to be available at the end of 2009.
Synopsys' DesignWare IP for the HDMI interface is compliant to the standard specification and supports High-bandwidth Digital Content Protection (HDCP). Synopsys also provides a roadmap for HDMI 1.4 with product availability anticipated at the end of 2009.
The IP is available in leading process technologies from 90-nm down to 40-nm, and includes sample software drivers for system development. Synopsys' HDMI IP solution is differentiated in terms of feature set, available process nodes and worldwide technical support.
The DesignWare HDMI IP offering includes a comprehensive set of IP deliverables that helps designers quickly embed this complex interface into next generation multimedia SoCs with less risk. Furthermore, the DesignWare HDMI IP solution provides differentiated features including:
* Superior analog front end to support longer HDMI cables, while maintaining high performance.
* Configurable RTL allow designers to optimize gate count and power consumption by choosing only the features required in their application.
* Built-in (on-die) termination resistors for lower bill-of-materials.
* Numerous optional features as well as a choice of various video and audio interfaces for ease of integration.
"HDMI is one of fastest growing multimedia interfaces and is gaining wide-spread acceptance as the standard for communicating between high-performance digital devices," said Paul O'Donovan, principal analyst at Gartner.
"Our research indicates exponential growth in the number of HDMI ports for mobile/portable markets such as camcorders and cameras. HDMI IP will play a key role in enabling designers to integrate the HDMI interface in their next-generation systems."
"Valens continues to develop next generation products for the high definition home entertainment market, and we chose Synopsys to provide us with a high-quality, compliant HDMI IP solution that would help us quickly implement the latest functionality into our advanced SoCs," said Massad Eyal, vice president of research and development R&D at Valens Semiconductor.
"Synopsys' silicon-proven DesignWare HDMI IP enables us to deliver compelling products to the market faster and with significantly less risk."
"HDMI has emerged as the de-facto multimedia interface standard for high-definition consumer electronics and mobile devices," said John Koeter, vice president of marketing for the Solutions Group.
"With Synopsys' extensive customer base, established sales and support infrastructure, and vast porting capabilities, designers can turn to a trusted HDMI IP solution that can be integrated into their SoC with less risk and improved time-to-market."
The DesignWare HDMI 1.3 Transmit and Receive Controllers and PHY IP are available now in leading 90-nm, 65-nm, 45-nm, and 40-nm process technologies. The DesignWare HDMI 1.4 IP solution is currently in development and anticipated to be available at the end of 2009.
Thursday, August 6, 2009
Synopsys keeps IT projects on track with BMC Software
HOUSTON, USA: As a leader in electronic design automation for the global electronics industry, Synopsys, Inc. gives its customers an edge by delivering products quickly with lower cost and risk.
Behind the scenes, Synopsys Information Technology relies on BMC Software (NYSE:BMC) to consistently keep IT projects within one percent of budget goals.
“BMC gives us a line of sight into our projects and spend, so we can do a better job prioritizing our work and staying on budget,” said Debra Martucci, chief information officer at Synopsys. “Now we can take a complete inventory of our resources and shift them as priorities change to operate most efficiently. The end result is better product and service for our internal customers.”
BMC’s IT Business Management Suite delivers an integrated view of Synopsys’ IT portfolio in the context of the services and applications the department provides.
By centralizing data from multiple sources into a single view, Synopsys IT has better visibility into its resources, finances and tasks. Synopsys uses BMC to track all IT-related projects –- from smaller tasks to major application and infrastructure upgrades and specialty projects like mergers and acquisitions.
Synopsys IT is also leveraging BMC Human Capital Management (HCM) to handle, track and deploy IT personnel. HCM tracks project and service hours for Synopsys’ IT staff, contractors and interns to better understand and evaluate how employees use their time and map project demand to workforce capacity. The solution drives down costs and improves efficiency by aligning IT and human resources functions with business objectives.
Behind the scenes, Synopsys Information Technology relies on BMC Software (NYSE:BMC) to consistently keep IT projects within one percent of budget goals.
“BMC gives us a line of sight into our projects and spend, so we can do a better job prioritizing our work and staying on budget,” said Debra Martucci, chief information officer at Synopsys. “Now we can take a complete inventory of our resources and shift them as priorities change to operate most efficiently. The end result is better product and service for our internal customers.”
BMC’s IT Business Management Suite delivers an integrated view of Synopsys’ IT portfolio in the context of the services and applications the department provides.
By centralizing data from multiple sources into a single view, Synopsys IT has better visibility into its resources, finances and tasks. Synopsys uses BMC to track all IT-related projects –- from smaller tasks to major application and infrastructure upgrades and specialty projects like mergers and acquisitions.
Synopsys IT is also leveraging BMC Human Capital Management (HCM) to handle, track and deploy IT personnel. HCM tracks project and service hours for Synopsys’ IT staff, contractors and interns to better understand and evaluate how employees use their time and map project demand to workforce capacity. The solution drives down costs and improves efficiency by aligning IT and human resources functions with business objectives.
Tuesday, August 4, 2009
Rockchip allies with Synopsys, Chartered to achieve first-pass silicon success
FUZHOU, CHINA, MOUNTAIN VIEW, USA, & SINGAPORE: Fuzhou Rockchip Electronics Co. Ltd., Synopsys, Inc. and Chartered Semiconductor Manufacturing Ltd. announced that Rockchip has achieved first-time silicon success on its next-generation multimedia system-on-a-chip (SoC), using a combination of Synopsys' tools, intellectual property (IP) and services with Chartered's 65nm manufacturing technology.
The RK 28 multimedia SoC, Rockchip's first mass-production 65nm chip designed in China and targeted primarily for the China market, is an application processor for mobile handheld devices.
The RK28 chip was designed with Synopsys' full RTL-to-GDSII flow using best-in-class technology from the Galaxy Implementation and Discovery Verification Platforms, as well as DesignWare IP, and implemented in Chartered's advanced low-power (65nm LP) process.
"The mobile applications served by our customers require chips that can meet stringent low-power specifications without compromising performance, and our multimedia RK28 SoC delivers on both fronts," said Feng Chen, chief marketing officer of Rockchip.
"Our EDA and manufacturing partners played key roles in the success of our program. Our ability to reach design closure within our market window then rapidly move from tapeout to production silicon validates the choices we made with Synopsys and Chartered."
Since the 65nm RK28 represented Rockchip's first design at a new technology node, production-proven technology and knowledge sharing among the parties were essential to project success.
The design took advantage of Synopsys' IC Compiler with Zroute technology to exceed its 500MHz performance target, while employing advanced low-power design techniques such as multi-voltage and power gating to reduce power consumption.
The production-proven VMM verification methodology and VCS functional verification solution were used to verify Rockchip's design. The RK28 chip also integrates silicon-proven Synopsys DesignWare IP, including USB 2.0 PHY, USB HS OTG Controller and SD/MMC Host Controller.
Design consultants from Synopsys Professional Services worked closely with Rockchip's engineers throughout the project, merging critical skills and expertise to mitigate project risks and address schedule pressures. The implementation of the design in Chartered's 65nm LP process enabled the chip to achieve target power, performance and area goals with first silicon, and quickly ramp to production volume.
"At Chartered, we understand our customers need technology and solutions with low risk and high yield to speed time to market, and we are pleased to see our collaboration with Rockchip and Synopsys achieve first-pass silicon success," said Dr. Liang-Choo "LC" Hsia, senior vice president of technology development at Chartered.
"The Rockchip-Synopsys-Chartered collaboration demonstrates how a strong foundation can support companies on the leading edge of design, especially those in the consumer entertainment and mobile applications."
"Rockchip joins a growing list of innovative chip developers that are taking advantage of Synopsys' broad portfolio of tools, IP and services to accomplish their aggressive design goals with efficiency," said John Chilton, senior vice president of marketing and strategic development at Synopsys.
"Our collaboration with Rockchip and Chartered demonstrates our commitment to serve customers in China and the rest of the world with solutions that accelerate tapeout and enhance manufacturability."
The RK 28 multimedia SoC, Rockchip's first mass-production 65nm chip designed in China and targeted primarily for the China market, is an application processor for mobile handheld devices.
The RK28 chip was designed with Synopsys' full RTL-to-GDSII flow using best-in-class technology from the Galaxy Implementation and Discovery Verification Platforms, as well as DesignWare IP, and implemented in Chartered's advanced low-power (65nm LP) process.
"The mobile applications served by our customers require chips that can meet stringent low-power specifications without compromising performance, and our multimedia RK28 SoC delivers on both fronts," said Feng Chen, chief marketing officer of Rockchip.
"Our EDA and manufacturing partners played key roles in the success of our program. Our ability to reach design closure within our market window then rapidly move from tapeout to production silicon validates the choices we made with Synopsys and Chartered."
Since the 65nm RK28 represented Rockchip's first design at a new technology node, production-proven technology and knowledge sharing among the parties were essential to project success.
The design took advantage of Synopsys' IC Compiler with Zroute technology to exceed its 500MHz performance target, while employing advanced low-power design techniques such as multi-voltage and power gating to reduce power consumption.
The production-proven VMM verification methodology and VCS functional verification solution were used to verify Rockchip's design. The RK28 chip also integrates silicon-proven Synopsys DesignWare IP, including USB 2.0 PHY, USB HS OTG Controller and SD/MMC Host Controller.
Design consultants from Synopsys Professional Services worked closely with Rockchip's engineers throughout the project, merging critical skills and expertise to mitigate project risks and address schedule pressures. The implementation of the design in Chartered's 65nm LP process enabled the chip to achieve target power, performance and area goals with first silicon, and quickly ramp to production volume.
"At Chartered, we understand our customers need technology and solutions with low risk and high yield to speed time to market, and we are pleased to see our collaboration with Rockchip and Synopsys achieve first-pass silicon success," said Dr. Liang-Choo "LC" Hsia, senior vice president of technology development at Chartered.
"The Rockchip-Synopsys-Chartered collaboration demonstrates how a strong foundation can support companies on the leading edge of design, especially those in the consumer entertainment and mobile applications."
"Rockchip joins a growing list of innovative chip developers that are taking advantage of Synopsys' broad portfolio of tools, IP and services to accomplish their aggressive design goals with efficiency," said John Chilton, senior vice president of marketing and strategic development at Synopsys.
"Our collaboration with Rockchip and Chartered demonstrates our commitment to serve customers in China and the rest of the world with solutions that accelerate tapeout and enhance manufacturability."
Wednesday, July 29, 2009
Teradici chooses Synopsys as primary EDA partner
MOUNTAIN VIEW, USA: Synopsys Inc. announced that Teradici Corp., a provider of groundbreaking PC-over-IP technology, has signed an expanded business agreement to establish Synopsys as its primary EDA partner.
As a result of the latest multi-year agreement, Teradici has consolidated on Synopsys' Galaxy Implementation and Discovery Verification Platforms for its implementation, verification and analog/mixed-signal flows, as well as extended their use of Synopsys DesignWare IP cores and consulting services.
"Over the past several years, we have built a successful relationship with Synopsys by utilizing their best-in-class design tools, interface IP and design services to mitigate our project risks and accelerate the delivery of our breakthrough technology to our customers," said Maher Fahmi, vice president of Silicon Engineering and co-founder, Teradici.
"As we grow our competencies in new areas such as analog design and simulation, we know we can continue to rely on the breadth and quality of Synopsys' technology and the outstanding support of its field and services teams."
"In today's challenging business climate, innovative chip developers like Teradici are looking for partners who will not only help them distinguish their products, but do so in a manner that makes them more efficient and productive across all their design flows," said John Chilton, senior vice president of marketing and strategic development at Synopsys.
"Our broadened relationship enables Teradici to take advantage of Synopsys' growing technology and services portfolio so they can focus on developing and delivering their unique network-delivered computing products to the marketplace."
As part of the new agreement, Teradici has expanded access to products, services and IP from Synopsys, including the Galaxy Implementation Platform's IC Compiler place-and-route technology, Design Compiler Ultra synthesis, Galaxy Custom Designer mixed-signal implementation, DFTMAX compression, TetraMAX automatic test pattern generation, PrimeTime SI signal integrity analysis, Star-RCXT parasitic extraction and Hercules physical verification; the Discovery Verification Platform's VCS, HSPICE, and HSIM simulators for analog and digital verification, and MVRC and MVSIM for low power verification; and DesignWare IP for USB 2.0 and Ethernet.
As a result of the latest multi-year agreement, Teradici has consolidated on Synopsys' Galaxy Implementation and Discovery Verification Platforms for its implementation, verification and analog/mixed-signal flows, as well as extended their use of Synopsys DesignWare IP cores and consulting services.
"Over the past several years, we have built a successful relationship with Synopsys by utilizing their best-in-class design tools, interface IP and design services to mitigate our project risks and accelerate the delivery of our breakthrough technology to our customers," said Maher Fahmi, vice president of Silicon Engineering and co-founder, Teradici.
"As we grow our competencies in new areas such as analog design and simulation, we know we can continue to rely on the breadth and quality of Synopsys' technology and the outstanding support of its field and services teams."
"In today's challenging business climate, innovative chip developers like Teradici are looking for partners who will not only help them distinguish their products, but do so in a manner that makes them more efficient and productive across all their design flows," said John Chilton, senior vice president of marketing and strategic development at Synopsys.
"Our broadened relationship enables Teradici to take advantage of Synopsys' growing technology and services portfolio so they can focus on developing and delivering their unique network-delivered computing products to the marketplace."
As part of the new agreement, Teradici has expanded access to products, services and IP from Synopsys, including the Galaxy Implementation Platform's IC Compiler place-and-route technology, Design Compiler Ultra synthesis, Galaxy Custom Designer mixed-signal implementation, DFTMAX compression, TetraMAX automatic test pattern generation, PrimeTime SI signal integrity analysis, Star-RCXT parasitic extraction and Hercules physical verification; the Discovery Verification Platform's VCS, HSPICE, and HSIM simulators for analog and digital verification, and MVRC and MVSIM for low power verification; and DesignWare IP for USB 2.0 and Ethernet.
Synopsys intros Galaxy 2009 with 2x faster throughput
MOUNTAIN VIEW, USA: Synopsys Inc. introduced the latest release of its Galaxy Implementation Platform delivering 2x faster design implementation and signoff throughput with new multicore performance and multi-corner/multi-mode (MCMM) technologies.
Built-in support for multicore processing across the Galaxy Platform enables engineering teams to immediately boost runtime performance using their existing compute servers. Additionally, the Galaxy Platform includes new MCMM technology providing improved quality of results and faster design closure when using a combined Design Compiler® Graphical and IC Compiler flow. The Galaxy 2009 release is available now.
In March 2008, Synopsys announced a broad multicore initiative to deploy advanced parallel, threaded and other optimized compute technologies across its verification, implementation and manufacturing platforms to reduce time-to-results. The most recent result of this initiative is the expansion of the Galaxy Platform with multicore technology to deliver 2x faster performance for design implementation and signoff.
Multicore technologies being introduced with the Design Compiler synthesis, TetraMAX automatic test pattern generation (ATPG), IC Compiler place-and-route, IC Validator physical verification, Star-RCXT extraction and PrimeTime static timing analysis solutions deliver breakthrough productivity and faster design closure.
Measurable performance improvements deploying these technologies include:
* Design Compiler: 1.5x faster runtime with four processor cores.
* IC Compiler: 2.5x faster runtime with MCMM using four cores.
* Star-RCXT: 3x faster performance using four cores and 8x faster using 16 cores.
* PrimeTime: 50 percent faster, on average, for typical production flows compared with the previous release. In addition, a faster run mode in PrimeTime ideal for early signal integrity analysis delivers 2x faster runtime, on average.
* TetraMAX: 3x faster performance with four cores and 6x faster performance with eight cores
* IC Validator: near-linear scalability with 7x speedup using eight cores and 20x speedup using 25 cores.
New MCMM synthesis technology in Design Compiler Graphical, a component of Synopsys' Eclypse Low Power Solution, supports concurrent optimization for worst-case leakage and timing corners. Design Compiler uses a common multi-scenario definition with IC Compiler.
Actual design results have shown 10 percent lower leakage when using MCMM optimization with a combined Design Compiler and IC Compiler flow. PrimeTime's Distributed Multi-Scenario Analysis (DMSA) capability has been extended to deliver a more comprehensive set of engineering change orders (ECOs) for both setup and hold timing violations, thus minimizing late-stage iterations in the design process.
"With the increasing complexity and diversity of system-on-chip designs, faster, unified implementation solutions are essential," said Bijan Kiani, vice president of product marketing, Design and Manufacturing Products, at Synopsys.
"Galaxy 2009 delivers faster runtime performance with comprehensive multicore and MCMM support for better quality of results and faster design closure. As a result, engineers are able to achieve higher productivity on their most challenging designs."
Galaxy Implementation Platform
The Galaxy Implementation Platform is a comprehensive solution for cell-based and custom IC implementation. Galaxy accepts design intent in industry standard formats and generates a production-ready IC design in GDSII format. Galaxy RTL and physical implementation concurrently balance design constraints by performing intelligent tradeoffs between speed, area, power, test and manufacturability.
Galaxy signoff engines accurately model complex physical interactions to ensure signal and power integrity. Coherent algorithms for parasitic extraction and timing produce correlated results.
Built-in support for multicore processing across the Galaxy Platform enables engineering teams to immediately boost runtime performance using their existing compute servers. Additionally, the Galaxy Platform includes new MCMM technology providing improved quality of results and faster design closure when using a combined Design Compiler® Graphical and IC Compiler flow. The Galaxy 2009 release is available now.
In March 2008, Synopsys announced a broad multicore initiative to deploy advanced parallel, threaded and other optimized compute technologies across its verification, implementation and manufacturing platforms to reduce time-to-results. The most recent result of this initiative is the expansion of the Galaxy Platform with multicore technology to deliver 2x faster performance for design implementation and signoff.
Multicore technologies being introduced with the Design Compiler synthesis, TetraMAX automatic test pattern generation (ATPG), IC Compiler place-and-route, IC Validator physical verification, Star-RCXT extraction and PrimeTime static timing analysis solutions deliver breakthrough productivity and faster design closure.
Measurable performance improvements deploying these technologies include:
* Design Compiler: 1.5x faster runtime with four processor cores.
* IC Compiler: 2.5x faster runtime with MCMM using four cores.
* Star-RCXT: 3x faster performance using four cores and 8x faster using 16 cores.
* PrimeTime: 50 percent faster, on average, for typical production flows compared with the previous release. In addition, a faster run mode in PrimeTime ideal for early signal integrity analysis delivers 2x faster runtime, on average.
* TetraMAX: 3x faster performance with four cores and 6x faster performance with eight cores
* IC Validator: near-linear scalability with 7x speedup using eight cores and 20x speedup using 25 cores.
New MCMM synthesis technology in Design Compiler Graphical, a component of Synopsys' Eclypse Low Power Solution, supports concurrent optimization for worst-case leakage and timing corners. Design Compiler uses a common multi-scenario definition with IC Compiler.
Actual design results have shown 10 percent lower leakage when using MCMM optimization with a combined Design Compiler and IC Compiler flow. PrimeTime's Distributed Multi-Scenario Analysis (DMSA) capability has been extended to deliver a more comprehensive set of engineering change orders (ECOs) for both setup and hold timing violations, thus minimizing late-stage iterations in the design process.
"With the increasing complexity and diversity of system-on-chip designs, faster, unified implementation solutions are essential," said Bijan Kiani, vice president of product marketing, Design and Manufacturing Products, at Synopsys.
"Galaxy 2009 delivers faster runtime performance with comprehensive multicore and MCMM support for better quality of results and faster design closure. As a result, engineers are able to achieve higher productivity on their most challenging designs."
Galaxy Implementation Platform
The Galaxy Implementation Platform is a comprehensive solution for cell-based and custom IC implementation. Galaxy accepts design intent in industry standard formats and generates a production-ready IC design in GDSII format. Galaxy RTL and physical implementation concurrently balance design constraints by performing intelligent tradeoffs between speed, area, power, test and manufacturability.
Galaxy signoff engines accurately model complex physical interactions to ensure signal and power integrity. Coherent algorithms for parasitic extraction and timing produce correlated results.
Tuesday, July 28, 2009
ARM, Chartered, IBM, Samsung and Synopsys to deliver vertically optimized solution for 32/28nm mobile SoC designs
SAN FRANCISCO, USA: In a move that addresses fundamental challenges in creating advanced systems-on-chips (SoCs), ARM, Chartered Semiconductor Manufacturing Ltd, IBM, Samsung Electronics Co. Ltd and Synopsys Inc. announced at the Design Automation Conference (DAC) an agreement to develop a comprehensive technology enablement solution for the design and manufacture of mobile Internet-optimized devices.
The objective of this collaboration is to leverage innovations in material science, mobile multimedia implementation and SoC design to lower risk and improve time-to-market for advanced mobile products. This complete design chain collaboration of technology leaders intends to integrate the following components:
ARM high-performance, low-power processor architecture for mobile applications, and optimized suite of physical intellectual property (physical IP) 32/28nm low-power/low-leakage, high-k metal-gate (HKMG) synchronized foundry services through the Common Platform manufacturing alliance of IBM, Chartered and Samsung.
Synopsys Lynx Design System, including Galaxy Implementation Platform for SoC implementation, as well as DesignWare connectivity IP. As semiconductor technology approaches fundamental physical limits and design complexity reaches unprecedented levels, a deeper type of technical alignment is essential.
Going beyond an existing track record of successful cooperation at previous nodes, this agreement among ARM, the Common Platform companies, and Synopsys represents a new level of collaboration necessary to address the cost and technical challenges associated with advanced SoC design and manufacturing. This initiative aligns strategy, technology roadmaps and customer deliveries.
"The Common Platform alliance's expanded engagement approach with ARM, and now Synopsys, means working more closely together with earlier access to each other's technology innovations, integrating and optimizing our capabilities for clients," said Michael J. Cadigan, general manager, IBM Microelectronics Division, on behalf of the Common Platform alliance companies. "The benefits are clear and differentiated: lower risk, lower cost and faster time-to-market."
Combination of strengths
Each company brings unique technology and expertise that, when combined through joint collaboration, creates an optimized solution not available from other sources.
ARM brings a robust portfolio of logic, memory and interface IP, as well as its widely adopted Cortex processor family that is used in a broad array of mobile applications. ARM Physical IP optimized for the Common Platform 32/28nm process delivers valuable low-power and system cost benefits. The intention of this agreement is to ensure the IP is fully optimized with the Synopsys design flow.
"The complexity of advanced manufacturing process technology requires a tight connection between the Physical IP, processor cores and EDA methodology," said Warren East, CEO, ARM. "Early collaboration between these leading companies will significantly improve the performance, power and area achievable by our partners and deliver increased value to the end products."
Synopsys brings a suite of tool components from its Galaxy Implementation Platform, Lynx Design System and DesignWare connectivity IP providing the foundation of the solutions design flow. By tuning the automated front-to-back flow to run on Common Platform technology with ARM processor and physical IP, the flow is aimed at delivering a streamlined implementation path that can reduce the total cost of developing an optimized SoC, while helping speed time-to-market and reduce risk.
"This unique ARM-Synopsys-Common Platform collaboration can alleviate costs and risks by harnessing the leading players in silicon technology, IP, tools and flow enablement to integrate and optimize the path from software to silicon," said Aart de Geus, chairman and CEO of Synopsys.
"Through this alignment, we plan to deliver early 32/28 nanometer tool and IP enablement, plus a complete, vertically optimized design solution based on the Synopsys Lynx Design System to provide customers the lowest cost of design and fastest time-to-market for next-generation mobile SoC designs."
The Common Platform 32/28nm process uses an innovative high-k metal-gate (HKMG) approach to address the limitations of polysilicon technology. It leverages the research and development efforts of the IBM joint technology development alliance to offer a high-performance, low-power manufacturing platform. The process offering is available with synchronized foundry services from all three Common Platform companies, ensuring customer freedom of choice and maximum sourcing flexibility.
The collaborative effort began a year ago. Initial 32nm low-power tool and IP enablement has been released and a steady stream of early customer deliverables is targeted in the coming months. Supporting physical and processor IP, connectivity IP, process design kits and tools will be available from their respective suppliers.
Demonstrations of the technology based on initial test chips will be shown at the 2009 DAC in the ARM-Common Platform-Synopsys "Innovation Optimized" exhibit (booth #1114).
The objective of this collaboration is to leverage innovations in material science, mobile multimedia implementation and SoC design to lower risk and improve time-to-market for advanced mobile products. This complete design chain collaboration of technology leaders intends to integrate the following components:
ARM high-performance, low-power processor architecture for mobile applications, and optimized suite of physical intellectual property (physical IP) 32/28nm low-power/low-leakage, high-k metal-gate (HKMG) synchronized foundry services through the Common Platform manufacturing alliance of IBM, Chartered and Samsung.
Synopsys Lynx Design System, including Galaxy Implementation Platform for SoC implementation, as well as DesignWare connectivity IP. As semiconductor technology approaches fundamental physical limits and design complexity reaches unprecedented levels, a deeper type of technical alignment is essential.
Going beyond an existing track record of successful cooperation at previous nodes, this agreement among ARM, the Common Platform companies, and Synopsys represents a new level of collaboration necessary to address the cost and technical challenges associated with advanced SoC design and manufacturing. This initiative aligns strategy, technology roadmaps and customer deliveries.
"The Common Platform alliance's expanded engagement approach with ARM, and now Synopsys, means working more closely together with earlier access to each other's technology innovations, integrating and optimizing our capabilities for clients," said Michael J. Cadigan, general manager, IBM Microelectronics Division, on behalf of the Common Platform alliance companies. "The benefits are clear and differentiated: lower risk, lower cost and faster time-to-market."
Combination of strengths
Each company brings unique technology and expertise that, when combined through joint collaboration, creates an optimized solution not available from other sources.
ARM brings a robust portfolio of logic, memory and interface IP, as well as its widely adopted Cortex processor family that is used in a broad array of mobile applications. ARM Physical IP optimized for the Common Platform 32/28nm process delivers valuable low-power and system cost benefits. The intention of this agreement is to ensure the IP is fully optimized with the Synopsys design flow.
"The complexity of advanced manufacturing process technology requires a tight connection between the Physical IP, processor cores and EDA methodology," said Warren East, CEO, ARM. "Early collaboration between these leading companies will significantly improve the performance, power and area achievable by our partners and deliver increased value to the end products."
Synopsys brings a suite of tool components from its Galaxy Implementation Platform, Lynx Design System and DesignWare connectivity IP providing the foundation of the solutions design flow. By tuning the automated front-to-back flow to run on Common Platform technology with ARM processor and physical IP, the flow is aimed at delivering a streamlined implementation path that can reduce the total cost of developing an optimized SoC, while helping speed time-to-market and reduce risk.
"This unique ARM-Synopsys-Common Platform collaboration can alleviate costs and risks by harnessing the leading players in silicon technology, IP, tools and flow enablement to integrate and optimize the path from software to silicon," said Aart de Geus, chairman and CEO of Synopsys.
"Through this alignment, we plan to deliver early 32/28 nanometer tool and IP enablement, plus a complete, vertically optimized design solution based on the Synopsys Lynx Design System to provide customers the lowest cost of design and fastest time-to-market for next-generation mobile SoC designs."
The Common Platform 32/28nm process uses an innovative high-k metal-gate (HKMG) approach to address the limitations of polysilicon technology. It leverages the research and development efforts of the IBM joint technology development alliance to offer a high-performance, low-power manufacturing platform. The process offering is available with synchronized foundry services from all three Common Platform companies, ensuring customer freedom of choice and maximum sourcing flexibility.
The collaborative effort began a year ago. Initial 32nm low-power tool and IP enablement has been released and a steady stream of early customer deliverables is targeted in the coming months. Supporting physical and processor IP, connectivity IP, process design kits and tools will be available from their respective suppliers.
Demonstrations of the technology based on initial test chips will be shown at the 2009 DAC in the ARM-Common Platform-Synopsys "Innovation Optimized" exhibit (booth #1114).
Synopsys, Mentor, CoWare join ARM Fast Models Enablement Program
CAMBRIDGE, UK: ARM announced at DAC, San Francisco, that CoWare, Mentor Graphics and Synopsys Inc. have joined the ARM Fast Models Enablement Program.
Members of the Program are able to integrate fully validated Fast Models from ARM, for a range of ARM processors, into their virtual platform environments and deliver to their customers.
This ensures that mutual customers can create complete ARM Powered virtual platforms using the design flow of their choice. By using virtual platforms built around ARM processor Fast Models, engineers can develop software well in advance of final hardware implementation, with application and driver software running at near to real-time system performance.
The Fast Models product family from ARM includes programmer's view (PV) models for the ARM9, ARM11 and Cortex families of processors, including the Cortex-A9 MPCore multicore processor. The Fast Model products also include configuration tools that enable the export of ARM processor-based subsystems with OSCI SystemC and TLM-2.0 compliant interfaces.
"We are seeing a growing demand for high-performance models in the industry," said John Cornish, EVP and general manager, System Design Division, ARM. "The TLM-2.0 interface enables our customers to combine our processor Fast Models with models of their other IP to create complete virtual platforms in the design environment of their choice."
"CoWare has successfully delivered Electronic System Virtualization solutions for ARM processor-based designs for many years supporting architecture design, verification, software development, integration and test. With our further engagement in this broader program covering the ARM Cortex Fast Models, we continue to expand this position to serve the growing needs of our joint customers," said Marc Serughetti, vice president of Marketing and Business Development at CoWare Inc.
"This integration and partnership is already proven and in use at several customers resulting in significant time-to-market benefits for those customers."
"Mentor’s Vista technology offers a comprehensive architecture design and prototyping solution that relies on fast processor and peripheral models as an essential part of the solution. The integration of the architecturally accurate ARM Fast Models into our Vista Platform will deliver significant value to our mutual customers," said Simon Bloch, Mentor Graphics vice president and general manager, design and synthesis division.
"In addition, ARM’s Fast Models are compatible with Vista’s TLM scalable modeling methodology that provides the timing and power layers essential for optimizing performance and power at the transaction level of abstraction."
"As a leading IP provider, Synopsys already provides OSCI TLM-2.0 compliant transaction-level models for several processor families including ARM and Synopsys DesignWare Cores and components for SoC infrastructure, AMBA interconnect, CoreConnect and PrimeCell peripherals in the Synopsys DesignWare System-level Library," said Frank Schirrmeister, director product marketing for the Solutions Group at Synopsys.
"The ARM PV Enablement Program allows our users to draw from a larger number of models and enables Synopsys to validate interoperability of Synopsys’ Innovator development environment for virtual platforms with ARM processor-based subsystems using Fast Models from ARM."
Availability
Fast Models Version 5.0 including the SystemC/TLM-2.0 compatible export capability is available for immediate licensing from ARM. 45-day evaluations are available through the Program members in concert with their respective integrated solutions through the PV Enablement Program.
Members of the Program are able to integrate fully validated Fast Models from ARM, for a range of ARM processors, into their virtual platform environments and deliver to their customers.
This ensures that mutual customers can create complete ARM Powered virtual platforms using the design flow of their choice. By using virtual platforms built around ARM processor Fast Models, engineers can develop software well in advance of final hardware implementation, with application and driver software running at near to real-time system performance.
The Fast Models product family from ARM includes programmer's view (PV) models for the ARM9, ARM11 and Cortex families of processors, including the Cortex-A9 MPCore multicore processor. The Fast Model products also include configuration tools that enable the export of ARM processor-based subsystems with OSCI SystemC and TLM-2.0 compliant interfaces.
"We are seeing a growing demand for high-performance models in the industry," said John Cornish, EVP and general manager, System Design Division, ARM. "The TLM-2.0 interface enables our customers to combine our processor Fast Models with models of their other IP to create complete virtual platforms in the design environment of their choice."
"CoWare has successfully delivered Electronic System Virtualization solutions for ARM processor-based designs for many years supporting architecture design, verification, software development, integration and test. With our further engagement in this broader program covering the ARM Cortex Fast Models, we continue to expand this position to serve the growing needs of our joint customers," said Marc Serughetti, vice president of Marketing and Business Development at CoWare Inc.
"This integration and partnership is already proven and in use at several customers resulting in significant time-to-market benefits for those customers."
"Mentor’s Vista technology offers a comprehensive architecture design and prototyping solution that relies on fast processor and peripheral models as an essential part of the solution. The integration of the architecturally accurate ARM Fast Models into our Vista Platform will deliver significant value to our mutual customers," said Simon Bloch, Mentor Graphics vice president and general manager, design and synthesis division.
"In addition, ARM’s Fast Models are compatible with Vista’s TLM scalable modeling methodology that provides the timing and power layers essential for optimizing performance and power at the transaction level of abstraction."
"As a leading IP provider, Synopsys already provides OSCI TLM-2.0 compliant transaction-level models for several processor families including ARM and Synopsys DesignWare Cores and components for SoC infrastructure, AMBA interconnect, CoreConnect and PrimeCell peripherals in the Synopsys DesignWare System-level Library," said Frank Schirrmeister, director product marketing for the Solutions Group at Synopsys.
"The ARM PV Enablement Program allows our users to draw from a larger number of models and enables Synopsys to validate interoperability of Synopsys’ Innovator development environment for virtual platforms with ARM processor-based subsystems using Fast Models from ARM."
Availability
Fast Models Version 5.0 including the SystemC/TLM-2.0 compatible export capability is available for immediate licensing from ARM. 45-day evaluations are available through the Program members in concert with their respective integrated solutions through the PV Enablement Program.
Sunday, July 26, 2009
Synopsys intros Galaxy Constraint Analyzer
MOUNTAIN VIEW, USA: Synopsys Inc. has introduced Galaxy Constraint Analyzer, a new tool which improves designer productivity through look-ahead constraint analysis technology tuned for the Synopsys Galaxy Implementation Platform.
The Galaxy Constraint Analyzer is an intuitive tool that enables designers to quickly assess the correctness and consistency of timing constraints.
Correctness and consistency lead to more efficient runtimes in Synopsys' Design Compiler synthesis and IC Compiler physical implementation tools.
The Galaxy Constraint Analyzer features unique constraint debug capabilities to help designers eliminate long "trial-and-error iterations" during implementation, reducing design cost as a result of more predictable schedules all the way to full-chip signoff.
"Our complex SoC designs have a large number of clocks that require an intricate set of timing constraint definitions," said Hitoshi Sugihara, department manager of the DFM & Digital EDA Technology Development Dept., Design Technology Div., Renesas Technology.
"Making sure that our design engineers start with and hand-off a high-quality set of constraint files significantly lowers risk to our design schedules. Using the Galaxy Constraint Analyzer enabled us to find constraint issues that we could not have found otherwise, saving us significant time and effort. We plan to incorporate the Galaxy Constraint Analyzer into our standard design flow that includes Design Compiler and IC Compiler."
The rapid increase in design size and complexity, as well as the widespread reuse of intellectual property (IP) design blocks, has lead to a major increase in the size and complexity of timing constraint specification files.
Ensuring high-quality timing constraints is paramount to efficient design implementation, especially during handoffs between teams. Incomplete, inconsistent or conflicting constraints can cause optimization and implementation tools to run ineffectively or to never converge.
To address this challenge, the Galaxy Constraint Analyzer tool provides an extensive set of rule checks designed to maximize the efficiency of Design Compiler synthesis and IC Compiler physical implementation.
In addition, Galaxy Constraint Analyzer uses technology based on Synopsys' golden PrimeTime timing engine to ensure correct interpretation and propagation of constraints. This gives designers a signoff-correlated view of the constraints ahead of each step of the design implementation process.
Galaxy Constraint Analyzer's ability to deliver comprehensive constraint analysis on 10-million-gate designs in a matter of minutes, combined with a unique set of interactive analysis and debug capabilities, helps designers quickly identify and fix constraint issues within hours versus days.
"Constraint analysis is becoming a crucial step to ensure an efficient design implementation process," said Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys.
"However, in order for a constraint analysis tool to be effective, it has to interpret and analyze constraint specifications in a manner that is consistent and correlated with signoff. We built the Galaxy Constraint Analyzer using technology based on the PrimeTime golden timing engine to help designers produce the highest quality constraints for the Galaxy Implementation Platform."
The Galaxy Constraint Analyzer is an intuitive tool that enables designers to quickly assess the correctness and consistency of timing constraints.
Correctness and consistency lead to more efficient runtimes in Synopsys' Design Compiler synthesis and IC Compiler physical implementation tools.
The Galaxy Constraint Analyzer features unique constraint debug capabilities to help designers eliminate long "trial-and-error iterations" during implementation, reducing design cost as a result of more predictable schedules all the way to full-chip signoff.
"Our complex SoC designs have a large number of clocks that require an intricate set of timing constraint definitions," said Hitoshi Sugihara, department manager of the DFM & Digital EDA Technology Development Dept., Design Technology Div., Renesas Technology.
"Making sure that our design engineers start with and hand-off a high-quality set of constraint files significantly lowers risk to our design schedules. Using the Galaxy Constraint Analyzer enabled us to find constraint issues that we could not have found otherwise, saving us significant time and effort. We plan to incorporate the Galaxy Constraint Analyzer into our standard design flow that includes Design Compiler and IC Compiler."
The rapid increase in design size and complexity, as well as the widespread reuse of intellectual property (IP) design blocks, has lead to a major increase in the size and complexity of timing constraint specification files.
Ensuring high-quality timing constraints is paramount to efficient design implementation, especially during handoffs between teams. Incomplete, inconsistent or conflicting constraints can cause optimization and implementation tools to run ineffectively or to never converge.
To address this challenge, the Galaxy Constraint Analyzer tool provides an extensive set of rule checks designed to maximize the efficiency of Design Compiler synthesis and IC Compiler physical implementation.
In addition, Galaxy Constraint Analyzer uses technology based on Synopsys' golden PrimeTime timing engine to ensure correct interpretation and propagation of constraints. This gives designers a signoff-correlated view of the constraints ahead of each step of the design implementation process.
Galaxy Constraint Analyzer's ability to deliver comprehensive constraint analysis on 10-million-gate designs in a matter of minutes, combined with a unique set of interactive analysis and debug capabilities, helps designers quickly identify and fix constraint issues within hours versus days.
"Constraint analysis is becoming a crucial step to ensure an efficient design implementation process," said Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys.
"However, in order for a constraint analysis tool to be effective, it has to interpret and analyze constraint specifications in a manner that is consistent and correlated with signoff. We built the Galaxy Constraint Analyzer using technology based on the PrimeTime golden timing engine to help designers produce the highest quality constraints for the Galaxy Implementation Platform."
TSMC, Synopsys ally on interoperable unified physical verification formats
MOUNTAIN VIEW, USA: Synopsys Inc. announced that its recently launched IC Validator DRC/LVS product now fully supports interoperable Design Rule Checking (iDRC) and Layout-Versus-Schematic (iLVS), the new TSMC unified physical verification formats.
Synopsys was one of the first EDA suppliers to collaborate with TSMC to create and develop the unified formats, transitioning from a vendor-specific to an interoperable specification of technology files, which not only enables consistent interpretation across all tools, but also assures timely access to all Synopsys customers.
"Working with advanced node customers, TSMC and Synopsys concluded that a unified specification for Physical Verification tools was key to accelerating time to market, a primary benefit of TSMC's Open Innovation Platform," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.
"We benefited from the close cooperation with Synopsys, using IC Validator as the development and validation platform and a catalyst for the timely introduction of these formats."
IC Validator was used from early on as one of the reference platforms for prototype development and final qualification of the unified formats. Architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use, IC Validator provides a step up in physical designer productivity.
IC Validator delivers speed-up through multicore processors by efficiently parsing iDRC/iLVS generic rules into atomic instructions suitable for highly distributed execution.
In addition, with its advanced and near linear scalar hybrid signoff engine, IC Validator provides an efficient platform for coding and validating complex polygon and edge based rules needed for emerging process nodes.
As part of the Galaxy Implementation Platform, IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tape-out and improve manufacturability by performing physical verification within the implementation flow.
It is production-ready and has been successfully used for tape-outs at leading fabless customers and chip manufacturers. Synopsys will showcase iDRC- and iLVS-enabled flows with IC Validator at the 46th Design Automation Conference in San Francisco, California.
"By eliminating qualification and consistency barriers and assuring timely access to technology files, this close collaboration between TSMC and Synopsys, with participation from other EDA vendors, clears the way for designers to easily select amongst available physical verification tools," said Bijan Kiani, vice president of product marketing, design and manufacturing products at Synopsys.
"This puts Synopsys in a strong position to efficiently bring In-Design physical verification to our common customers."
Synopsys was one of the first EDA suppliers to collaborate with TSMC to create and develop the unified formats, transitioning from a vendor-specific to an interoperable specification of technology files, which not only enables consistent interpretation across all tools, but also assures timely access to all Synopsys customers.
"Working with advanced node customers, TSMC and Synopsys concluded that a unified specification for Physical Verification tools was key to accelerating time to market, a primary benefit of TSMC's Open Innovation Platform," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.
"We benefited from the close cooperation with Synopsys, using IC Validator as the development and validation platform and a catalyst for the timely introduction of these formats."
IC Validator was used from early on as one of the reference platforms for prototype development and final qualification of the unified formats. Architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use, IC Validator provides a step up in physical designer productivity.
IC Validator delivers speed-up through multicore processors by efficiently parsing iDRC/iLVS generic rules into atomic instructions suitable for highly distributed execution.
In addition, with its advanced and near linear scalar hybrid signoff engine, IC Validator provides an efficient platform for coding and validating complex polygon and edge based rules needed for emerging process nodes.
As part of the Galaxy Implementation Platform, IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tape-out and improve manufacturability by performing physical verification within the implementation flow.
It is production-ready and has been successfully used for tape-outs at leading fabless customers and chip manufacturers. Synopsys will showcase iDRC- and iLVS-enabled flows with IC Validator at the 46th Design Automation Conference in San Francisco, California.
"By eliminating qualification and consistency barriers and assuring timely access to technology files, this close collaboration between TSMC and Synopsys, with participation from other EDA vendors, clears the way for designers to easily select amongst available physical verification tools," said Bijan Kiani, vice president of product marketing, design and manufacturing products at Synopsys.
"This puts Synopsys in a strong position to efficiently bring In-Design physical verification to our common customers."
Friday, July 24, 2009
Synopsys Galaxy supports TSMC 28nm with Reference Flow 10.0
MOUNTAIN VIEW, USA: Synopsys Inc. announced that the Galaxy Implementation Platform supports TSMC's 28-nanometer process technology with Reference Flow 10.0.
Galaxy technologies featured in Reference Flow 10.0 include comprehensive 28-nm design rule support for place and route, interconnect process modeling and in-design manufacturing compliance, IEEE 1801-2009 (UPF)-based hierarchical low power flow support, power-aware design-for-test (DFT), electrical design-for-manufacturing (eDFM) enhancements and advanced signoff capabilities.
"TSMC and Synopsys have successfully collaborated to deliver 10 generations of the TSMC Reference Flow," said ST Juang, senior director of Design Infrastructure Marketing at TSMC. "The combination of Synopsys Galaxy technology and our 28-nanometer process technology in Reference Flow 10.0 provides designers a solution that addresses manufacturability while balancing the design for optimal performance and power consumption."
Synopsys' Galaxy Implementation Platform provides support for TSMC 28-nanometer design rules with IC Compiler place and route, IC Validator physical verification and Star-RCXT parasitic extraction.
As a key component of Synopsys' Eclypse Low Power Solution, the Galaxy Platform includes new hierarchical low power flow support with IEEE 1801, disjoint voltage area support, new power-aware technology for Design Compiler DFT synthesis and TetraMAX automatic test pattern generation (ATPG).
"The enhanced capabilities of our Galaxy Implementation Platform to support TSMC 28-nm design rules enable the design community to more easily benefit from TSMC's latest process technology," said Bijan Kiani, vice president of Product Marketing, Design and Manufacturing Products, at Synopsys.
"The release of Reference Flow 10.0 combines industry-leading EDA solutions from Synopsys and state-of-the-art manufacturing technology from TSMC to offer designers a low-risk path from design to silicon for their next-generation products."
Additional Galaxy technologies integrated into Reference Flow 10.0 provide comprehensive flow support for TSMC's eDFM timing analysis initiative. eDFM addresses potential parametric performance shifts due to manufacturing process variation in feature thickness, shape and stress.
These technologies include Seismos stress effect analysis and characterization, PrimeYield CMP modeling with TSMC's CMP simulator (VCMP), Star-RCXT feature-scale VCMP-aware extraction, PrimeTime VCMP-aware timing analysis, and PrimeRail VCMP-aware IR/EM analysis.
Galaxy technologies featured in Reference Flow 10.0 include comprehensive 28-nm design rule support for place and route, interconnect process modeling and in-design manufacturing compliance, IEEE 1801-2009 (UPF)-based hierarchical low power flow support, power-aware design-for-test (DFT), electrical design-for-manufacturing (eDFM) enhancements and advanced signoff capabilities.
"TSMC and Synopsys have successfully collaborated to deliver 10 generations of the TSMC Reference Flow," said ST Juang, senior director of Design Infrastructure Marketing at TSMC. "The combination of Synopsys Galaxy technology and our 28-nanometer process technology in Reference Flow 10.0 provides designers a solution that addresses manufacturability while balancing the design for optimal performance and power consumption."
Synopsys' Galaxy Implementation Platform provides support for TSMC 28-nanometer design rules with IC Compiler place and route, IC Validator physical verification and Star-RCXT parasitic extraction.
As a key component of Synopsys' Eclypse Low Power Solution, the Galaxy Platform includes new hierarchical low power flow support with IEEE 1801, disjoint voltage area support, new power-aware technology for Design Compiler DFT synthesis and TetraMAX automatic test pattern generation (ATPG).
"The enhanced capabilities of our Galaxy Implementation Platform to support TSMC 28-nm design rules enable the design community to more easily benefit from TSMC's latest process technology," said Bijan Kiani, vice president of Product Marketing, Design and Manufacturing Products, at Synopsys.
"The release of Reference Flow 10.0 combines industry-leading EDA solutions from Synopsys and state-of-the-art manufacturing technology from TSMC to offer designers a low-risk path from design to silicon for their next-generation products."
Additional Galaxy technologies integrated into Reference Flow 10.0 provide comprehensive flow support for TSMC's eDFM timing analysis initiative. eDFM addresses potential parametric performance shifts due to manufacturing process variation in feature thickness, shape and stress.
These technologies include Seismos stress effect analysis and characterization, PrimeYield CMP modeling with TSMC's CMP simulator (VCMP), Star-RCXT feature-scale VCMP-aware extraction, PrimeTime VCMP-aware timing analysis, and PrimeRail VCMP-aware IR/EM analysis.
Tuesday, July 21, 2009
Synopsys, TSMC develop iPDK and interoperable ecosystem
MOUNTAIN VIEW, USA: Synopsys Inc. today announced that Synopsys and TSMC have entered into a comprehensive multi-year agreement to jointly develop, validate, support and distribute interoperable process design kits (iPDKs) that are optimized for TSMC advanced semiconductor processes including the 65-nanometer (nm), 40-nm and 28-nm nodes.
The agreement is the culmination of a two-year collaboration to establish an interoperable PDK ecosystem that can accelerate and broaden designer access to new process nodes, promote design reuse and enable greater analog, mixed-signal and RF design innovation.
Additionally, TSMC has adopted Synopsys' Galaxy Custom Designer implementation solution as its iPDK development and validation platform.
"We are creating new business models and innovations such as iPDK under TSMC's Open Innovation Platform," said ST Juang, senior director of Design Infrastructure Marketing at TSMC.
"Synopsys has a highly skilled and dedicated team with expertise in developing advanced, high-quality interoperable PDKs, and offers the industry's most open custom design platform that supports iPDKs. This collaborative approach will help to more quickly deliver iPDKs to our mutual customers so that they can begin capitalizing on the benefits of an interoperable ecosystem."
Synopsys was lead developer in the collaborative effort to develop and validate a complete TSMC 65-nm iPDK. Working directly with the TSMC PDK development team and other EDA vendors, Synopsys developed an iPDK that supports the analog, mixed-signal and RF flow on multiple EDA vendor tools.
Synopsys and TSMC also collaborated on implementing a comprehensive iPDK development and validation solution based on Custom Designer. TSMC validated its recently-announced 65-nm iPDK to work with Synopsys' custom design solution, including Custom Designer, HSPICE circuit simulation, CustomSim circuit simulation, IC Validator/Hercules LVS/DRC and Star-RCXT extraction.
"Open standards are the catalyst for accelerating innovation, increasing competition and fostering growth in the electronics industry," said Paul Lo, senior vice president and general manager of the Analog/Mixed-Signal Group at Synopsys.
"Synopsys' open-environment custom design platform and interoperable PDK expertise, coupled with TSMC's comprehensive PDK production capability, has enabled us to move the industry forward to realize the benefits of an interoperable custom design ecosystem. This is a major step for the entire semiconductor industry."
The agreement is the culmination of a two-year collaboration to establish an interoperable PDK ecosystem that can accelerate and broaden designer access to new process nodes, promote design reuse and enable greater analog, mixed-signal and RF design innovation.
Additionally, TSMC has adopted Synopsys' Galaxy Custom Designer implementation solution as its iPDK development and validation platform.
"We are creating new business models and innovations such as iPDK under TSMC's Open Innovation Platform," said ST Juang, senior director of Design Infrastructure Marketing at TSMC.
"Synopsys has a highly skilled and dedicated team with expertise in developing advanced, high-quality interoperable PDKs, and offers the industry's most open custom design platform that supports iPDKs. This collaborative approach will help to more quickly deliver iPDKs to our mutual customers so that they can begin capitalizing on the benefits of an interoperable ecosystem."
Synopsys was lead developer in the collaborative effort to develop and validate a complete TSMC 65-nm iPDK. Working directly with the TSMC PDK development team and other EDA vendors, Synopsys developed an iPDK that supports the analog, mixed-signal and RF flow on multiple EDA vendor tools.
Synopsys and TSMC also collaborated on implementing a comprehensive iPDK development and validation solution based on Custom Designer. TSMC validated its recently-announced 65-nm iPDK to work with Synopsys' custom design solution, including Custom Designer, HSPICE circuit simulation, CustomSim circuit simulation, IC Validator/Hercules LVS/DRC and Star-RCXT extraction.
"Open standards are the catalyst for accelerating innovation, increasing competition and fostering growth in the electronics industry," said Paul Lo, senior vice president and general manager of the Analog/Mixed-Signal Group at Synopsys.
"Synopsys' open-environment custom design platform and interoperable PDK expertise, coupled with TSMC's comprehensive PDK production capability, has enabled us to move the industry forward to realize the benefits of an interoperable custom design ecosystem. This is a major step for the entire semiconductor industry."
Synopsys' DesignWare IP slashes power in datapath circuits
MOUNTAIN VIEW, USA: Synopsys Inc. announced the DesignWare minPower Components, a new IP product that is an integral part of the Synopsys Eclypse Low Power Solution.
The DesignWare minPower Components dramatically reduce power in datapath logic compared to traditional power optimization methods. By using the DesignWare minPower Components, leading wireless, networking and DSP companies achieved power reduction of up to 48 percent in datapath logic.
"Optimizing the power consumption of datapath circuits in mobile applications can significantly extend battery life because these blocks are often on, even in standby mode," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "Our customers have achieved an additional 7 to 48 percent reduction in power for these circuits."
"As the high speed networking market evolves to support another 10X increase in data rates, power dissipation has become an important issue in the adoption of next-generation technologies," said Jag Bolaria, senior analyst at The Linley Group.
"To be competitive, chip manufacturers need to optimize power dissipation in the datapath. Synopsys' DesignWare minPower Components include innovative techniques that address this problem - enabling designers to further reduce power consumption at advanced data rates."
Today's conventional techniques do not address reducing specific power elements such as glitch power in deep logic levels and dynamic power in high-performance datapath pipelines.
The DesignWare minPower Components offer unique, power-optimized datapath architectures that enable the DC Ultra synthesis tool to automatically generate circuits that suppress switching activity and glitches, reducing both dynamic and leakage power for mobile devices and high-performance applications.
Based on the actual switching activities, transition probabilities, available standard cells and analysis of possible configurations, the DesignWare minPower Components architectures are automatically configured by DC Ultra to implement the optimal structure with the lowest power consumption.
In addition to the automatically inferable components, the DesignWare minPower Components also include more than 40 instantiable components that incorporate low power design techniques such as enhanced clock gating, built-in datapath gating and patented data-tracking pipeline management technology to reduce power consumption.
The DesignWare minPower Components are tightly integrated with the Synopsys Galaxy Implementation Platform, which enables significant optimization of a design's total power compared to existing flows. The unique architectures in the DesignWare minPower Components allow high-level datapath structures to be automatically optimized based on power costing and switching activities.
Applications with datapath circuits that have a high percentage of active time, such as wireless receivers, audio/video processors, CPUs, media processors, and signal processing blocks for high-performance networking and storage, are ideal candidates for the DesignWare minPower Components.
The DesignWare minPower Components dramatically reduce power in datapath logic compared to traditional power optimization methods. By using the DesignWare minPower Components, leading wireless, networking and DSP companies achieved power reduction of up to 48 percent in datapath logic.
"Optimizing the power consumption of datapath circuits in mobile applications can significantly extend battery life because these blocks are often on, even in standby mode," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "Our customers have achieved an additional 7 to 48 percent reduction in power for these circuits."
"As the high speed networking market evolves to support another 10X increase in data rates, power dissipation has become an important issue in the adoption of next-generation technologies," said Jag Bolaria, senior analyst at The Linley Group.
"To be competitive, chip manufacturers need to optimize power dissipation in the datapath. Synopsys' DesignWare minPower Components include innovative techniques that address this problem - enabling designers to further reduce power consumption at advanced data rates."
Today's conventional techniques do not address reducing specific power elements such as glitch power in deep logic levels and dynamic power in high-performance datapath pipelines.
The DesignWare minPower Components offer unique, power-optimized datapath architectures that enable the DC Ultra synthesis tool to automatically generate circuits that suppress switching activity and glitches, reducing both dynamic and leakage power for mobile devices and high-performance applications.
Based on the actual switching activities, transition probabilities, available standard cells and analysis of possible configurations, the DesignWare minPower Components architectures are automatically configured by DC Ultra to implement the optimal structure with the lowest power consumption.
In addition to the automatically inferable components, the DesignWare minPower Components also include more than 40 instantiable components that incorporate low power design techniques such as enhanced clock gating, built-in datapath gating and patented data-tracking pipeline management technology to reduce power consumption.
The DesignWare minPower Components are tightly integrated with the Synopsys Galaxy Implementation Platform, which enables significant optimization of a design's total power compared to existing flows. The unique architectures in the DesignWare minPower Components allow high-level datapath structures to be automatically optimized based on power costing and switching activities.
Applications with datapath circuits that have a high percentage of active time, such as wireless receivers, audio/video processors, CPUs, media processors, and signal processing blocks for high-performance networking and storage, are ideal candidates for the DesignWare minPower Components.
Monday, July 20, 2009
Synopsys intros IC Compiler In-Design Rail Analysis
MOUNTAIN VIEW, USA: Synopsys Inc. today introduced its In-Design Rail Analysis capability to accelerate design closure.
Part of Synopsys' IC Compiler in-design ecosystem, In-Design Rail Analysis utilizes embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation.
By identifying and fixing voltage-drop and electromigration issues earlier in the flow, designers can eliminate costly iterations late in the design process.
Working in concert with IC Compiler's Power Network Synthesis (PNS) and In-Design Physical Verification capabilities, In-Design Rail Analysis provides designers with a comprehensive solution for both the implementation and verification of power networks.
"Performing rail analysis and fixing within the IC Compiler place-and-route environment will greatly improve our designers' productivity, a significant benefit of Synopsys' Galaxy Implementation Platform," said Hitoshi Sugihara, Department Manager of DFM & Digital EDA Technology Development Department at Renesas Technology Corp.
"We worked with Synopsys early in the development of this technology to ensure that it is easy to use, and have confirmed PrimeRail accuracy and correlation with HSPICE and silicon. We plan to standardize on a design methodology that takes advantage of In-Design Rail Analysis."
Traditional approaches to power network design consist of separate implementation and verification steps, often performed by different engineers using many tools and environments in a complex flow.
With leading-edge system-on-chip (SoC) designs, this approach often results in multiple iterations between physical implementation and signoff, adding significant risk to project schedules. By eliminating complicated data exchanges and with no new tools to learn, In-Design Rail Analysis helps IC Compiler users ensure the integrity of their power network early and frequently during the physical implementation process, avoiding late-stage surprises close to tapeout.
In-Design Rail Analysis works in tandem with IC Compiler's PNS capability to enable designers to efficiently implement, optimize and refine power networks, significantly reducing overdesign. In addition, In-Design Physical Verification helps ensure that power networks are design-rule clean as refinements and fixes are implemented.
IC Compiler's ecosystem of PNS, In-Design Rail Analysis and In-Design Physical Verification today offers a fast and comprehensive solution for power network design.
"The charter of our IC Compiler in-design ecosystem is to bring advanced analysis and verification capabilities into the hands of place-and-route engineers," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group.
"Complementing our recent introduction of In-Design Physical Verification with IC Validator, In-Design Rail Analysis is the latest innovation aimed at significantly reducing design iterations which can seriously impact time-to-tapeout."
Part of Synopsys' IC Compiler in-design ecosystem, In-Design Rail Analysis utilizes embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation.
By identifying and fixing voltage-drop and electromigration issues earlier in the flow, designers can eliminate costly iterations late in the design process.
Working in concert with IC Compiler's Power Network Synthesis (PNS) and In-Design Physical Verification capabilities, In-Design Rail Analysis provides designers with a comprehensive solution for both the implementation and verification of power networks.
"Performing rail analysis and fixing within the IC Compiler place-and-route environment will greatly improve our designers' productivity, a significant benefit of Synopsys' Galaxy Implementation Platform," said Hitoshi Sugihara, Department Manager of DFM & Digital EDA Technology Development Department at Renesas Technology Corp.
"We worked with Synopsys early in the development of this technology to ensure that it is easy to use, and have confirmed PrimeRail accuracy and correlation with HSPICE and silicon. We plan to standardize on a design methodology that takes advantage of In-Design Rail Analysis."
Traditional approaches to power network design consist of separate implementation and verification steps, often performed by different engineers using many tools and environments in a complex flow.
With leading-edge system-on-chip (SoC) designs, this approach often results in multiple iterations between physical implementation and signoff, adding significant risk to project schedules. By eliminating complicated data exchanges and with no new tools to learn, In-Design Rail Analysis helps IC Compiler users ensure the integrity of their power network early and frequently during the physical implementation process, avoiding late-stage surprises close to tapeout.
In-Design Rail Analysis works in tandem with IC Compiler's PNS capability to enable designers to efficiently implement, optimize and refine power networks, significantly reducing overdesign. In addition, In-Design Physical Verification helps ensure that power networks are design-rule clean as refinements and fixes are implemented.
IC Compiler's ecosystem of PNS, In-Design Rail Analysis and In-Design Physical Verification today offers a fast and comprehensive solution for power network design.
"The charter of our IC Compiler in-design ecosystem is to bring advanced analysis and verification capabilities into the hands of place-and-route engineers," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group.
"Complementing our recent introduction of In-Design Physical Verification with IC Validator, In-Design Rail Analysis is the latest innovation aimed at significantly reducing design iterations which can seriously impact time-to-tapeout."
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