Fuji Electric Device achieves significant cost reduction with Cadence Virtuoso accelerated parallel simulator

SAN JOSE, USA: Cadence Design Systems Inc. announced that Fuji Electric Device Technology Co. Ltd. cut development costs by about a third by using the Cadence Virtuoso Accelerated Parallel Simulator.

The company, a leader in power management ICs, credited the simulator with helping design teams boost the quality of their chips, and get them to market faster.

Fuji Electric Device Technology develops high-voltage and high-efficiency AC/DC IC for green IDC power management, communication and automotive markets. To verify a full-chip power system, a simulation technology with high performance and full SPICE accuracy was required.

“The Virtuoso Accelerated Parallel Simulator enabled our design teams to reduce the number of prototyping iterations, leading to a 30 percent reduction in our development costs,” said Takashi Kobayashi, general manager, Semiconductor Device R&D Dept., Electron Device Laboratory, Semiconductors Group, Fuji Electric Device Technology Co. Ltd.

“Using the Accelerated Parallel Simulator, we have reduced simulation time up to 75 percent for our full-chip designs without sacrificing any accuracy. As a result we are able to deliver high-quality devices and meet the market window.”

“We’re glad to see Fuji Electric Device Technology place its logo alongside the many other leading technology companies who have discovered the capabilities and benefits of the Virtuoso Accelerated Parallel Simulator for small to large pre layout and post layout designs,” said Zhihong Lui, corporate vice president at Cadence.

“The company’s experience of quality improvements and faster time to market is wholly consistent with what we’ve been hearing from other companies as well.”

Part of the Virtuoso Multi-mode Simulation, the Virtuoso Accelerated Parallel Simulator provides the next generation SPICE accurate simulation, with scalable performance and capacity, for a broad class of complex analog, RF and mixed-signal blocks and sub-systems with ten thousands of devices.

It is tightly integrated with the Virtuoso custom design platform and provides all the transistor-level analysis capabilities as in Virtuoso Spectre Simulator. The proprietary full matrix-solving algorithm delivers unparalleled scalable multi-threading capability using modern multi-core machines.

Duolog announces distributor agreement with Innotech

SAN JOSE, USA: Duolog Technologies Ltd, the leading provider of SoC integration and automation tools, has entered into a distributor agreement with Innotech Corp. for exclusive distribution of Duolog products in Japan.

The formation of a distributor agreement with Innotech will enable Duolog to meet the increasing demand for its SoC integration and automation tools in the Japanese market. Innotech will also help to accelerate Duolog’s access to new markets such as digital consumer electronics, musical instrumentation and automotive. Based on the agreement with Duolog, Innotech will provide a dedicated Duolog team, including both sales representatives and Field Applications Engineers (FAEs).

Duolog will leverage Innotech's extensive experience in the distribution and support of EDA tools in the Japanese market.

“Innotech has a strong reputation and customer base, as well as a proven track record of selling and providing technical support for leading-edge EDA tools from companies such as Cadence Design Systems. We fully expect that this agreement will lead to additional Duolog customers in Japan and will help us to diversify into new market areas,” said Ray Bulger, CEO of Duolog.

Innotech General Manager and Director of IC Solutions, Takashi Takahashi, added: "We selected Duolog Technologies as our partner as Duolog has strong expertise in developing robust products to enable the rapid realisation of SoC, MCU and FPGA designs. Duolog’s products enhance an important part of the design flow for Japanese semiconductor and system companies.

"We would like Japanese customers to adopt and use these integration and automation products in their designs to take full advantage of the many benefits they bring such as greatly improved productivity and communication."

Ubixum achieves product-ready design at First Silicon with Synopsys Galaxy Custom Designer solution

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Ubixum has used Synopsys' Galaxy Custom Designer implementation solution to successfully design its latest advanced image sensor chip.

The chip has been verified to be product-ready with first silicon. Custom Designer is a modern-era custom implementation solution that delivers superior ease-of-use and leverages Synopsys' Galaxy Implementation Platform to provide a unified solution for custom and digital designs. The Custom Designer tool set enabled Ubixum to achieve higher productivity and better integration with their optimized design process.

"Synopsys' comprehensive custom implementation and simulation solutions, methodologies and support played a critical role in helping us to achieve first-silicon success," said Keith Fife, cofounder of Ubixum.

"The use of Custom Designer running natively on the OpenAccess database allowed us to easily integrate our own tools and to access the design through our own API. Custom Designer can handle very large designs with many complex polygon shapes found in our custom devices. Its ability to properly handle and display large arrays has been important to our productivity. We have already started to use Custom Designer for our next product."

Ubixum turned to Custom Designer for its modern architecture and completeness that delivers productivity with a familiar user interface while integrating a common use model for simulation, analysis, parasitic extraction and physical verification.

Custom Designer is built natively on the OpenAccess database for legacy designs and offers unprecedented openness and interoperability with process design kits (PDKs) from leading foundries. Key modules include a schematic editor featuring on-canvas editing and dynamic net highlighting.

The simulation environment provides a common use model allowing access to Synopsys simulators, including the HSPICE, CustomSim and Custom WaveView simulators. In addition, the results from Hercules DRC/LVS and Star-RCXT parasitic extraction are dynamically available within Custom Designer.

"Galaxy Custom Designer continues to meet the demands of our customers as design challenges continue to increase. Ubixum's successful design underscores Synopsys' commitment to deliver solutions that address our customers' design challenges and meet their productivity needs," said Bijan Kiani, vice president of Product Marketing for Design and Manufacturing Tools at Synopsys.

"We congratulate Ubixum on their first-pass silicon success, and we plan to continue working closely with them for the mutual benefit of both companies by extending the advanced design capabilities of Galaxy Custom Designer."

Magma customers pass 50-tapeout mark at 45/40nm using Talus

BANGALORE, INDIA: Magma Design Automation Inc. today announced Magma customers have passed the 50-tapeout mark for chips designed at 45 nanometer (nm) or smaller geometries using Magma’s Talus netlist-to-GDSII design implementation system –- more than with any other EDA supplier’s implementation system.

Talus, Magma’s next-generation implementation platform designed specifically for chips at 45-/40-nm or smaller process nodes, is now widely used among Magma customers and its latest release, Talus 1.1, has demonstrated particular advantages for designs at the 45-/40-nm process nodes.

More than 55 percent of the 45- and 40-nm tapeouts were completed for networking and mobile applications. Other applications taking advantage of 45- and 40-nm technology include multimedia and graphics.

In terms of geographic distribution, about 70 percent of the 45- and 40-nm tapeouts completed to date were by companies based in North America and about 25 percent by companies based in Japan or the Asia-Pacific region.

“As you might expect, networking and mobile applications represent the bulk of chips completed at 45 or 40 nm,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit.

“The designs completed so far at these geometries tend to be complex, in some cases approaching 100 million gates. Talus 1.1 with its COre™ (concurrent optimizing routing engine) and high capacity is ideally suited for implementing chips in these application areas which tend to push the performance envelope as well as have high gate counts.”

Talus 1.1: Fastest path to silicon for 45-/40-nm chips
The Talus system was built to anticipate the unique requirements of chip design at advanced process nodes, and Talus 1.1 takes its capabilities even further. Since its availability was announced in May 2009, Magma customers have found Talus 1.1 to deliver significant improvements in runtime and timing convergence.

It also achieves timing closure with no design-rule checking (DRC) violations and reduces total chip area significantly. Talus also offers a significant capacity advantage over competing systems which allows design teams to work on much larger blocks during the design process.

“Magma’s raison d’etre from our beginning has been to provide designers with the best technology for advanced chips,” Buch added. “That’s why we closely track how many chips are taped out as the semiconductor community transitions to new process geometries.

“The transition to the 45-/40-nm nodes has again created an opportunity for Magma to expand market share. Of course, we are not stopping there and already have the foundation in place to support the next process node at 32/28nm. In fact, we are already seeing some of our customers working on 28-nm designs.”

Mentor Graphics reports strong bookings in Q2

WILSONVILLE, USA: Mentor Graphics Corp. recently announced results for the fiscal second quarter 2010, ending July 31, 2009. For the quarter, the company reported revenues of $182.6 million, non-GAAP earnings per share of $.02, and a GAAP loss per share of $.22. Bookings for the quarter rose 15 percent over the prior fiscal second quarter.

“The quarter’s strong bookings performance was driven by new customers and new products. Though the business climate is still difficult, we did see strong sequential increases in consulting and distributor bookings during the quarter, both signs we take as indicators of an improving customer environment,” said Walden C. Rhines, CEO and chairman of Mentor Graphics.

“The company continues to build its strength in new markets, expanding its electronic system level design (ESL) and low-power product offerings during the quarter. Taiwan Semiconductor Manufacturing Co.'s (TSMC) inclusion of a full Mentor low-power implementation flow in their Reference Flow 10.0 further strengthens the company’s position in the physical implementation market.”

During the quarter, Mentor released a new version of its Catapult C synthesis tool enabling full chip synthesis, including control logic, and better power management. The company also released its PADS 9.0 printed circuit board flow which incorporated new collaboration, manufacturing and analysis tools.

At the Design Automation Conference (DAC) in July, Mentor advanced its full system low-power strategy by launching its VistaTM platform which enables engineers to model power early in the design cycle. Also at DAC, Mentor and its partners detailed the company’s multi-operating system, multi-core embedded system strategy featuring Linux, Android, and Nucleus operating systems.

Last Tuesday, the company closed its acquisition of LogicVision announced during the second quarter. The acquisition strengthens the company’s market-leading position in the design-for-test market by combining LogicVision’s strength in built-in-self-test (BIST) with the company’s strength in automated test pattern generation (ATPG) and embedded test pattern compression technology.

“With a tight rein on costs and the beginnings of an improving economic climate, the company performed better than we were confident to predict,” said Gregory K. Hinckley, president of Mentor Graphics. “The contract renewals we had in the quarter were at similar levels to their previous contract values, which was an improvement from the first quarter’s renewal rates. And despite acquisitions, headcount and operating expenses are down from a year ago, as the company continued to attack costs like travel, facilities and outside services.”

Outlook
For the third quarter fiscal 2010, the company expects revenue of about $183 million, non-GAAP earnings per share of about $.01 and a GAAP loss per share of about $.19.

University of Southampton receives Charles Babbage Grant from Synopsys

MOUNTAIN VIEW, USA: Synopsys Inc. today announced that the School of Electronics and Computer Science (ECS) at the University of Southampton is the first Western European university to receive the Charles Babbage Grant from Synopsys.

Through the grant, ECS receives licenses of Synopsys' comprehensive electronic design automation (EDA) software and intellectual property. The grant also enabled the University to set up a brand new laboratory for virtual learning.

The Virtual Learning Environment focuses on integrated circuit design and also involves a new range of courses on advanced system-on-chip (SoC) design, with support and faculty training from Synopsys. The grant has enabled ECS to install new computer hardware in the virtual learning laboratory to support up to 20 students.

Synopsys software provides students and researchers the opportunity to utilize industrial tools for logic and physical synthesis, circuit simulation, nanometer device modeling and fabrication process modeling. Synopsys software serves as the foundation for an industry design flow where students get real-world, hands-on experience building and testing their designs.

"The School of Electronics and Computer Science is the largest of its kind in the UK with a long tradition of research in electronic engineering and computer science. This grant enables us to continue that tradition with the latest leading-edge commercial tools," said Dr. Matt Swabey, electronics teaching fellow at ECS.

"We can now give our students real quantitative experience in modeling SoCs, enabling them to modify and try out designs to achieve defined goals. This ability will be enormously valuable to our students."

Access to industrial design tools for advanced research and microelectronic design is a common challenge facing universities today. Synopsys helps resolve this issue through initiatives like the Charles Babbage Grant and its Worldwide University Program, which provide select universities with design software for modern electronic design flows and leading IC fabrication processes.

Previous grant recipients in the USA include Case Western Reserve University, Purdue University and Syracuse University.

John Chilton, Senior Vice President of Marketing & Strategic Development at Synopsys, formally opened the lab during an August 17th ceremony at the University of Southampton attended by students and faculty.

"Synopsys selected the University of Southampton because of its global reputation for leading-edge research and its academic focus on engineering and computer science," commented Chilton. "Through this grant, Synopsys enables the University to further its reputation as a leading academic institution and to give its students access to the latest tools and equipment, supporting their educational experience and preparing them for future roles in industry, academia or government."

Synopsys announces financial results for Q3 2009

MOUNTAIN VIEW, USA: Synopsys Inc. today reported results for its third quarter ended July 31, 2009.

For the third quarter of fiscal 2009, Synopsys reported revenue of $345.2 million compared to $344.1 million for the third quarter of fiscal 2008.

"Synopsys again made excellent progress towards delivering on our year's objectives," said Aart de Geus, chairman and CEO of Synopsys. "We are actively working with customers to help them successfully navigate the economic recovery, and are positioning ourselves for even greater strength in the future."

GAAP results
On a generally accepted accounting principles (GAAP) basis, net income for the third quarter of fiscal 2009 was $47.4 million, or $0.32 per share, compared to $57.7 million, or $0.39 per share, for the third quarter of fiscal 2008, which included a $17.3 million tax benefit associated with the settlement of an IRS tax issue for fiscal years 2000 and 2001.

Non-GAAP results
On a non-GAAP basis, net income for the third quarter of fiscal 2009 was $68.3 million, or $0.47 per share, compared to non-GAAP net income of $64.5 million, or $0.44 per share, for the third quarter of fiscal 2008.

Financial targets
Synopsys also provided its financial targets for the fourth quarter and full fiscal year 2009. These targets constitute forward-looking information and are based on current expectations.

Fourth Quarter of Fiscal Year 2009 Targets:
Revenue: $335 million - $343 million
GAAP expenses: $297 million - $313 million
Non-GAAP expenses: $272 million - $282 million
Other income and expense: $0 - $3 million
Tax rate applied in non-GAAP net income calculations: approximately 26 percent
Fully diluted outstanding shares: 146 million - 149 million
GAAP earnings per share: $0.14 - $0.21
Non-GAAP earnings per share: $0.29 - $0.33
Revenue from backlog: greater than 90 percent

Full-Year Fiscal Year 2009 Targets:
Revenue: approximately $1.357 billion - $1.365 billion
Other income and expense: $11 million - $14 million
Tax rate applied in non-GAAP net income calculations: approximately 27 percent
Fully diluted outstanding shares: 144 million - 146.5 million
GAAP earnings per share: $1.16 - $1.23
Non-GAAP earnings per share: $1.71 - $1.75

Cash flow from operations: $190 million-$210 million (excludes potential impact of a tentative settlement with the Internal Revenue Service, described below).

In the second quarter, the company reached a tentative settlement with the IRS that would resolve a dispute regarding its 2002-2004 returns, primarily associated with the acquisition of Avant!.

The tentative settlement is subject to further approval by the government. If approved, we expect it to result in a cash payment to the IRS of approximately $50 million, most likely within the next 12 months. If the tentative settlement is approved, this payment would be fully offset by tax reductions in future years.

ASICSoft is Aldec's Northern California EDA tools distributor

SAN JOSE, USA: ASICSoft Inc. has partnered with Aldec as the northern California distributor for Aldec’s EDA tools. ASICSoft will play a major role with three key product lines: Active-HDL, Riviera-PRO, and ALINT.

“This partnership is a perfect match to ASICSoft’s multi-tiered service offering. Our intense focus into hardware engineering services and now EDA tools will make it even easier for us to reach our mission to partner with technical leaders to get their projects completed on time,” stated Mike Chandler, President and CEO of ASICSoft.

"ASICSoft has extensive relationships with engineering managers, a great reputation for customer service excellence, and the seasoned professionals necessary to meet the high demands of Silicon Valley EDA tool users.

"We are confident that ASICSoft will deliver the extraordinary level of customer satisfaction that has become Aldec’s reputation in the EDA marketplace," stated Keith McCann, Director of Aldec North American Sales.

Teradici chooses Synopsys as primary EDA partner

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Teradici Corp., a provider of groundbreaking PC-over-IP technology, has signed an expanded business agreement to establish Synopsys as its primary EDA partner.

As a result of the latest multi-year agreement, Teradici has consolidated on Synopsys' Galaxy Implementation and Discovery Verification Platforms for its implementation, verification and analog/mixed-signal flows, as well as extended their use of Synopsys DesignWare IP cores and consulting services.

"Over the past several years, we have built a successful relationship with Synopsys by utilizing their best-in-class design tools, interface IP and design services to mitigate our project risks and accelerate the delivery of our breakthrough technology to our customers," said Maher Fahmi, vice president of Silicon Engineering and co-founder, Teradici.

"As we grow our competencies in new areas such as analog design and simulation, we know we can continue to rely on the breadth and quality of Synopsys' technology and the outstanding support of its field and services teams."

"In today's challenging business climate, innovative chip developers like Teradici are looking for partners who will not only help them distinguish their products, but do so in a manner that makes them more efficient and productive across all their design flows," said John Chilton, senior vice president of marketing and strategic development at Synopsys.

"Our broadened relationship enables Teradici to take advantage of Synopsys' growing technology and services portfolio so they can focus on developing and delivering their unique network-delivered computing products to the marketplace."

As part of the new agreement, Teradici has expanded access to products, services and IP from Synopsys, including the Galaxy Implementation Platform's IC Compiler place-and-route technology, Design Compiler Ultra synthesis, Galaxy Custom Designer mixed-signal implementation, DFTMAX compression, TetraMAX automatic test pattern generation, PrimeTime SI signal integrity analysis, Star-RCXT parasitic extraction and Hercules physical verification; the Discovery Verification Platform's VCS, HSPICE, and HSIM simulators for analog and digital verification, and MVRC and MVSIM for low power verification; and DesignWare IP for USB 2.0 and Ethernet.

Synopsys intros Galaxy Constraint Analyzer

MOUNTAIN VIEW, USA: Synopsys Inc. has introduced Galaxy Constraint Analyzer, a new tool which improves designer productivity through look-ahead constraint analysis technology tuned for the Synopsys Galaxy Implementation Platform.

The Galaxy Constraint Analyzer is an intuitive tool that enables designers to quickly assess the correctness and consistency of timing constraints.

Correctness and consistency lead to more efficient runtimes in Synopsys' Design Compiler synthesis and IC Compiler physical implementation tools.

The Galaxy Constraint Analyzer features unique constraint debug capabilities to help designers eliminate long "trial-and-error iterations" during implementation, reducing design cost as a result of more predictable schedules all the way to full-chip signoff.

"Our complex SoC designs have a large number of clocks that require an intricate set of timing constraint definitions," said Hitoshi Sugihara, department manager of the DFM & Digital EDA Technology Development Dept., Design Technology Div., Renesas Technology.

"Making sure that our design engineers start with and hand-off a high-quality set of constraint files significantly lowers risk to our design schedules. Using the Galaxy Constraint Analyzer enabled us to find constraint issues that we could not have found otherwise, saving us significant time and effort. We plan to incorporate the Galaxy Constraint Analyzer into our standard design flow that includes Design Compiler and IC Compiler."

The rapid increase in design size and complexity, as well as the widespread reuse of intellectual property (IP) design blocks, has lead to a major increase in the size and complexity of timing constraint specification files.

Ensuring high-quality timing constraints is paramount to efficient design implementation, especially during handoffs between teams. Incomplete, inconsistent or conflicting constraints can cause optimization and implementation tools to run ineffectively or to never converge.

To address this challenge, the Galaxy Constraint Analyzer tool provides an extensive set of rule checks designed to maximize the efficiency of Design Compiler synthesis and IC Compiler physical implementation.

In addition, Galaxy Constraint Analyzer uses technology based on Synopsys' golden PrimeTime timing engine to ensure correct interpretation and propagation of constraints. This gives designers a signoff-correlated view of the constraints ahead of each step of the design implementation process.

Galaxy Constraint Analyzer's ability to deliver comprehensive constraint analysis on 10-million-gate designs in a matter of minutes, combined with a unique set of interactive analysis and debug capabilities, helps designers quickly identify and fix constraint issues within hours versus days.

"Constraint analysis is becoming a crucial step to ensure an efficient design implementation process," said Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys.

"However, in order for a constraint analysis tool to be effective, it has to interpret and analyze constraint specifications in a manner that is consistent and correlated with signoff. We built the Galaxy Constraint Analyzer using technology based on the PrimeTime golden timing engine to help designers produce the highest quality constraints for the Galaxy Implementation Platform."

TSMC, Synopsys ally on interoperable unified physical verification formats

MOUNTAIN VIEW, USA: Synopsys Inc. announced that its recently launched IC Validator DRC/LVS product now fully supports interoperable Design Rule Checking (iDRC) and Layout-Versus-Schematic (iLVS), the new TSMC unified physical verification formats.

Synopsys was one of the first EDA suppliers to collaborate with TSMC to create and develop the unified formats, transitioning from a vendor-specific to an interoperable specification of technology files, which not only enables consistent interpretation across all tools, but also assures timely access to all Synopsys customers.

"Working with advanced node customers, TSMC and Synopsys concluded that a unified specification for Physical Verification tools was key to accelerating time to market, a primary benefit of TSMC's Open Innovation Platform," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.

"We benefited from the close cooperation with Synopsys, using IC Validator as the development and validation platform and a catalyst for the timely introduction of these formats."

IC Validator was used from early on as one of the reference platforms for prototype development and final qualification of the unified formats. Architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use, IC Validator provides a step up in physical designer productivity.

IC Validator delivers speed-up through multicore processors by efficiently parsing iDRC/iLVS generic rules into atomic instructions suitable for highly distributed execution.

In addition, with its advanced and near linear scalar hybrid signoff engine, IC Validator provides an efficient platform for coding and validating complex polygon and edge based rules needed for emerging process nodes.

As part of the Galaxy Implementation Platform, IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tape-out and improve manufacturability by performing physical verification within the implementation flow.

It is production-ready and has been successfully used for tape-outs at leading fabless customers and chip manufacturers. Synopsys will showcase iDRC- and iLVS-enabled flows with IC Validator at the 46th Design Automation Conference in San Francisco, California.

"By eliminating qualification and consistency barriers and assuring timely access to technology files, this close collaboration between TSMC and Synopsys, with participation from other EDA vendors, clears the way for designers to easily select amongst available physical verification tools," said Bijan Kiani, vice president of product marketing, design and manufacturing products at Synopsys.

"This puts Synopsys in a strong position to efficiently bring In-Design physical verification to our common customers."

Synopsys intros IC Compiler In-Design Rail Analysis

MOUNTAIN VIEW, USA: Synopsys Inc. today introduced its In-Design Rail Analysis capability to accelerate design closure.

Part of Synopsys' IC Compiler in-design ecosystem, In-Design Rail Analysis utilizes embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation.

By identifying and fixing voltage-drop and electromigration issues earlier in the flow, designers can eliminate costly iterations late in the design process.

Working in concert with IC Compiler's Power Network Synthesis (PNS) and In-Design Physical Verification capabilities, In-Design Rail Analysis provides designers with a comprehensive solution for both the implementation and verification of power networks.

"Performing rail analysis and fixing within the IC Compiler place-and-route environment will greatly improve our designers' productivity, a significant benefit of Synopsys' Galaxy Implementation Platform," said Hitoshi Sugihara, Department Manager of DFM & Digital EDA Technology Development Department at Renesas Technology Corp.

"We worked with Synopsys early in the development of this technology to ensure that it is easy to use, and have confirmed PrimeRail accuracy and correlation with HSPICE and silicon. We plan to standardize on a design methodology that takes advantage of In-Design Rail Analysis."

Traditional approaches to power network design consist of separate implementation and verification steps, often performed by different engineers using many tools and environments in a complex flow.

With leading-edge system-on-chip (SoC) designs, this approach often results in multiple iterations between physical implementation and signoff, adding significant risk to project schedules. By eliminating complicated data exchanges and with no new tools to learn, In-Design Rail Analysis helps IC Compiler users ensure the integrity of their power network early and frequently during the physical implementation process, avoiding late-stage surprises close to tapeout.

In-Design Rail Analysis works in tandem with IC Compiler's PNS capability to enable designers to efficiently implement, optimize and refine power networks, significantly reducing overdesign. In addition, In-Design Physical Verification helps ensure that power networks are design-rule clean as refinements and fixes are implemented.

IC Compiler's ecosystem of PNS, In-Design Rail Analysis and In-Design Physical Verification today offers a fast and comprehensive solution for power network design.

"The charter of our IC Compiler in-design ecosystem is to bring advanced analysis and verification capabilities into the hands of place-and-route engineers," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group.

"Complementing our recent introduction of In-Design Physical Verification with IC Validator, In-Design Rail Analysis is the latest innovation aimed at significantly reducing design iterations which can seriously impact time-to-tapeout."

Cadence integrates chip planning with implementation!

Last month, Cadence Design Systems Inc. unveiled an integrated chip planning and implementation solution. This has been achieved through the integration of Cadence InCyte Chip Estimator and the Cadence Encounter Digital Implementation (EDI) System technologies.

Cadence has called this breakthrough solution, which provides design and implementation engineers with superior visibility and predictability of chip performance, area, power consumption, cost, and time to market across the full range of design activities, including system-level design and IP selection through final implementation and signoff.

I got into a brief conversation with Adam Traidman, Group Marketing Director, Cadence, Dave Desharnais, Product Marketing Group Director, Cadence, and Rahul Arya, Director, Marketing & Technology Sales, Cadence Design Systems India Pvt Ltd.

EDA industry revenue dips 10.7 percent in Q1-09
By the way, the EDA Consortium (EDAC) Market Statistics Service (MSS) today announced that the EDA industry revenue for Q1 2009 declined 10.7 percent to $1192.1 million, compared to $1334.2 million in Q1 2008, driven primarily by an accounting shift at one major EDA company. The four-quarter moving average declined 11.3 percent.

"The business environment remained difficult for EDA as for other industries, with Q1 EDA revenues declining in all regions except Asia Pacific," said Walden C. Rhines, EDA Consortium chair and Mentor Graphics CEO and chairman. "Nevertheless, for Q1, the overall decline was less than for the previous quarter."

Back to the current discussion then! It'd be interesting to see how all these tools bring the EDA industry back above the red level!

Why this solution?
The obvious question, why the Integrated Chip Planning and Implementation Solution now?

Adam Traidman said that the Chip Estimator is quite unique! It helps customers early in the IC design cycle.

"We go beyond EDA and estimate cost, etc. We help the designers to do an early architectural level ecomnomical and techical analysis and estimation, etc. Statistics show that during the early phases of design, those decisions can contribute to 80 percent of final design. Today, very few EDA companies provide set of tools and methodologies that allow such trade-off," he added.

According to him, every customer does this analysis, probably, manually. Cadence is now automating this method. In this respect, it has integrated chip planning with implementation.

"The results of the analysis -- you are concerned about accuracy; you look to the EDA vendors to help converge from initial implementation to the actual convergence. Think of it like a cockpit for the design engineer, general manager, program manager, etc.," he noted.

"You've made all the fundamental decisions, etc. If you're sitting on the physical implementation tool, and you need think through the implications that can be there. For example, to re-synthesize new libraries, etc. We are talking about chip planning at a much, much higher level," added Traidman.

Helping with IP selection!
The Cadence solution also leverages the vast ecosystem of IP at the ChipEstimate.com portal where over 200 IP suppliers and foundries contribute data. Helping with IP selection has been mentioned among the processes, perhaps, an indicator that designers may have not been able to select the right IPs all this while.

According to Traidman, IP selection and qiuality are key issues. "A lot of people, doing these tradeoffs, could be design managers, general manager, etc. When they sit with this tool, and when it pops up, they can see a huge library of 7,000 IPs from about 200 IP suppliers and foundries. Any design team can view all of the IPs as a free service," he elaborated. By the way, ChipEstimate is owned by Cadence!

He further added that the ChipEstimate portal allows customers to lower the risks of converging. The portal has been growing since 2006, and receives 1 million page view each month.

Just for interest's sake, there's another site -- Design And Reuse -- that claims to be the world's largest directory of 8,000 silicon IPs from more than 400 vendors! I have also got into some other discussions -- that are ongoing -- for developing a similar site in India, for the Indian semiconductor industry!

What about Cadence Encounter?
Post the integration, what happens now to the Cadence Encounter solution and whether it is still available standalone?

Dave Desharnais said the Cadence Encounter solution is still available standalone. "We have integrated some key functions from InCyte. From InCyte, you would normally not have the link to get into physical implementation. Likewise, with feeding back of a fully realized database," he said.

Last December (2008), Cadence had announced the Encounter Digital Implementation System, a next generation complete RTL-to-GDSII solution for logic and physical implementation.

Along with a fundamental new memory architecture and end-to-end multicore backplane to address the requirements of leapfrog capacity and faster turnaround time for billion transistor designs, it also delivers complete implementation and signoff-in-the-loop for low power, mixed signal, and advanced node design; including the latest 28nm process node where it has been used on over half of the designs being done at this node today.

As per Rahul Arya, since the initial launch, there has been significant usage and endorsement from the world's largest semiconductor companies, including ST, Toshiba, NEC, NXP, Fujitsu, AMD, and many more that are requested as non-public endorsements.

He added: "The announcement of InCyte and EDI System integration brings a whole new dimension for both system-level and design implementation teams. While both solutions -- InCyte and EDI System -- are still available as standalone, using both solutions together enables designers at all levels to now have complete visibility into all aspects of the design -- from system level architecture requirements and IP selection, to full physical floorplanning, final low power and implementation signoff results.

"The bringing together of both of these solutions delivers literally unprecedented predictability, visibility, and accuracy into all steps of the chip creation and implementation flow for faster design convergence."

The design solution will be demonstrated at the Design Automation Conference (DAC 2009) in San Francisco this month and made available later this year.

SMIC, Synopsys announce Reference Flow 4.0

MOUNTAIN VIEW, USA & SHANGHAI CHINA: Synopsys Inc. and Semiconductor Manufacturing International Corp. (SMIC), the largest foundry in China mainland, announced the availability of the 65nm RTL-to-GDSII reference design flow, version 4.0.

The reference flow, the result of collaboration between Synopsys Professional Services and SMIC, adds the Synopsys Eclypse Low Power Solution and IC Compiler Zroute technology, expanding the resources available to designers to address low power and design-for-manufacturing challenges at smaller process nodes. The result for customers is immediate access to an optimized path to SMIC silicon at 65-nm to help them meet aggressive project timelines.

The flow utilizes Synopsys' Galaxy Implementation Platform, a key part of the Eclypse Low Power Solution, providing designers with the ability to implement advanced low power techniques throughout the design flow including RTL synthesis and test, physical implementation and signoff stages.

In addition, IC Compiler's Zroute technology supports SMIC's 65-nm routing rules using advanced routing algorithms to evaluate the impact of manufacturing rules, timing and other design goals. The integration of Zroute balances design-for-manufacturing (DFM) optimization techniques with design timing, area, power and signal integrity goals for a particular chip design.

The reference design flow was validated using SMIC's in-house-developed CCS standard cell library, SRAM, PLL, IO Library and low power cell library. The validation included multiple Vdd and multiple supply blocks with power-gating and data retention.

Additional key features of the flow include multi-corner multi-mode (MCMM) optimization and critical area analysis and reduction, using IC Compiler, and design-for-test (DFT) synthesis combined with on-chip clocking control support for automatic generation of at-speed tests.

"SMIC's 65-nanometer logic process requires a flow that addresses critical timing, power leakage and DFM issues to reduce risk and increase the quality of results," said Paul Ouyang, vice president of Design Services Center at SMIC.

"We worked closely with Synopsys to once again deliver a solution that enables our mutual customers to take advantage of both companies' leading technologies. We look forward to an ongoing relationship with Synopsys as we move toward even more advanced process nodes."

"Synopsys works closely with our semiconductor foundry partners to enable our mutual customers to accelerate their designs into manufacturing," said Rich Goldman, vice president of Corporate Marketing and Strategic Alliances at Synopsys. "Our collaboration with SMIC gives IC engineering teams a proven reference flow to advance their SoC designs targeting SMIC's 65-nanometer process technology, leveraging Synopsys' low power and DFM technologies."

1st Asia Symposium on Quality Electronic Design -- July 15-16, Kuala Lumpur

SAN JOSE, USA & KUALA LUMPUR, MALAYSIA:The 1st Asia Symposium on Quality Electronic Design (ASQED09) has announced the final program consisting of several keynote speeches by industry leaders and experts from Synopsys, NXP, Cadence Design Systems, University of Tokyo, and Verdant Electronics, tutorials, panel discussion, and over 80 technical presentations.

This is the first ASQED event in Asia. The ASQED09 conference is being held on July 15-16, 2009 in Kuala Lumpur, Malaysia. ASQED plays a critical role in promoting quality-based electronic design and manufacturing in Asia and plans to be an integral part of establishing a communication link between semiconductor disciplines such as design, design methodologies, manufacturing, test, and packaging.

“As the electronics world moves from individual subsystem ICs to systems-on-chip (SoCs), design verification is becoming a crucial factor in overall product quality,” said Dr. Charlie Huang, Senior Vice President and Chief Strategy Officer of Cadence Design Systems, and ASQED keynote speaker.

“The ASQED conference provides an opportunity to highlight the growing need for advanced verification tools and methodologies so that engineers can ensure the quality of their designs and produce truly differentiated electronics products for the Asian market.”

Powerful keynotes headline conference
The list of plenary keynoters offers a comprehensive perspective from design, process, and tool methodologies. Keynoters include:

A New World of Partnerships for 22nm and Below
Dr. Chi-Foon Chan, President and COO, Synopsys

The Present Status and Issues in Solar Photovoltaic Systems
Prof. Takashi Tomita, Solar Quest, RCAST, the University of Tokyo

IC Packaging Technology - Electronic's New Gatekeeper for Cost and Performance
Joseph Fjelstad, Founder and President, Verdant Electronics

Trust But Verify – Product Quality in the SoC Era
Dr. Charlie Huang, SVP & Chief Strategy Officer, Cadence Design Systems

Variability-Resilient Mixed-Signal IC Design Methods
Dr. Hans Rijns, Vice President, head of Research, NXP Semiconductors, Netherlands

Tutorials
ASQED09 is pleased to offer the following tutorials by industry experts:

* Tera-scale Computing and Interconnect Challenges – 3D Stacking Considerations; Dr. Tanay Karnik, Intel, and
* Advanced Packaging Technologies and Future Interconnection Trends; Joseph Fjelstad, Verdant Electronics.

Panel discussion
Electronic Industry Trends and Implications for Asia
Moderated by Dr. Ali Iranmanesh, CEO & Chairman, Silicon Valley Technical Institute

Technical sessions
ASQED09 technical session consists of over 80 papers by engineers and researchers worldwide, covering the following topics:

* Circuit & System Design
* Test & Verification
* IC Packaging Technology
* PCB and PWB Technology & Manufacturing
* Semiconductor Technology & Manufacturing
* Nano and Bio Electronics Innovations
* Photovoltaic Technology & Manufacturing
* Electronic Design Automation Methodologies

The papers will be presented in three parallel tracks on Wednesday July 15th and Thursday July 16th.

ASQED09 corporate sponsors and supporters include Synopsys (Titanium Sponsor), Mentor Graphics (Platinum Sponsor), and Cadence Design Systems (Gold Sponsor). ASQED also includes select company exhibits.

Magma's Vivek Raghavan is new MD, India Operations

BANGALORE, INDIA: Magma Design Automation Inc. today announced the appointment of Vivek Raghavan as Managing Director of the company's India operations.

Raghavan will report to Roy E. Jewell, Magma President and Chief Operating Officer, as well as continue his current responsibility as Vice-president of Magma's Custom Design Business Unit, managing development of physical verification products.

“India is a key part of Magma’s overall strategy and we are looking to Vivek to continue working with our team there to expand the company’s role in India’s EDA fabric,” said Rajeev Madhavan, Magma’s Chairman and Chief Executive Officer. “He has been one of our senior managers in India and I expect he will work with our talented employees to continue the India operation’s success.”

Nearly 30 percent of Magma’s worldwide workforce operates in the company’s Bangalore, Mumbai and Noida facilities.

“Recent developments in Magma products demonstrate great technology and strong competitiveness," Raghavan said. “I’m very pleased to continue working with the team in India that has helped make these advancements possible.”

Vivek joined Magma in 2004 when it acquired Mojave Design, where he was Co-founder & CEO. Prior experience includes senior engineering management positions with Synopsys and Avant! Corporation, where he developed and managed successful products in physical design and parasitic extraction of integrated circuits. He holds a B.Tech degree in Electrical Engineering from IIT-Delhi and a Ph.D. in Electrical and Computer engineering from Carnegie Mellon University.

Synopsys continues Galaxy Custom Designer momentum with rel 2009.06

MOUNTAIN VIEW, USA: Synopsys Inc. has announced availability of advanced analog simulation and layout capabilities in its Galaxy Custom Designer implementation solution.

The new features in the 2009.06 release deliver productivity advances to aid analog circuit designers and layout engineers, enabling Synopsys to further extend its reach in the custom implementation segment.

The Custom Designer 2009.06 release adds significant new capabilities, including high-capacity, high-performance schematic-driven layout (SDL) designed for today's large analog blocks. The SDL capability features robust schematic and layout synchronization technology and a streamlined engineering change order (ECO) flow.

Also included in the 2009.06 release is an easy-to-use analog simulation and analysis environment featuring high-performance waveform display and processing, mixed text/schematic integration and Tcl scripting for batch verification.

"Designer productivity should quickly improve with Custom Designer's new capabilities. Additionally, the open environment and support for interoperable process design kits should enhance design reuse and portability," said Anand Valavi, group head and manager, Analog Mixed Signal Group at Wipro.

"The 2009.06 release of Custom Designer continues Synopsys' established record of delivering differentiated capabilities with the same high quality, ease-of-use and enhanced productivity that we have come to expect."

Introduced in September 2008, Custom Designer is a modern-era custom implementation solution that delivers superior ease-of-use and leverages Synopsys' Galaxy Implementation Platform to provide a unified solution for custom and digital designs. Built natively on the OpenAccess database, it offers unprecedented support for legacy designs and interoperable process design kits (PDKs).

"Our vision is to deliver the industry's most productive and open custom implementation solution," said Paul Lo, senior vice president and general manager of the Analog/Mixed-Signal Group at Synopsys. "We are breaking new ground and delivering innovative capabilities previously not available in existing products. This release represents a major step in our mission to deliver advanced technologies to enhance designers' productivity through automation."

Cadence unveils integrated chip planning and implementation solution

USA:Cadence Design Systems Inc. today unveiled a breakthrough solution that provides design and implementation engineers with superior visibility and predictability of chip performance, area, power consumption, cost, and time to market across the full range of design activities, including system-level design and IP selection through final implementation and signoff.

This unique and automated approach to semiconductor design has been achieved through the integration of Cadence InCyte Chip Estimator and the Cadence Encounter Digital Implementation (EDI) System technologies. The combination of these technologies increases the predictability of key metrics from design specification through final implementation while reducing overall IC project risk.

“As development costs of complex SoCs continue to skyrocket, manufacturers in all sectors are looking for increased visibility into their design processes,” said Richard Wawrzyniak, senior ASIC/SoC analyst at Semico Research Corporation. “By integrating capabilities from these two products, Cadence addresses a growing industry need by offering a solution that provides a unique and timely window into the development of a SoC.”

Decisions made during the architectural planning stages of the design cycle largely determine the chip’s resulting size, power consumption, performance, and cost. During these early stages design teams can realize the biggest benefits by considering and quantifying a variety of architectural and IP options prior to final design, implementation and signoff.

Traditionally, however, semiconductor designers have been forced to use a manual or disconnected approach to make estimations and architectural choices without the benefit of flexibility, automation, accurate analysis, or tight links to implementation tools. This new Cadence solution eliminates guesswork and provides a new data-driven and holistic approach to the optimization of IP selection and integration through architecture, design, implementation and signoff.

Using the new Cadence solution, designers can quickly and accurately estimate die size, power and cost, including real-time IP and manufacturing process what-if analysis to ease IP selection and determine design architecture and feasibility.

As a milestone in Cadence’s open, multi-vendor approach to IP, the solution leverages the vast ecosystem of IP at the ChipEstimate.com portal where over 200 IP suppliers and foundries contribute data to enable this accurate what-if analysis capability. Once system-level trade-offs and architecture are complete, designers can dynamically progress to the final implementation phase, leveraging estimates as a seed and driving to faster convergence.

Cadence’s EDI System completes the implementation and signoff of the design while monitoring and tracking aspects of block and full-chip progress, and also providing in-situ updates to actual die-size, power consumption, performance and cost with full transparency to all stakeholders. As optimizations in EDI System improve yield, size or power, users can immediately quantify those benefits in terms of the fully packaged chip cost.

“This new solution offers a unique new advantage to semiconductor design teams where all parties involved from system-level architects to chip implementation engineers can now make more informed and precise tradeoffs, including technical and economic metrics,” said Charlie Huang, senior vice president and chief strategy officer at Cadence. “It breaks down the barriers between both domains for a more transparent and predictive semiconductor development process. This cost-aware design philosophy is a new paradigm for design teams and addresses the critical market need of cost and risk reduction in IC designs.”

The new design solution will be demonstrated at the Design Automation Conference in San Francisco this July and be available later this year.

IC Validator offers step up in physical designer's productivity

Recently, Synopsys Inc. introduced an IC Validator design rule checking/layout verification signoff (DRC/LVS) for in-design physical verification and signoff for advanced designs at 45nm and below.

Said to provide a step up in physical designer productivity, it is architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use.

What does IC Validator do?
According to Sanjay Bali, Director of Marketing, Physical Verification & DFM, Synopsys, the IC Validator is a complete physical verification tool, performing increasingly complex DRC and LVS sign-off checks.

It has been specifically architected for in-design physical verification. This means: the place-and-route engineers can run DRC and practical DFM steps alongside place and route within the familiar IC Compiler physical design environment.

And, why need for such a solution? He added that three key summary challenges are driving the need for a new approach and hence the new tool. These are:
a) Increase in complexity and count of manufacturing rules.
b) Unabated growth on design complexity.
c) Increasing DFM challenges, which just cannot be handled in a post processing approach.

Currently, the solution is aimed at 45nm and below as these nodes largely represent the challenges listed above.

Enhancing physical designer's productivity
Three key tenants of the IC Validator that offer improved physical designer productivity are:
a) High accuracy necessary for leading-edge process nodes.
b) Superior scalability for efficient utilization of available hardware. And,
c) Ease of use with seamless integration of IC Validator and IC Compiler

Bali said: "The IC Validator has been architected from the ground up for in-design physical verification. In-design physical verification enables place-and-route engineers to accelerate the time to tapeout by enabling sign-off quality physical verification from within implementation or physical design. Physical designers designing with IC Compiler can now benefit from the in-design physical verification approach with the push of a button, incurring minimal overhead cost to eliminate surprises late in the design.

"With the verify-as-you-go approach replacing the implement-then-verify approach, physical designers can significantly reduce iteration count, eliminate streamouts and streamins, and accelerate time to tapeout. In addition, the integration enables several productivity enhancing flows like incremental DRC verification, incremental metal fill flows and ECO flows -- all leading to significant reduction in time to tapeout."

It would be interesting to determine or know by approximately what percent is the total physical verification time reduced, and what all does it cover in the process?

Bali added that in extreme cases, finding and fixing DRC violations can easily impact the schedules by a few weeks! The key here is that physical designers typically wait until the final stages of the tapeout to run physical verification. Inevitably, the schedule at this point is squeezed and the cost of fixing the error is high.

"With a sign-off quality physical verification tool integrated into the physical design environment, place-and-route engineers can verify as they implement and eliminate late surprises while speeding up the total physical verification turnaround time. In addition, the outcome of this process is a sign-off clean design.

Production ready!
The Synopsys IC Validator is also said to 'production ready!" What exactly does that mean?

The IC Validator has been successfully used to tapeout designs at several chip manufacturers, said Bali. In addition, it is currently being used for production designs at Nvidia and Toshiba. Besides other leading foundry's and chip manufactures it is also qualified by TSMC for 40nm and 28nm process nodes.

For those interested, Toshiba already has Synopsys as its key EDA partner, and NVIDIA adopted the IC Validator for sign-off physical verification, within days of its launch! More are bound to follow!

Saving design spins!
Will the IC Validator approach be able to save design spins? How much is the physical design cycle time reduced?

With the in-design physical verification, place-and-route engineers will be able to run sign-off quality DRC checks, timing aware and sign-off quality metal fill, all within the familiar IC Compiler environment. Linear scalability for efficient use of hardware, sign-off accuracy and integration with IC Compiler will enable productivity enhancing flows like auto detect and autofix, incremental verification flows -- all can significantly reduce time to tapeout.

How can it help in avoiding the painful sign-off failure-to-physical-redesign iterations that are increasingly common below 90nm?

With the seamless integration of the IC Validator with the IC Compiler, physical designers can now verify the design as they implement for manufacturing sign-off accuracy.

Incremental DRC's strength
How good is the incremental design-rule checker (DRC)? Is it really parallelized for the multicore servers?

According to Bali, incremental flows are one of the strongest tenants of IC Validator. To improve physical designer productivity, rule-based only or layer-based only incremental verification runs can be initiated from within IC Compiler.

He said: "For ECO validation, the IC Validator supports window or an area-based incremental verification approach to speed up surgical checks. The incremental flows are meant to be quick, but the IC Validator has multicore capability to further speed up the process."

The IC Validator discovers and fixes design rule violations within the global context of the design as well. How is this made possible?

With the in-design physical verification, the IC Validator can accurately and automatically identify DRC violation and automatically provide fix guidance to IC Compiler to fix the violation and then re-verify it again.

Handling metal fills and design changes
Operations typically performed during physical verification, such as metal fills, may trigger additional design changes to achieve timing closure. How is this handled by the IC Validator?

Bali said that the prevailing post-processing oriented DFM flows introduce excessive and lengthy discover-fix iterations. Metal fill insertion, a mandatory DFM step at the advanced nodes, exemplifies this issue.

"Physical designers stream out the timing closed post-fill design for signoff validation and then stream it back in to fix any signoff errors flagged during physical verification. This multi-hour discover-fix loop is typically repeated per block till the post-fill design is both signoff qualified and timing clean.

"With in-design physical verification, the IC Validator and IC Compiler address the challenges of DFM, within the place-and-route environment. The seamless integration enables a single pass metal fill flow that is timing aware and of signoff quality and is void of expensive streamouts and streamins," he added.

NVIDIA deploys Magma Talus 1.1 into production

BANGALORE, INDIA: Magma Design Automation Inc. announced that NVIDIA Corp. deployed Magma’s Talus 1.1 IC implementation system into full production.

Talus 1.1 offers significant improvements in routing, optimization and runtime as well as enhanced usability features. NVIDIA had been participating in the beta testing of the latest Talus release and, based on the positive results of the testing and improved flow performance, made the decision to start using Talus 1.1 for NVIDIA’s production design projects.

“We have recently upgraded to Talus 1.1 in our production environment based on significant improvements in the core algorithms, flow convergence and the overall usability,” said Patrick Sproule, manager of VLSI Design for NVIDIA. “In particular, the improvements in runtime, timing convergence and ECO routing have improved our throughput and quality of results.”

Magma’s unified data model is a key factor in the performance of the Talus chip implementation system. All the implementation and analysis engines in the Talus flow are built around, and have access to, the same data, and as a result flow convergence and turnaround times are shortened and optimization steps can be applied across the flow.

“We made a significant R&D investment in Talus 1.1 with the focus on improving overall performance and convergence while also improving the ease-of-use and efficiency of the system,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit.

“Our customers are implementing very complex chips and need the combination of a powerful, fast, high-quality chip design system that is also easy to drive. We made a specific effort in Talus 1.1 to develop simplified flows that reduce the number of commands required, but still deliver superior results in the finished design. We are very pleased with the fact that Talus 1.1 performed so well for NVIDIA that they have moved it onto their production chip design projects.”

Talus platform
Talus is a completely unified RTL-to-GDSII system for design implementation, with advanced capabilities for nanometer design. To address shorter time-to-market windows, Talus is the first implementation solution to multi-process the entire IC design flow. Its front-end design system provides logic designers with a fast, high-capacity, physically aware synthesis capability.

Its physical design system addresses variability and multimode/multicorner complexity with new optimization, place and route, and clock tree synthesis technology. To reduce leakage and dynamic power, Talus also provides a complete low-power design system. To improve manufacturability and reliability, Talus provides built-in design-for-manufacturing (DFM) features such as redundant via insertion, recommended end-of-line extension, and wire spreading & widening.