Magma supports SMIC processes with 65nm low-power reference flow

SAN JOSE, USA: Magma Design Automation Inc. announced availability of an advanced low-power IC implementation reference flow for the 65nm process and low-leakage-process intellectual property (IP) from Semiconductor Manufacturing International Corp (SMIC).

SMIC's 65-nm logic technology combines improved performance and reduced power consumption with the increased design possibilities and cost efficiencies that a smaller-node process offers.

Magma's Talus IC implementation system fully supports the SMIC 65-nm low-leakage process intellectual property (IP), including standard-cell libraries, power management kit (PMK) and memory compilers.

The Talus implementation flow coupled with Talus Power Pro applies various techniques throughout implementation and to minimize power consumption while maximizing quality of results.

Talus reduces turnaround time and the power consumption of ICs used in a wide range of consumer applications, such as mobile phones, PMPs, global positioning, digital TV, set-top boxes and mobile storage devices.

"Magma's development of an advanced low-power IC implementation reference flow for the SMIC 65-nm process technology demonstrates both companies' commitment to providing designers with tools and technology to improve performance and reduce power consumption of ICs," said Paul Ouyang, vice president of design services at SMIC.

"Talus is the only flow that enables designers to address power considerations throughout the flow and within a single environment," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "Using Talus, SMIC customers can get the best combination of performance, low power and fast turnaround times for complex designs."

The reference flow is available now at no cost to Magma customers.

SMIC achieves silicon success with high performance 45nm process

SHANGHAI, CHINA: Semiconductor Manufacturing International Corp. announced the successful completion of its first 45-nanometer high performance (GP, generic process with high performance) yield lot.

SMIC's high-speed, high performance 45nm GP technology integrates a silicon germanium stress module into the design, allowing the device to run faster, making it ideal for a number of applications, including system-on-chip, graphics and network processors, telecommunications and wireless consumer products, and serves as a technology platform for the fast growing China market.

The 45nm GP technology bookends with SMIC's silicon success on its 45nm low power (LP) technology, which is suitable for mobile devices that put a premium on low power consumption. SMIC signed an agreement with International Business Machines (IBM) to license its low-power and high-performance bulk CMOS technologies in December 2007. The GP technology transfer was completed in March 2009.

"I'm delighted with the progress of SMIC's 45nm project team, which continues to meet rigorous deadlines, and we appreciate the excellent support from IBM throughout this progress," said Dr. Robert Tsu, SMIC's 45nm project leader and Associate Vice President of Logic Technology. "Integrating the silicon germanium process and achieving a well-yielded test chip from the very first yield lot is a significant technical accomplishment, and these accomplishments allow SMIC to provide a highly manufacturable technology to our customers."

SMIC's 45nm GP technology is supported by a proven design-in SPICE model and in-house design IP capability that enables customers to begin prototype product design and plan for early time-to-market. In June, SMIC announced the adoption of new SPICE model software for the design and verification of 45nm IP blocks, I/O circuitry, and standard cell characterization flows.

As the company's 65nm low-power technology development cycle comes to a successful close, with a recently completed IP portfolio, multiple customer product qualification, and a ramping up of production, efforts have focused on 45nm. The readiness of SMIC's 45nm LP and GP technologies for design-in allows customers to enter a premium-value market.

"We are very excited and encouraged by the completion of our first 45nm high performance yield lot, another important signpost in SMIC's strategic plan," said Dr. Richard Chang, SMIC's President and CEO.

"It verifies the IBM-licensed technology, validates our strategic decision to invest in advanced logic technologies, and enhances SMIC's position as the advanced logic technology leader in China. This 45nm GP process is a proven, robust, high yielding, and high performance technology that we anticipate can not only deliver better performance, reliability, and cost to our valued customers, but also help SMIC become even more competitive in China and worldwide."

SMIC, Synopsys announce Reference Flow 4.0

MOUNTAIN VIEW, USA & SHANGHAI CHINA: Synopsys Inc. and Semiconductor Manufacturing International Corp. (SMIC), the largest foundry in China mainland, announced the availability of the 65nm RTL-to-GDSII reference design flow, version 4.0.

The reference flow, the result of collaboration between Synopsys Professional Services and SMIC, adds the Synopsys Eclypse Low Power Solution and IC Compiler Zroute technology, expanding the resources available to designers to address low power and design-for-manufacturing challenges at smaller process nodes. The result for customers is immediate access to an optimized path to SMIC silicon at 65-nm to help them meet aggressive project timelines.

The flow utilizes Synopsys' Galaxy Implementation Platform, a key part of the Eclypse Low Power Solution, providing designers with the ability to implement advanced low power techniques throughout the design flow including RTL synthesis and test, physical implementation and signoff stages.

In addition, IC Compiler's Zroute technology supports SMIC's 65-nm routing rules using advanced routing algorithms to evaluate the impact of manufacturing rules, timing and other design goals. The integration of Zroute balances design-for-manufacturing (DFM) optimization techniques with design timing, area, power and signal integrity goals for a particular chip design.

The reference design flow was validated using SMIC's in-house-developed CCS standard cell library, SRAM, PLL, IO Library and low power cell library. The validation included multiple Vdd and multiple supply blocks with power-gating and data retention.

Additional key features of the flow include multi-corner multi-mode (MCMM) optimization and critical area analysis and reduction, using IC Compiler, and design-for-test (DFT) synthesis combined with on-chip clocking control support for automatic generation of at-speed tests.

"SMIC's 65-nanometer logic process requires a flow that addresses critical timing, power leakage and DFM issues to reduce risk and increase the quality of results," said Paul Ouyang, vice president of Design Services Center at SMIC.

"We worked closely with Synopsys to once again deliver a solution that enables our mutual customers to take advantage of both companies' leading technologies. We look forward to an ongoing relationship with Synopsys as we move toward even more advanced process nodes."

"Synopsys works closely with our semiconductor foundry partners to enable our mutual customers to accelerate their designs into manufacturing," said Rich Goldman, vice president of Corporate Marketing and Strategic Alliances at Synopsys. "Our collaboration with SMIC gives IC engineering teams a proven reference flow to advance their SoC designs targeting SMIC's 65-nanometer process technology, leveraging Synopsys' low power and DFM technologies."

SMIC deploys Synopsys HSPICE simulator for 45nm physical IP and standard cell development

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Semiconductor Manufacturing International Corp., one of the leading semiconductor foundries in the world, has adopted Synopsys' HSPICE circuit simulator and WaveView Analyzer for design and verification of its 65nm and 45nm IP blocks, I/O circuitry and standard cell characterization flows.

Taking advantage of the innovations in the 2009.03 release of the HSPICE circuit simulator, SMIC was able to cut simulation runtime in half with improved silicon correlation over their existing solution.

"With HSPICE, we were able to run our analog IP and standard cell circuits two times faster than our existing solution," said Paul Ouyang, vice president of Design Services at SMIC. "In addition, WaveView Analyzer significantly improved our verification productivity by delivering an easy-to-use, feature-rich and high-performance waveform analysis solution. We are now able to instantly render large waveforms and run automatic specification verification functions."

"The 2009.03 release of HSPICE delivers further simulation speed improvements on both single- and multicore computer hardware while maintaining the same trusted silicon-accurate results," said Graham Etchells, director of marketing for the Analog/Mixed-Signal Group at Synopsys. "Continuing innovations in HSPICE, WaveView Analyzer and other AMS circuit simulation solutions enable foundries worldwide to accelerate development of advanced process nodes."

The HSPICE simulator is widely recognized as the "gold standard" for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With more than 25 years of successful design tapeouts, the HSPICE simulator is one of the fastest and most trusted circuit simulators.

HSPICE is an integral component of Synopsys' Discovery Verification Platform, which offers high-performance functional and mixed-signal verification to enable designers to achieve the highest throughput and accuracy for complex mixed-signal system-on-chip (SoC) designs.

SMIC announces 65nm low leakage process IP portfolio

SHANGHAI, CHINA: Semiconductor Manufacturing International Corp., a leading semiconductor foundry and the most advanced in Mainland China, announced the availability of a set of 65-nanometer low leakage process IPs, including the preliminary version release of six memory compliers. This portfolio, which contains a number of new, ready-to-use IPs, follows the 65nm standard cell libraries that were released earlier this year.

The centerpiece of SMIC's new 65nm IP offerings is the set of six memory compilers, which enable the intelligent and rapid generation of memory blocks in bulk and on the fly. The compilers include memories optimized for very high performance and also optimized for performance and area.

These critical IPs, along with many others in the portfolio, were developed internally by SMIC's design services group with rigid design methodology. The silicon validation is undergoing. The 65nm IP portfolio can be used to design a wide range of consumer applications such as mobile phones, personal media players, GPS, DTV, set-top boxes, and mobile storage devices.

Since SMIC's 65nm library was developed in-house, it offers customers a number of advantages in flexibility and customizability, allowing for the library to be easily tuned to processes and recharacterized according to customer requests, streamlining the design flow and improving time to market.

"This 65nm IP portfolio are targeting both low power and high speed applications, allowing customers to come in and start designing a wide range of system-on-chip projects," said Paul Ouyang, SMIC's Vice President of Design Services, adding that the company has already engaged a number of customers in the 65nm node.

"The set of memory compilers is a full-featured high quality product, and this accomplishment is a testament to the talented and dedicated engineers in SMIC's design services group," he added. Scheduled production release of the memory compilers will be on June 30th. Additional in-house and 3rd party 65nm IPs are under development, which are planned to be available to customers later this year.

Customers will have an opportunity to examine SMIC's 65nm IP offerings at an SMIC workshop scheduled on June 5.

Global and China semiconductor industry report 2008-09

NEW YORK, USA: Reportlinker.com has added a new market research report is available in its catalogue, the Global & China Semiconductor Industry Report, 2008-2009.

According to China Semiconductor Industry Association, the integrated circuit industry scale was totaled at CNY 124.682 billion in 2008, a reduction of 0.4 percent of last year, which was the first time that a negative growth occurred in the recent 20 years.

Driven by the constant consumption upgrading and 2008 Beijing Olympic Games, the industry maintained a growth of 10.4 percent in the first half of 2008, 12.5 percent and 8.3 percent, respectively in the first quarter and second quarter. However, the growth rate sharply declined to 1.1 percent in the third quarter, and a negative growth of -20 percent in the fourth quarter, which was the biggest quarterly drop in the recent 20 years.

Considering the policy, China’s semiconductor industry is currently in the dilemma, giving preferential policies will lead the issue of trade protectionism by the countries rely on semiconductor products export such as the USA; if not, the Chinese companies will be more difficult to survive facing oversea competitors.

China is the largest IC market in the world, with a market scale at US $85 billion in 2008, but the market share of domestic suppliers was less than 7 percent. Although China is the global factory of electronics products, the orders and shipments are both controlled outside.

Considering the IC design, China has few of IC design houses like Solomon, Actions, Spreadtrum and Vimicro. The Solomon, derived from the LCD division of Motorola, relies on Motorola, lack of product innovations. Backed by the Realtek, the Actions is the world’s largest sound card manufacturer and has an outstanding performance in the digital audio field.

Spreadtrum recorded a reduction of 50 percent in the fourth quarter of 2008, far higher than Mediatek. Protected by the huge domestic demand for PC camera, Vimicro stays steady; however, caused by its high labor cost, the company recorded successively operational loss in the last four quarters.

IC design sector suffered the most with the transfer of international financial crisis to the real economy, especially those newly established companies due to the break of their capital chain, venture investors also draw back, and the A-turn investment dropped 82 percent during 2000-2007. According to GSA, there were 74 companies shut down since Oct 2008, and most of which were small companies.

Nevertheless, the wafer OEM maintains a high expansion in China. Since its establishment in the year of 2000, SMIC has built productions in Shanghai, Beijing, Tianjin, Chengdu, Wuhan and Guangzhou through M&A and trusteeship.

In addition, guided by Shanghai Government, the Huahong Group acquired Grace Semiconductor at the beginning of 2009, along with an extra investment of US $2.2 billion for a 12-inch wafer plant. However, the fact is that SMIC has been recording a loss since its establishment.

The cost structure of semiconductor manufacturing is roughly as following: machine depreciation 50 percent, materials 20 percent, water and power 5 percent, and labor 10 percent. For Chinese companies, only 15 percent of the cost can be controlled, while the part has been played to the full extent. Moreover, the unilateral understanding to scale has fettered their imaginations of strategy, which makes the semiconductor industry in the situation of unmerited scale.

In addition, the semiconductor industry is always protected by governments, dare not or unwilling to face with the market-oriented risk. The Chartered is a typical example.

There are two typical development routes regarding the wafer OEM, one is represented by the TSMC: focus on the technology and high-profit business; the other is represented by the UMC: huge investment on IC design houses for the purpose of production capacity enhancement, for example, the investment to MTK, Novatek and SIS are all proved successful.

Novatek is the second largest IC design house in Taiwan, as well as the global second largest TFT-LCD drive IC manufacturer. MTK is the top mobile phone vendor and the 7th largest IC design house in the world, as well as the largest IC design house in Taiwan.

It is not enough to just invest a huge capital and the semiconductor industry also requires more input in the basic science and technology especially in China.