Toshiba deploys Magma Talus for 90-, 65- and 40-nm ASICs and ASSPs

BANGALORE, INDIA: Magma Design Automation Inc. announced that Toshiba Corp. has deployed Magma’s Talus IC implementation software for developing ICs at 90-, 65- and 40-nanometer (nm) process nodes that target multimedia, networking and printer applications, in Toshiba worldwide design centers.

Toshiba adopted Talus after an extensive evaluation that proved the software’s ability to drastically reduce turnaround time, increase designer productivity and improve quality of results.

Toshiba deployed Magma design implementation software in Toshiba’s Apex flows in 2001, and now has finished multiple designs including 65-nm and 40-nm tapeouts using Talus through its Apex 4.0 flow.

“Toshiba has demanding delivery schedules and performance requirements, and Magma has been instrumental in enabling us to address ever-increasing design and market challenges,” said Takashi Yoshimori, Assistant Chief Technology Executive of SoC Design, Semiconductor Company, Toshiba Corp.

“Talus recently allowed us to reduce turnaround time drastically and improve leakage power and area for a multi-mode SoC design with more than 10 million gates. Based on this achievement and proven track record, we are now implementing our 90-, 65- and 40-nm designs with Talus.”

“For Toshiba and its customers, reducing turnaround time is key,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit. “Toshiba’s adoption of Talus firmly establishes Magma’s software as the fastest path to silicon.”

Magma's Talus enables eSilicon to implement 400-million-gate designs

SAN JOSE, USA: Magma Design Automation Inc. announced that eSilicon Corp., a pioneering semiconductor value chain producer (VCP), is completing the implementation of several very large customer designs using the Talus IC implementation system, including Talus Design, Talus Vortex and Hydra.

These designs are being implemented in a 65-nanometer (nm) process and are more than 500 sq. mm in area, with more than 400 million gates. This is the equivalent of 30 million placeable objects, including more than 100 million bits of memory and more than 2,000 memory instances.

These highly complex chips require eSilicon to use a design solution with extremely high capacity and the ability to deliver fast turnaround on design planning and implementation.

In addition, given a tight delivery schedule, eSilicon needed a system that would be usable "out of the box" without a lengthy setup cycle. Magma's field team partnered with the eSilicon design team to deploy Talus.

"We selected Talus for these large designs because of its capacity and our need to minimize our deployment time and keep the implementation cycle as short as possible," said Prasad Subramaniam, vice president of Technology of eSilicon. "The high complexity of these designs poses a significant challenge in productivity and turnaround time.

"We are pleased that the Talus multi-CPU feature works smoothly and yields significant improvement across a broad implementation flow. We have our default implementation build scripts for large blocks to use two CPUs and we increased to four CPUs for critical runs. This allowed us to gain 1.5 times to 3 times improvement in turnaround time on these large designs."

eSilicon found Talus to be well suited for these designs. Talus' underlying unified data model architecture contains the entire set of data associated with the design. The complete design data can be exported or imported at any time as a Volcano(tm), Magma's proprietary database format.

One of the eSilicon designs is based on a collaborative development model with the customer, and Talus' unified architecture simplifies the efficient handoff of design data via Volcanoes at various points during the implementation process.

In addition, Talus' core multi-CPU feature and enhanced GlassBox modeling for timing enabled very significant improvement in the turnaround times for implementation and analysis.

One key challenge for these complex chips is the turnaround times for top-level analysis and optimization. eSilicon is making extensive use of a new Hydra GlassBox abstraction capability.

This enhanced GlassBox abstraction feature yields extremely compact representations of the blocks that contain all the physical, timing and extraction data necessary for fast and accurate chip-level analysis and optimization without consuming enormous amounts of memory.

Because of this new "cached delay" feature for GlassBox abstraction, the latest Talus release requires less than 50 percent of the memory resources required by the previous Talus version and delivers up to a 5X improvement in runtime compared to the previous GlassBox approach.

"The fast deployment of Talus and implementation of these designs is a testament to eSilicon's engineering skill and demonstrates Talus' ability to handle large, complex designs," said Premal Buch, general manager of Magma's Design Implementation Business Unit.

"The size of these designs and the speed of deployment demonstrate the major improvements in capacity, runtime and usability that have been engineered into the latest Talus release. It also validates Hydra's capability for managing the top-level design and optimization of very large designs without excessive memory consumption."

Magma supports SMIC processes with 65nm low-power reference flow

SAN JOSE, USA: Magma Design Automation Inc. announced availability of an advanced low-power IC implementation reference flow for the 65nm process and low-leakage-process intellectual property (IP) from Semiconductor Manufacturing International Corp (SMIC).

SMIC's 65-nm logic technology combines improved performance and reduced power consumption with the increased design possibilities and cost efficiencies that a smaller-node process offers.

Magma's Talus IC implementation system fully supports the SMIC 65-nm low-leakage process intellectual property (IP), including standard-cell libraries, power management kit (PMK) and memory compilers.

The Talus implementation flow coupled with Talus Power Pro applies various techniques throughout implementation and to minimize power consumption while maximizing quality of results.

Talus reduces turnaround time and the power consumption of ICs used in a wide range of consumer applications, such as mobile phones, PMPs, global positioning, digital TV, set-top boxes and mobile storage devices.

"Magma's development of an advanced low-power IC implementation reference flow for the SMIC 65-nm process technology demonstrates both companies' commitment to providing designers with tools and technology to improve performance and reduce power consumption of ICs," said Paul Ouyang, vice president of design services at SMIC.

"Talus is the only flow that enables designers to address power considerations throughout the flow and within a single environment," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "Using Talus, SMIC customers can get the best combination of performance, low power and fast turnaround times for complex designs."

The reference flow is available now at no cost to Magma customers.

Chartered offers 65nm RF platform for single-chip wireless apps

SINGAPORE: Chartered Semiconductor Manufacturing, one of the world’s top dedicated foundries, today announced a robust 65nm RF platform specifically geared for developers of single-chip RF products.

The Chartered process offering, jointly developed with IBM, is based on Chartered’s enhanced 65nm low-power process (65nm LPe), and includes an IBM RF physical design kit (PDK) available from Chartered. This RF Platform comes with broad RF design enablement from leading analog IP suppliers and the Wireless SoC Platform Alliance (WISPA) consortium.

The RF platform is supported by an RF PDK specifically for the 65nm LPe process. The kit significantly reduces design time and helps ensure first-time-right silicon for full-featured SoCs with integrated RF.

It has been characterized and silicon-validated on the process on Chartered-manufactured silicon, and uses proven techniques from IBM to achieve a high degree of model-to-silicon accuracy. The PDK enables a more flexible methodology, based on a unique parameterized cell (p-cell) design approach that allows designers to tune RF components in a wide variety of ways.

The comprehensive PDK consists of a full palette of transistors and passives, including high fT RF transistors, vertical native (VNCAPs) and MIM capacitors, large tuning range MOS varactors, high Q-factor shielded inductor, precision poly resistors, and RF ESD devices.

These device solutions are complemented by RF-centric p-cells, an inductor synthesis kit, EM simulators setup files support and substrate noise analysis kit.

Single-chip RF solution
As consumer multi-media mobile applications continue to expand in features and functionality, integrated high-speed wired and wireless connectivity have become essential.

Combining high-speed wired and RF subsystems on a single SoC has been a challenge for most companies, historically forcing them to use the less favorable option of multiple-chip solutions that compromise cost and end-product form factor.

The RF platform from Chartered is intended to reduce the time, cost and risk associated with developing single-chip solutions that incorporate RF by making the latest process technology more accessible for those applications.

“The IBM Joint Development Alliance, known primarily for its advanced CMOS process technology development, has now added derivative technology development to the collaboration portfolio,” said Scottie Ginn, vice president of Design Enablement and Packaging, IBM Semiconductor Research and Development Center.

“We have invested heavily in developing a methodology that ensures the highest level of accuracy in RF design. Chartered has leveraged this RF methodology for its 65nm process to realize the full potential of the underlying process technology.”

In addition, a wide spectrum of IP support for RF applications is available for the 65nm RF platform. This includes silicon tested RF subsystems for WiFi, WiMax, and GPS; a host of industry standard interfaces (mDDR/DDR/DDR2, USB 2.0, PCI express, SATA II, and LVDS); and functional analog /mixed signal subsystems (Analog Front End, Audio CODEC, Video ADC/DAC, PLL/DLL, and baseband DAC/ADC).

Through Chartered’s participation in and support of the WISPA consortium, the 65nm RF process is backed by leading RF and SoC design services companies that can facilitate IP customization and software development via reference boards.

WISPA participants Socle Technology Corporation and Catena have worked together to develop a modular platform consisting of RF and baseband functions centered on hardened ARM9 and ARM11 microprocessor cores.

“By using the Chartered 65nm RF platform and RF PDK, all our silicon test chip measurements correlate extremely well with the simulation and we are able to achieve good progress with the system design in a very short time and with high confidence of getting the expected result.

"We believe that wireless connectivity will be commonplace in the mobile market and our goal is to make the integration of those wireless subsystems as accessible as possible so that product companies can focus on other phases of the hardware and software solution,” said Kave Kianush, CTO and vice president at Catena.

“Close collaboration with our partners and industry specialists in the RF and wireless ecosystem is essential to being able to offer a robust solution that addresses the needs of leading-edge mobile and wireless product developers.

"Combined with their specific capabilities and technology, our underlying process technology makes an ideal foundation for a market-ready integrated SoC platform. The silicon-verified mixed-signal/RF PDK serves to facilitate analog, mixed-signal and RF designs, RF SoC integration and verification,” said Dr. Shao-Fu “Sanford” Chu, vice president of device technology division, technology development at Chartered.

Enhanced 65nm low-power process
Chartered’s enhanced 65nm low-power process (65nm LPe) features multi-voltage threshold options for optimizing power and performance, and 4-9 metal layers to optimize die size requirements.

It offers support for a rich portfolio of RF and analog components, and is supported by a robust ecosystem of EDA tools and IP blocks, including a broad offering of standard cell and IO libraries from leading suppliers.

“The types of wireless-enabled products being developed by our mutual customers require a high level of IP integration to support the growing feature sets requested by consumers.

Chartered’s enhanced 65nm low-power technology delivers unique advantages by providing market-leading leakage benefits and support for a wide portfolio of proven IPs for SoC integration.

Socle’s expertise in ARM9 and ARM11 integration leverages the ecosystem supported on Chartered’s 65nm LPe platform and allows efficient customization of the feature set requested by a customer to bring its products to market faster and at lower risk,” said Chou-Te Kang, vice president of R&D at Socle.

Chartered begins production ramp of enhanced 65nm low-power process

SINGAPORE: Chartered Semiconductor Manufacturing announced the general availability of an enhanced version of its 65nm low-power (LP) process, called 65nm LPe.

The 65nm LPe process utilizes innovative leakage-reduction techniques to significantly improve system-on-chip (SoC) standby power consumption by up to 50 percent.

The result is a lower-power process especially suited for battery-operated and cost-sensitive mobile applications that require active standby conditions, such as mobile handsets, multimedia players or personal internet devices. The process is also supported by a robust range of IP specifically optimized for the lower leakage capabilities.

Chartered is also offering an optimized RF platform solution based on the 65nm LPe process that combines RF physical design kits, broad IP support and a collaborative development system with its partners from the Wireless SoC Platform Alliance (WISPA) consortium. (See additional press release from July 13, 2009: “Chartered Offers 65nm RF Platform To Enable Single-Chip Wireless Applications”).

The 65nm LPe process significantly improves the performance-to-leakage ratio (Ion/Ioff) within the process’ pMOSFET. Given the same Ion (uA/um), the Ioff current is reduced by a magnitude of 20X.

This directly impacts the battery life of mobile applications as this leakage improvement is observable in both active and standby situations. In cases where a product operates in long standby situations such as a mobile phone, improvement in the standby power consumption can be as great as 15-25 percent, depending on the application.

A full suite of IP is available for the new process from leading suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic Circuits, Denali, Synopsys, True Circuits and Virage Logic.

The support includes analog front end (AFE), audio codecs, standard interfaces and a range of level physical IP libraries and memory compilers that have been specifically tuned to take advantage of the enhanced leakage capabilities of the process.

Chartered’s enhanced 65nm LPe process features a core 25 angstrom transistor oxide with three voltage options (Standard Vt, Low Vt, High Vt). The High Vt option offers the lowest leakage at 0.01nA/um and 0.007nA/um for the NMOS and PMOS transistors, respectively.

Two thick gate oxides are available: a 32A device for 1.8V; and a flexible, IP-enabled 2.5V 52A device that is also useable for 1.8V and 3.3V applications by varying the channel length. The back end of line (BEOL) metal implementation supports up to nine layers of copper to optimize die size and routing efficiency.

Manufactured on rotated substrates, the 65LPe process benefits from an increase in the pMOSFET hole mobility and saturation velocity without detrimentally affecting the nMOSFET.

“Today’s high-volume mobile applications require highly optimized silicon solutions that operate in an extremely power-efficient manner, but don’t compromise performance or functionality,” said Brian Klene, vice president, product marketing at Chartered.

“Our 65nm LPe process has been developed specifically with extended battery life in mind, with optimizations made to the process itself and our ecosystem of design support to improve efficiency significantly. The 65nm LPe process is a full-featured and flexible platform on which a wide variety of wireless, mobile and multimedia products can be based.”

Silicon Frontline software qualifies for TSMC’s iRCX format for 40/65nm

LOS GATOS, USA: Silicon Frontline Technology, Inc. (SFT) announced that its 3D extraction software for post-layout verification, F3D (Fast 3D), has been qualified by TSMC for its 40 nanometer (nm) and 65nm processes as the tool supports TSMC’s new iRCX format to improve parasitic extraction and modeling accuracy, and ensures EDA tool interoperability for high performance chip designs.

Silicon Frontline post-layout verification software produces accuracy and high performance by using rigorous 3D technology to extract parasitics. Users have the option to specify the level of accuracy desired, net by net, at the block level or with regular expressions. With this technology, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.

“We are pleased to have the world’s leading foundry, TSMC, qualify our 3D extraction software for post-layout verification of designs targeting its 40 and 65nm processes,” said Yuri Feinberg, CEO. “With our software, TSMC’s customers can achieve required accuracy with full chip capacity and performance.”

“Through the TSMC Open Innovation PlatformTM, TSMC collaborates with multiple EDA suppliers to create and qualify design tools for designs targeting our advanced semiconductor processes,” added Tom Quan, deputy director, Design Service Marketing at TSMC. “Silicon Frontline’s 3D extraction software is one of the first EDA tools that passes our iRCX Qualification Program, and is now ready to be used by our customers.”

UMC qualifies Silicon Frontline’s parasitic extraction software for 40/65nm

LOS GATOS, USA: Silicon Frontline Technology Inc. (SFT) announced that its 3D extraction software for post-layout verification, F3D (Fast 3D), has been validated by semiconductor foundry United Microelectronics Corp. for 40 and 65nm processes.

F3D provides field solver accuracy for full-chip design, enabling higher quality extraction and faster post-layout verification closure.

UMC qualified Silicon Frontline’s F3D for post-layout verification because it guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics.

Users can specify the level of accuracy desired, net by net, at the block level or with regular expressions. By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.

"Qualifying design tools such as Silicon Frontline’s F3D aids our customers in choosing the software they need to design complex, high performance ICs and to confidently achieve silicon success," said Stephen Fu, IP Development and Design Support director, at UMC. "The combination of F3D technology with our advanced manufacturing processes, gives customers a more predictable and smoother flow to silicon success.”

“We are pleased to have one of the world’s leading foundries, UMC, support our 3D extraction software for post-layout verification of designs targeting its advanced processes,” said Yuri Feinberg, CEO. “With our software, UMC customers can experience Guaranteed Accuracy with full-chip capacity and performance.”

Magma's QuickCap NX certified to support TSMC iRCX format for 40nm

BANGALORE, INDIA: Magma Design Automation Inc. announced that QuickCap NX has been certified to support the parasitic extraction and modeling accuracy requirements of the TSMC iRCX format for ICs targeting 65nm and 40nm processes.

With the consistent data provided by the iRCX format, designers can use Magma QuickCap NX to extract accurate parasitic-capacitance values based on the truest 3D representation of the physical circuit. Accurate capacitance values are critical for calculating many properties of chip performance, including capacitive crosstalk, RC delay time and power consumption.

With QuickCap NX and the iRCX format, designers can more accurately predict IC performance prior to manufacturing, allowing them to either make modifications or proceed with confidence in achieving silicon success.

The TSMC iRCX is an interoperable interconnect modeling data format that ensures the accuracy of resistance/capacitance (RC) extractors, electromigration (EM) tools, power integrity analysis tools and electromagnetic simulators. iRCX is the first of several interoperable EDA interface formats co-developed between TSMC and its design tool partners as part of the TSMC Open Innovation Platform (OIP).

“At the 40nm and 65nm nodes, the ability to generate accurate interconnect models at a high frequency can create a bottleneck in the design flow,” said Tom Quan, deputy director, Design Service Marketing at TSMC. “By working together to qualify QuickCap NX for TSMC iRCX format, TSMC and Magma ensure designers have the most accurate models, breaking design flow bottlenecks and enabling first-pass design success.”

“TSMC has been using QuickCap NX as the standard deviation comparison target for RC extraction tools on special pattern structures and real design samples,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit. “The TSMC qualification of QuickCap NX for the iRCX format provides our mutual customers with further confidence that Magma’s 3D field solver is the industry gold standard for parasitic extraction.”

QuickCap NX: Gold standard in parasitic extraction
QuickCap NX is used by major semiconductor companies as the reference standard for parasitic extraction. It is a highly accurate 3D extractor that precisely models advanced process effects such as optimal proximity correction (OPC), chemical-mechanical polishing (CMP) and trapezoidal wires.

QuickCap NX is proven to closely correlate to exact analytical solutions and silicon measurements, delivering capacitance values that are within 1 percent of silicon measurements.

It provides dial-in accuracy and error-bounds reporting on each net, giving the user complete control and trust in the accuracy of results. Leading foundries have validated QuickCap NX's ability to more closely match silicon measurements. By taking process effects into account, the average difference between QuickCap NX capacitance values and actual silicon measurements has been reduced from 9.79 percent to just 0.11 percent.

QuickCap NX in the Magma flow
QuickCap NX can be used for post-layout analysis in the Magma flow. QuickCap technology is also incorporated into the Talus physical design software system to support highly accurate timing and noise analysis during chip implementation. It is used to compute the highly accurate capacitance rules used within Talus and the Quartz RC sign-off extraction tool.

Silicon results validate design for eBeam methodology at 65nm

SAN JOSE, USA: The eBeam Initiative, a forum dedicated to the education and promotion of a new design-to-manufacturing approach known as design for e-beam (DFEB), announced that steering group members D2S, Inc., e-Shuttle, Inc. and Fujitsu Microelectronics have validated the DFEB methodology for low-volume, 65-nm system-on-chip applications, without sacrificing performance, area or power.

DFEB combines software and design technologies that enable today’s most advanced character projection (CP) e-beam direct-write (EbDW) equipment to reduce shot count, thus making EbDW throughput feasible for low-volume designs. The announcement marks a significant milestone as it demonstrates early progress on the three-year roadmap.

The final estimated shot count for the test chip using DFEB represented a more than 10X reduction over conventional EbDW technologies, while also meeting the required performance, power and area goals. The collaborative effort drew from a number of companies involved in the eBeam Initiative.

Specifically, D2S and Fujitsu Microelectronics worked on the design while e-Shuttle manufactured the test chip to confirm the DFEB technology for the 65-nm node. D2S designed the DFEB library overlay with Fujitsu Microelectronics and also partnered closely with e-Shuttle and Advantest Corporation on the stencil mask used in the fab’s EbDW machine. Prototyping is a target application for DFEB, and with e-Shuttle’s experience in these services, they were able to validate the applicability of DFEB for prototyping.

According to Yoji Hino, corporate executive vice president of Fujitsu Microelectronics Limited and member of the eBeam Initiative steering group, “With this test chip, we now have tangible results that DFEB is enabling us to meet the necessary shot count requirements without sacrificing the quality of design results. DFEB makes maskless prototypes practical now.”

A related paper jointly authored by Advantest, D2S, e-Shuttle and Fujitsu Microelectronics Limited will be presented by e-Shuttle at the session of Electron Beam Lithography Tools during the 53rd International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), taking place May 26-29 in Marco Island, Fla.

The article, titled: “DFEB, a novel approach to EbDW throughput enhancement for volume production,” will be available online after May 29 at www.ebeam.org.

SMIC announces 65nm low leakage process IP portfolio

SHANGHAI, CHINA: Semiconductor Manufacturing International Corp., a leading semiconductor foundry and the most advanced in Mainland China, announced the availability of a set of 65-nanometer low leakage process IPs, including the preliminary version release of six memory compliers. This portfolio, which contains a number of new, ready-to-use IPs, follows the 65nm standard cell libraries that were released earlier this year.

The centerpiece of SMIC's new 65nm IP offerings is the set of six memory compilers, which enable the intelligent and rapid generation of memory blocks in bulk and on the fly. The compilers include memories optimized for very high performance and also optimized for performance and area.

These critical IPs, along with many others in the portfolio, were developed internally by SMIC's design services group with rigid design methodology. The silicon validation is undergoing. The 65nm IP portfolio can be used to design a wide range of consumer applications such as mobile phones, personal media players, GPS, DTV, set-top boxes, and mobile storage devices.

Since SMIC's 65nm library was developed in-house, it offers customers a number of advantages in flexibility and customizability, allowing for the library to be easily tuned to processes and recharacterized according to customer requests, streamlining the design flow and improving time to market.

"This 65nm IP portfolio are targeting both low power and high speed applications, allowing customers to come in and start designing a wide range of system-on-chip projects," said Paul Ouyang, SMIC's Vice President of Design Services, adding that the company has already engaged a number of customers in the 65nm node.

"The set of memory compilers is a full-featured high quality product, and this accomplishment is a testament to the talented and dedicated engineers in SMIC's design services group," he added. Scheduled production release of the memory compilers will be on June 30th. Additional in-house and 3rd party 65nm IPs are under development, which are planned to be available to customers later this year.

Customers will have an opportunity to examine SMIC's 65nm IP offerings at an SMIC workshop scheduled on June 5.

Cypress unveils first SRAM on 65nm

SAN JOSE, USA: Cypress Semiconductor Corp. announced it is sampling the industry’s first Quad Data Rate (QDR) and Double Data Rate (DDR) SRAM devices on 65-nm linewidth.

The 72-Mbit QDRII, QDRII+, DDRII and DDRII+ memories leverage process technology developed with foundry partner UMC. The SRAMs feature the market’s fastest available clock speed of 550 MHz and a total data rate of 80Gbps in a 36-bit I/O width QDRII+ device, using half the power of 90nm SRAMs.

They are ideal for networking applications, including Internet core and edge routers, fixed and modular Ethernet switches, 3G base stations and secure routers, and also enhance the performance of medical imaging and military signal processing systems. The devices are pin compatible with 90nm SRAMs, enabling networking customers to increase performance and port density while maintaining the same board layout.

Compared with their 90nm predecessors, the 65nm QDR and DDR SRAMs lower input and output capacitance by 60 percent. The QDRII+ and DDRII+ devices have On-Die Termination (ODT), which improves signal integrity, reduces system cost and saves board space by eliminating external termination resistors. The 65nm devices use a Phase Locked Loop (PLL) instead of a Delay Locked Loop (DLL), which enables a 35 percent wider data valid window to reduce development time and cost for the customer.

“We continue to expand our Synchronous SRAM portfolio to broaden our target markets and grow market share,” said Dana Nazarian, Executive Vice President of the Memory and Imaging Division at Cypress. “Cypress is committed to supporting the SRAM market long-term and building on our leadership position.”

90pc fab investments for 300mm capacity: SEMI

Recently, SEMI (Semiconductor Equipment and Materials International) released its World Fab Forecast report. This report mentions that projected decline in world semiconductor fab equipment spending of 20 percent is likely for 2008. However, a rebound of over 20 percent in spending is expected in 2009, driven by over 70 fab projects.

The August 2008 edition of this report lists 53 fab equipping projects and up to 21 construction projects for fabs in 2009. It is sincerely hoped that at least one of the fabs likely from the Southeast Asian region is from India!

With the help of Scott Smith Senior Manager, Public Relations, SEMI, I was able to get in touch with Christian Gregor Dieseldorff, Senior Manager of Fab Information and Analysis at SEMI, in an attempt to find out more about the decline in global fab spends, these new fabs, and how these fabs can lead a turnaround in the global semiconductor industry. Thanks Scott!

So what are the chief reasons for the decline in fab spends during 2008? According to Dieseldorff, given the weaker economic conditions globally, coupled with higher energy and commodity prices and the financial crisis, the overall outlook for semiconductor growth in 2008 is for low-single digit growth in both revenues and units. As such, device makers have responded by cutting back their capital spending and pushing out fab projects or putting them on hold.

I was keen to find out the geographic breakup of these 70 new fabs that are likely yo come up in 2009.

Dieseldorff advised that these are not 70 new fabs coming up in 2009. Rather, the numbers reflect 300mm fabs only, and is a mix of on-going and new projects for fabs equipping and fab construction projects in 2009.

For equipping 300mm fabs, SEMI expects about: Americas 8, China 5, Europe and Mideast 4, Japan 7, South Korea 11, SE Asia 3 and Taiwan 15.

For 300mm fab construction projects, SEMI expects about: Americas 3, China 2, Europe and Mideast 1, Japan 2, South Korea 3, SE Asia 2 and Taiwan 8.

What are the salient features of some of these new fabs likely to come up next year (for instance, new tech nodes)? Dieseldorff highlighted that about 90 percent of the investments are for 300mm capacity, and the amount of spending for advanced nodes, such as 65nm, is increasing.

"Also, device makers are building larger fabs, which are termed "mega fabs," so, to potentially realize a greater return based on scales of economy," he added.

How will these new fabs contribute to a better performance from the global semicon industry? This will be quite interesting to witness.

Dieseldorff said that over the past several years, demand for semiconductor devices has been quite strong, and so, the industry has had to bring on capacity to support this need, both in terms of needed capacity and technology. Even with the slower market growth in 2008, recent industry data shows healthy levels of fab capacity utilization, especially for the advanced technology generations and for 300mm manufacturing.

He added: "The expectation is that demand for semiconductors will strengthen once global economic conditions improve. So, the capacity addition that is coming online this year and the fab projects that are equipping and beginning construction in 2009 are necessary to meet the future demand."

So how will all of this affect the overall memory market (e.g., 42pc increase in share for memory)? Dieseldorff shared his thought, a fact, known well to those in the semiconductor industry, that the memory market has been battered by declining average selling prices and a condition termed by some as "profitless prosperity."

"Looking at demand forecasts specific to memory, tremendous growth is anticipated," he forecasted.

However, the manufacturers in this device segment are battling it out for market share, and the general expectation is that consolidation will continue.

Also, joint-ventures and partnerships are becoming increasingly critical in the memory sector as manufacturers seek to leverage their existing resources to meet future technology and capacity requirements.

It would be interesting to find out why Taiwan and Korea are forecasted as likely to exceed Japan in fab spend?

According to Dieseldorff, in Korea, Samsung has been and is the key spender, and as a company, it will continue to invest so to have a dominant share in the memory sector.

He said: "In 2009, our expectation is for the DRAM manufacturers in Taiwan to boost spending after cutting back this year. We expect seven new 300 mm fab lines in Taiwan to come into production over the next two years."

However, spending in Japan has been more measured and is likely to remain so. Toshiba, and its joint-venture partner, Sandisk are the big spenders in Japan, when it comes to new fab capacity. Other Japanese semiconductor manufacturers are more cautious and are focused more on technology spending.

Growth drivers for semiconductor industry

Michael J. Fister, president and CEO, Cadence Design Systems Inc., who was in India for the CDNLive event, delivered a wonderful keynote at the recently held CDNLive. Here's what he had to say!

The semiconductor industry is maturing. Since 2000, the industry’s annual growth rate has experienced extreme highs and lows.

Though the semiconductor industry's revenue growth will be low in 2007, the good news is that growth rates are smoothing out as costly fabs demand consistent production. Wireless communications, computers, and consumer products continue to be the growth drivers for semiconductors. A couple of the semiconductor technology trends driving electronic design and product development are:

* More designs at advanced nodes — Beginning this year, 90nm designs will outnumber those at 130nm. Meanwhile, 65nm is design activity is ramping up and advanced designs are targeting 45nm.

* Growth in transistor count and logic — Not only are transistor counts increasing according to Moore’s Law, those transistors are being used to create more functions -– and therefore more complexity -– on a single chip, not just adding memory to the existing designs.

A related trend is that the amount of chip production outsourced to foundries continues to grow, with many Integrated Device Manufacturers (IDMs) moving to a 'Fab-lite' strategy for advanced nodes. This is happening as design is becoming a greater product differentiation than production.

Note that Fister's reference to Fab-lite is interesting, even though lot of new investments are said to be getting into, and he himself says, "costly fabs demand consistent production." There is another point that should not be overlooked -- the one concerning Qualcomm, a fabless company, making it to the Top 10 semicon companies, for the first time.

Coming back the Cadence CEO, all of these trends create two kinds of challenges for chip design. These are: 1) manufacturability at advanced process nodes like 90nm and below, and 2) increased complexity and scale of chip design of system-on-chip (SoC).

Design solutions today must address these challenges, and increase team productivity and schedule predictability. To accomplish this, Cadence is focused on a holistic approach to the design flow. The Cadence Low-Power Solution and the Encounter Timing System are good examples of this holistic approach addressing the challenges of escalating scale and complexity.

The same holistic approach is shown in Cadence’s approach to manufacturability, which is to integrate design for manufacturability (DFM) into all aspects of the design flow, rather than just apply DFM techniques as a post-design step.