LOS GATOS, USA: Silicon Frontline Technology, Inc. (SFT) announced that its 3D extraction software for post-layout verification, F3D (Fast 3D), has been qualified by TSMC for its 40 nanometer (nm) and 65nm processes as the tool supports TSMC’s new iRCX format to improve parasitic extraction and modeling accuracy, and ensures EDA tool interoperability for high performance chip designs.
Silicon Frontline post-layout verification software produces accuracy and high performance by using rigorous 3D technology to extract parasitics. Users have the option to specify the level of accuracy desired, net by net, at the block level or with regular expressions. With this technology, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
“We are pleased to have the world’s leading foundry, TSMC, qualify our 3D extraction software for post-layout verification of designs targeting its 40 and 65nm processes,” said Yuri Feinberg, CEO. “With our software, TSMC’s customers can achieve required accuracy with full chip capacity and performance.”
“Through the TSMC Open Innovation PlatformTM, TSMC collaborates with multiple EDA suppliers to create and qualify design tools for designs targeting our advanced semiconductor processes,” added Tom Quan, deputy director, Design Service Marketing at TSMC. “Silicon Frontline’s 3D extraction software is one of the first EDA tools that passes our iRCX Qualification Program, and is now ready to be used by our customers.”
Showing posts with label Silicon Frontline Technology. Show all posts
Showing posts with label Silicon Frontline Technology. Show all posts
Friday, July 10, 2009
UMC qualifies Silicon Frontline’s parasitic extraction software for 40/65nm
LOS GATOS, USA: Silicon Frontline Technology Inc. (SFT) announced that its 3D extraction software for post-layout verification, F3D (Fast 3D), has been validated by semiconductor foundry United Microelectronics Corp. for 40 and 65nm processes.
F3D provides field solver accuracy for full-chip design, enabling higher quality extraction and faster post-layout verification closure.
UMC qualified Silicon Frontline’s F3D for post-layout verification because it guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics.
Users can specify the level of accuracy desired, net by net, at the block level or with regular expressions. By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
"Qualifying design tools such as Silicon Frontline’s F3D aids our customers in choosing the software they need to design complex, high performance ICs and to confidently achieve silicon success," said Stephen Fu, IP Development and Design Support director, at UMC. "The combination of F3D technology with our advanced manufacturing processes, gives customers a more predictable and smoother flow to silicon success.”
“We are pleased to have one of the world’s leading foundries, UMC, support our 3D extraction software for post-layout verification of designs targeting its advanced processes,” said Yuri Feinberg, CEO. “With our software, UMC customers can experience Guaranteed Accuracy with full-chip capacity and performance.”
F3D provides field solver accuracy for full-chip design, enabling higher quality extraction and faster post-layout verification closure.
UMC qualified Silicon Frontline’s F3D for post-layout verification because it guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics.
Users can specify the level of accuracy desired, net by net, at the block level or with regular expressions. By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
"Qualifying design tools such as Silicon Frontline’s F3D aids our customers in choosing the software they need to design complex, high performance ICs and to confidently achieve silicon success," said Stephen Fu, IP Development and Design Support director, at UMC. "The combination of F3D technology with our advanced manufacturing processes, gives customers a more predictable and smoother flow to silicon success.”
“We are pleased to have one of the world’s leading foundries, UMC, support our 3D extraction software for post-layout verification of designs targeting its advanced processes,” said Yuri Feinberg, CEO. “With our software, UMC customers can experience Guaranteed Accuracy with full-chip capacity and performance.”
Thursday, May 14, 2009
Silicon Frontline announces post-layout EDA verification software
LOS GATOS, USA: Silicon Frontline Technology Inc. (SFT), a new company founded by Electronic Design Automation (EDA) technologists, announced the company and its first products for post-layout verification: F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures like power devices.
The products incorporate patent-pending 3D technology to deliver a Guaranteed Accurate solution for full-chip, post-layout verification. They work in industry standard flows allowing simpler adoption and quicker closure, with guaranteed accuracy, of the post-layout verification loop.
Silicon Frontline was founded in 2005 by EDA software and post-layout verification experts, Yuri Feinberg, CEO, and Dr. Andrei Tcherniaev, VP Engineering, who previously co-founded NASSDA (acquired by Synopsys in 2005) and were the original developers of HSIM, the EDA industry’s first hierarchical circuit simulator.
“We founded Silicon Frontline with the goal of moving post-layout verification technology to the next level,” said Yuri Feinberg, CEO. “We want EDA users to experience what hasn’t been possible until now—Guaranteed Accuracy.”
“Traditional extraction technology could not model our design with sufficient confidence. With Silicon Frontline’s 3D software, we match simulations to silicon, providing us the shortest and highest confidence path to quality and reliability,” remarked Patrick O’Connor, VP Engineering at Canesta, a developer of 3D image sensors.
Guaranteed Accurate Post-Layout Verification Technology
Silicon Frontline’s post-layout verification software guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics. Users have the option to specify the level of accuracy desired, net by net, at block level or with regular expressions.
By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
Support for Standard and Advanced Nanometer Processes
The Silicon Frontline software has been qualified by major foundries for accuracy, performance, and capacity as well as integration with major physical verification systems. It can be used with today’s mature process technology or advanced process technologies such as 40nm or below.
Advanced Field-Solver Technology, Better Accuracy, Capacity and Performance
Silicon Frontline’s 3D technology eliminates the performance and capacity issues inherent in older Field-Solver technology and accomplishes full-chip extraction with Field-Solver accuracy.
Typical examples of F3D running with Guaranteed Accuracy are a 65nm SOC run in under 10 hours; MOMCaps run in under three minutes, which takes over seven hours with standard Field Solvers; and a 40nm design, where F3D delivered results within 2 percent of silicon, competing tools were up to 30 percent off. These results are not possible with commercial tools available today.
Technology, Users, Target Applications
The technology in Silicon Frontline’s products is a combination of a rigorous 3D extraction method with a highly efficient 3D geometric engine yielding significant performance improvement and handling additional issues such as thickness variation due to CMP, width variation due to optical and other manufacturing effects.
The software generates a fully annotated SPICE netlist with parasitics for use by downstream tools. It is used by CAD, TCAD and post-layout verification engineers.
F3D is ideally suited for sensitive analog and AMS circuits where coupling is a challenge -– ADCs, DACs, circuits with differential signals, MIM/MOMCaps and 3D devices, image sensors, RF and high speed designs and for circuits manufactured at advanced technology nodes, such as 65, 40 and 32nm. R3D target applications include discrete or embedded power devices, where efficiency and reliability are important, as well as designs requiring analysis of large metal interconnects.
The F3D and R3D are available now.
The products incorporate patent-pending 3D technology to deliver a Guaranteed Accurate solution for full-chip, post-layout verification. They work in industry standard flows allowing simpler adoption and quicker closure, with guaranteed accuracy, of the post-layout verification loop.
Silicon Frontline was founded in 2005 by EDA software and post-layout verification experts, Yuri Feinberg, CEO, and Dr. Andrei Tcherniaev, VP Engineering, who previously co-founded NASSDA (acquired by Synopsys in 2005) and were the original developers of HSIM, the EDA industry’s first hierarchical circuit simulator.
“We founded Silicon Frontline with the goal of moving post-layout verification technology to the next level,” said Yuri Feinberg, CEO. “We want EDA users to experience what hasn’t been possible until now—Guaranteed Accuracy.”
“Traditional extraction technology could not model our design with sufficient confidence. With Silicon Frontline’s 3D software, we match simulations to silicon, providing us the shortest and highest confidence path to quality and reliability,” remarked Patrick O’Connor, VP Engineering at Canesta, a developer of 3D image sensors.
Guaranteed Accurate Post-Layout Verification Technology
Silicon Frontline’s post-layout verification software guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics. Users have the option to specify the level of accuracy desired, net by net, at block level or with regular expressions.
By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
Support for Standard and Advanced Nanometer Processes
The Silicon Frontline software has been qualified by major foundries for accuracy, performance, and capacity as well as integration with major physical verification systems. It can be used with today’s mature process technology or advanced process technologies such as 40nm or below.
Advanced Field-Solver Technology, Better Accuracy, Capacity and Performance
Silicon Frontline’s 3D technology eliminates the performance and capacity issues inherent in older Field-Solver technology and accomplishes full-chip extraction with Field-Solver accuracy.
Typical examples of F3D running with Guaranteed Accuracy are a 65nm SOC run in under 10 hours; MOMCaps run in under three minutes, which takes over seven hours with standard Field Solvers; and a 40nm design, where F3D delivered results within 2 percent of silicon, competing tools were up to 30 percent off. These results are not possible with commercial tools available today.
Technology, Users, Target Applications
The technology in Silicon Frontline’s products is a combination of a rigorous 3D extraction method with a highly efficient 3D geometric engine yielding significant performance improvement and handling additional issues such as thickness variation due to CMP, width variation due to optical and other manufacturing effects.
The software generates a fully annotated SPICE netlist with parasitics for use by downstream tools. It is used by CAD, TCAD and post-layout verification engineers.
F3D is ideally suited for sensitive analog and AMS circuits where coupling is a challenge -– ADCs, DACs, circuits with differential signals, MIM/MOMCaps and 3D devices, image sensors, RF and high speed designs and for circuits manufactured at advanced technology nodes, such as 65, 40 and 32nm. R3D target applications include discrete or embedded power devices, where efficiency and reliability are important, as well as designs requiring analysis of large metal interconnects.
The F3D and R3D are available now.
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