SAN JOSE, USA: Altera Corp. announced that, based on quarter-to-date results and a broad improvement in market conditions, the company now expects third quarter sales to be in a range of flat to up 3 percent from the second quarter. Previous guidance had been for sales to decline 1 to 5 percent sequentially.
All market segments, except for the telecom and wireless segment, will be up sequentially in the third quarter. The decline in telecom and wireless is more moderate than previously anticipated as a result of better than forecast demand from OEMs supplying Asian wireless networks.
As previously announced, third quarter results will include approximately $4.5 million in severance costs, with nearly all of these costs being included in third quarter operating expense.
These actions will create approximately $1.0 million in operating expense savings in the third quarter and, when fully implemented, approximately $9 million in annual run rate savings. Including the net effect of this restructuring, Altera now anticipates that third quarter operating expense will be in the range of $126 to $128 million compared with prior guidance of $122 to $126 million.
Design wins for Altera's newly launched 40-nm products continue to be very strong. As anticipated, third quarter sales of 40-nm products are likely to approximate $10 million, more than double second quarter levels.
Showing posts with label 40nm. Show all posts
Showing posts with label 40nm. Show all posts
Wednesday, September 9, 2009
Wednesday, August 26, 2009
Magma's Quartz deployed by NVIDIA as primary design rule checker for 40nm and below
SAN JOSE, USA: Magma Design Automation Inc., a provider of chip design software, announced that its Quartz DRC has been deployed by NVIDIA Corp. as the primary physical verification checker for designs targeted at 40-nanometer (nm) and smaller process nodes.
NVIDIA, which invented the graphics processing unit and continues to lead its development, is using the Magma physical verification tools for applications ranging from custom cell development to full-chip verification. NVIDIA selected Quartz for 40 nm and below after use on multiple 65-nm designs and finding they delivered significantly faster turnaround time than existing physical verification tools.
"We have been using Magma's Quartz physical verification solution in production since we moved to the 65-nm process node, and it has proven to be both accurate and significantly faster than other solutions," said James Chen, VLSI technology manager at NVIDIA. "Through dozens of tapeouts, we've seen that Quartz provides the sign-off accuracy needed via certified runsets provided by our foundry partners. Though design sizes and rule complexity have increased significantly, we've been able to meet aggressive design schedules by leveraging Quartz's linear scalability on standard, low-memory Linux machines."
Quartz DRC and LVS are architected to process integrated circuit (IC) designs of any size, at any technology node, in the least amount of time. Magma's is the first truly scalable physical verification solution, able to provide turnaround time that is up to an order of magnitude faster than existing solutions while using existing compute resources. The Quartz tools are fully compatible with third-party IC implementation flows and can read file formats used by traditional physical verification tools.
"Quartz DRC and LVS have enabled silicon success for a wide range of customers, including those doing the most advanced designs in the world," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. "NVIDIA's decision to deploy Quartz as the primary physical verification design rule checker for 40-nm and smaller process nodes is an endorsement of the software's ability to provide the fastest turnaround-time while using very cost-effective hardware systems."
NVIDIA, which invented the graphics processing unit and continues to lead its development, is using the Magma physical verification tools for applications ranging from custom cell development to full-chip verification. NVIDIA selected Quartz for 40 nm and below after use on multiple 65-nm designs and finding they delivered significantly faster turnaround time than existing physical verification tools.
"We have been using Magma's Quartz physical verification solution in production since we moved to the 65-nm process node, and it has proven to be both accurate and significantly faster than other solutions," said James Chen, VLSI technology manager at NVIDIA. "Through dozens of tapeouts, we've seen that Quartz provides the sign-off accuracy needed via certified runsets provided by our foundry partners. Though design sizes and rule complexity have increased significantly, we've been able to meet aggressive design schedules by leveraging Quartz's linear scalability on standard, low-memory Linux machines."
Quartz DRC and LVS are architected to process integrated circuit (IC) designs of any size, at any technology node, in the least amount of time. Magma's is the first truly scalable physical verification solution, able to provide turnaround time that is up to an order of magnitude faster than existing solutions while using existing compute resources. The Quartz tools are fully compatible with third-party IC implementation flows and can read file formats used by traditional physical verification tools.
"Quartz DRC and LVS have enabled silicon success for a wide range of customers, including those doing the most advanced designs in the world," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. "NVIDIA's decision to deploy Quartz as the primary physical verification design rule checker for 40-nm and smaller process nodes is an endorsement of the software's ability to provide the fastest turnaround-time while using very cost-effective hardware systems."
Thursday, August 13, 2009
Synopsys' HDMI IP solution for 90nm to 40nm process technologies
MOUNTAIN VIEW, USA: Synopsys Inc. today announced the broad availability of silicon-proven High-Definition Multimedia Interface (HDMI) transmitter and receiver digital controllers and PHY IP solutions as part of Synopsys' DesignWare IP portfolio.
Synopsys' DesignWare IP for the HDMI interface is compliant to the standard specification and supports High-bandwidth Digital Content Protection (HDCP). Synopsys also provides a roadmap for HDMI 1.4 with product availability anticipated at the end of 2009.
The IP is available in leading process technologies from 90-nm down to 40-nm, and includes sample software drivers for system development. Synopsys' HDMI IP solution is differentiated in terms of feature set, available process nodes and worldwide technical support.
The DesignWare HDMI IP offering includes a comprehensive set of IP deliverables that helps designers quickly embed this complex interface into next generation multimedia SoCs with less risk. Furthermore, the DesignWare HDMI IP solution provides differentiated features including:
* Superior analog front end to support longer HDMI cables, while maintaining high performance.
* Configurable RTL allow designers to optimize gate count and power consumption by choosing only the features required in their application.
* Built-in (on-die) termination resistors for lower bill-of-materials.
* Numerous optional features as well as a choice of various video and audio interfaces for ease of integration.
"HDMI is one of fastest growing multimedia interfaces and is gaining wide-spread acceptance as the standard for communicating between high-performance digital devices," said Paul O'Donovan, principal analyst at Gartner.
"Our research indicates exponential growth in the number of HDMI ports for mobile/portable markets such as camcorders and cameras. HDMI IP will play a key role in enabling designers to integrate the HDMI interface in their next-generation systems."
"Valens continues to develop next generation products for the high definition home entertainment market, and we chose Synopsys to provide us with a high-quality, compliant HDMI IP solution that would help us quickly implement the latest functionality into our advanced SoCs," said Massad Eyal, vice president of research and development R&D at Valens Semiconductor.
"Synopsys' silicon-proven DesignWare HDMI IP enables us to deliver compelling products to the market faster and with significantly less risk."
"HDMI has emerged as the de-facto multimedia interface standard for high-definition consumer electronics and mobile devices," said John Koeter, vice president of marketing for the Solutions Group.
"With Synopsys' extensive customer base, established sales and support infrastructure, and vast porting capabilities, designers can turn to a trusted HDMI IP solution that can be integrated into their SoC with less risk and improved time-to-market."
The DesignWare HDMI 1.3 Transmit and Receive Controllers and PHY IP are available now in leading 90-nm, 65-nm, 45-nm, and 40-nm process technologies. The DesignWare HDMI 1.4 IP solution is currently in development and anticipated to be available at the end of 2009.
Synopsys' DesignWare IP for the HDMI interface is compliant to the standard specification and supports High-bandwidth Digital Content Protection (HDCP). Synopsys also provides a roadmap for HDMI 1.4 with product availability anticipated at the end of 2009.
The IP is available in leading process technologies from 90-nm down to 40-nm, and includes sample software drivers for system development. Synopsys' HDMI IP solution is differentiated in terms of feature set, available process nodes and worldwide technical support.
The DesignWare HDMI IP offering includes a comprehensive set of IP deliverables that helps designers quickly embed this complex interface into next generation multimedia SoCs with less risk. Furthermore, the DesignWare HDMI IP solution provides differentiated features including:
* Superior analog front end to support longer HDMI cables, while maintaining high performance.
* Configurable RTL allow designers to optimize gate count and power consumption by choosing only the features required in their application.
* Built-in (on-die) termination resistors for lower bill-of-materials.
* Numerous optional features as well as a choice of various video and audio interfaces for ease of integration.
"HDMI is one of fastest growing multimedia interfaces and is gaining wide-spread acceptance as the standard for communicating between high-performance digital devices," said Paul O'Donovan, principal analyst at Gartner.
"Our research indicates exponential growth in the number of HDMI ports for mobile/portable markets such as camcorders and cameras. HDMI IP will play a key role in enabling designers to integrate the HDMI interface in their next-generation systems."
"Valens continues to develop next generation products for the high definition home entertainment market, and we chose Synopsys to provide us with a high-quality, compliant HDMI IP solution that would help us quickly implement the latest functionality into our advanced SoCs," said Massad Eyal, vice president of research and development R&D at Valens Semiconductor.
"Synopsys' silicon-proven DesignWare HDMI IP enables us to deliver compelling products to the market faster and with significantly less risk."
"HDMI has emerged as the de-facto multimedia interface standard for high-definition consumer electronics and mobile devices," said John Koeter, vice president of marketing for the Solutions Group.
"With Synopsys' extensive customer base, established sales and support infrastructure, and vast porting capabilities, designers can turn to a trusted HDMI IP solution that can be integrated into their SoC with less risk and improved time-to-market."
The DesignWare HDMI 1.3 Transmit and Receive Controllers and PHY IP are available now in leading 90-nm, 65-nm, 45-nm, and 40-nm process technologies. The DesignWare HDMI 1.4 IP solution is currently in development and anticipated to be available at the end of 2009.
Tuesday, July 28, 2009
Altera 40-nm Arria II GX FPGAs achieve PCI-SIG compliance for PCIe Express 2.0
SAN JOSE, USA: Altera Corp. today announced that its 40-nm Arria II GX FPGAs are compliant with the PCI Express (PCIe) 2.0 specification.
The device successfully passed the PCI-SIG® Compliance and Interoperability Tests at the PCI-SIG Workshop and is now included on the PCI-SIG Integrators List. Arria II GX FPGAs achieved compliance for up to x8 lane configurations for PCIe Gen1 end-point applications.
Currently shipping, Altera's mid-range Arria II GX FPGAs feature integrated transceivers with data rates up to 3.75 Gbps, and have a hard, configurable PCIe interface embedded within the device.
The device's hard IP block implements PCIe Gen1 (PIPE) PHY-MAC, data link, and transaction layers. This IP block is highly configurable to meet the requirements to support end-point and root-port applications, and is PCIe 2.0 compliant in x1-, x4- and x8-lane configurations.
"Arria II GX FPGAs are the only mid-range FPGAs that have attained PCIe 2.0 compliance," said Luanne Schirrmeister, senior director of component product marketing at Altera. "They offer 25 percent higher performance, up to 50 percent lower price and up to 50 percent lower power compared to competitive FPGAs."
Arria II GX FPGAs are targeted for applications using mainstream protocols such as PCIe and Gigabit Ethernet (GbE). The devices have up to sixteen 3.75-Gbps transceivers, 256K logic elements (LEs) and 8.5 Mbits of internal RAM.
The Arria II GX EP2AGX125 device is currently available.
The device successfully passed the PCI-SIG® Compliance and Interoperability Tests at the PCI-SIG Workshop and is now included on the PCI-SIG Integrators List. Arria II GX FPGAs achieved compliance for up to x8 lane configurations for PCIe Gen1 end-point applications.
Currently shipping, Altera's mid-range Arria II GX FPGAs feature integrated transceivers with data rates up to 3.75 Gbps, and have a hard, configurable PCIe interface embedded within the device.
The device's hard IP block implements PCIe Gen1 (PIPE) PHY-MAC, data link, and transaction layers. This IP block is highly configurable to meet the requirements to support end-point and root-port applications, and is PCIe 2.0 compliant in x1-, x4- and x8-lane configurations.
"Arria II GX FPGAs are the only mid-range FPGAs that have attained PCIe 2.0 compliance," said Luanne Schirrmeister, senior director of component product marketing at Altera. "They offer 25 percent higher performance, up to 50 percent lower price and up to 50 percent lower power compared to competitive FPGAs."
Arria II GX FPGAs are targeted for applications using mainstream protocols such as PCIe and Gigabit Ethernet (GbE). The devices have up to sixteen 3.75-Gbps transceivers, 256K logic elements (LEs) and 8.5 Mbits of internal RAM.
The Arria II GX EP2AGX125 device is currently available.
Tuesday, July 21, 2009
Samsung begins mass producing 2Gb DDR3 using 40nm class technology
SEOUL, SOUTH KOREA: Samsung Electronics Co. Ltd. has begun mass producing the industry’s first two gigabit (Gb) DDR3 devices using 40nm class process technology.
“We see market adoption to DDR3 picking up steam and are accommodating that with early entry of 2Gb DDR3 using the most efficient DRAM manufacturing technology available today,” said Jim Elliott, Vice President, Memory Marketing, Samsung Semiconductor Inc. “This will set the pace for a new standard in premium, eco-friendly DRAM solutions offering the most advanced, low power RDIMM for servers anywhere.”
Samsung’s seven-month window between new process technology development and mass production of the new DDR3 (Jan. to Jul. ‘09) will allow OEMs to optimize their next-generation systems more quickly.
In addition, moving to a 40nm production process will provide around a 60 percent increase in production productivity over use of a 50 nm process.
Besides 16GB, 8GB and 4GB RDIMMs for servers, Samsung will produce UDIMMs (unregistered in-line memory modules) for workstations or desktop PCs or SODIMMs (small outline dual in-line memory modules) for notebook PCs of up to 4GBs, using the new chip.
The monolithic 2Gb chips are energy-efficient solutions for high-density, high-performance memory applications. Each supports a data rate of up to 1.6 gigabits per second (Gbps) at 1.35 volts, up to twice as fast as an 800Mbps 1Gb-based dual-die package.
According to market research firm iSuppli, 2 Gb DDR3 is expected to account for 82 percent of the total DDR3 DRAM market in units sold by 2012, and become the mainstream DDR3 DRAM product by 2010.
“We see market adoption to DDR3 picking up steam and are accommodating that with early entry of 2Gb DDR3 using the most efficient DRAM manufacturing technology available today,” said Jim Elliott, Vice President, Memory Marketing, Samsung Semiconductor Inc. “This will set the pace for a new standard in premium, eco-friendly DRAM solutions offering the most advanced, low power RDIMM for servers anywhere.”
Samsung’s seven-month window between new process technology development and mass production of the new DDR3 (Jan. to Jul. ‘09) will allow OEMs to optimize their next-generation systems more quickly.
In addition, moving to a 40nm production process will provide around a 60 percent increase in production productivity over use of a 50 nm process.
Besides 16GB, 8GB and 4GB RDIMMs for servers, Samsung will produce UDIMMs (unregistered in-line memory modules) for workstations or desktop PCs or SODIMMs (small outline dual in-line memory modules) for notebook PCs of up to 4GBs, using the new chip.
The monolithic 2Gb chips are energy-efficient solutions for high-density, high-performance memory applications. Each supports a data rate of up to 1.6 gigabits per second (Gbps) at 1.35 volts, up to twice as fast as an 800Mbps 1Gb-based dual-die package.
According to market research firm iSuppli, 2 Gb DDR3 is expected to account for 82 percent of the total DDR3 DRAM market in units sold by 2012, and become the mainstream DDR3 DRAM product by 2010.
Thursday, July 16, 2009
Magma's Talus-based RTL-to-GDSII low-power reference flow for UMC's 40nm process
SAN JOSE, USA: Magma Design Automation Inc. announced the availability of an integrated low-power IC implementation reference flow for UMC's advanced 40-nanometer (nm) process.
This reference flow supports the UMC 40-nm process and the UMC 40-nm low-leakage library. Based on the Magma Talus IC implementation system and fully compliant with the Unified Power Format (UPF), it allows designers to address low-power nanometer design considerations during implementation and within a single environment, maximizing quality of results (QoR) while reducing turnaround time. Similar low-power reference flows for 90- and 65-nm processes are already available from Magma.
"UMC and Magma's long-standing partnership has resulted in many productive design support solutions for our customers," said Stephen Fu, director of the IP Development and Design Support Division at UMC. "Our latest effort is an integrated low-power IC implementation reference flow that gives designers a means to address low-power issues during the implementation phase of 40-nm designs."
"Our goal in working with UMC was to give project teams a way to address low-power nanometer design considerations with an integrated low-power IC implementation reference flow," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "The Talus platform's unique integration accomplishes that goal while reducing overall turnaround time."
Magma-UMC low-power reference flow
The Magma-UMC RTL-to-GDSII low-power reference flow includes the required scripts and documentation for Magma users to move to UMC's advanced 40-nm low-power process technology and offers timing closure without iterations to enable quick silicon delivery.
A multiple-power domain is used to create different voltage domains with designated purposes, including reducing leakage current and reducing chip power consumption while meeting timing requirements. The reference flow provides MTCMOS power switch insertion and placement for implementing a switched domain.
It performs automatic checking and insertion of level shifters and isolation cells into the right locations in a domain, insertion of retention flip-flops in the domain that can be powered down, and always-on buffering for retention of the control signal in the switched domain.
In addition, Magma's placement engines complete all the standard-cell placement in the design using features such as comprehensive congestion analysis and timing-driven placement.
Magma's clock tree synthesis constructs a minimum-skew clock tree. With the GUI clock-tree browser, users can monitor the clock tree implementation during the flow and can select the correct clock tree structures for their design. After clock tree synthesis is completed, Magma's advanced routing engines complete the routing, including signal and power routing, based on UMC's 40-nm design rules.
Magma's integrated IC implementation solution and unified data structure as the basis for the reference flow ensures better quality results for timing, area, power, signal integrity and reliability while minimizing the design cycle.
The reference flow is available from Magma now at no cost to Magma customers.
This reference flow supports the UMC 40-nm process and the UMC 40-nm low-leakage library. Based on the Magma Talus IC implementation system and fully compliant with the Unified Power Format (UPF), it allows designers to address low-power nanometer design considerations during implementation and within a single environment, maximizing quality of results (QoR) while reducing turnaround time. Similar low-power reference flows for 90- and 65-nm processes are already available from Magma.
"UMC and Magma's long-standing partnership has resulted in many productive design support solutions for our customers," said Stephen Fu, director of the IP Development and Design Support Division at UMC. "Our latest effort is an integrated low-power IC implementation reference flow that gives designers a means to address low-power issues during the implementation phase of 40-nm designs."
"Our goal in working with UMC was to give project teams a way to address low-power nanometer design considerations with an integrated low-power IC implementation reference flow," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "The Talus platform's unique integration accomplishes that goal while reducing overall turnaround time."
Magma-UMC low-power reference flow
The Magma-UMC RTL-to-GDSII low-power reference flow includes the required scripts and documentation for Magma users to move to UMC's advanced 40-nm low-power process technology and offers timing closure without iterations to enable quick silicon delivery.
A multiple-power domain is used to create different voltage domains with designated purposes, including reducing leakage current and reducing chip power consumption while meeting timing requirements. The reference flow provides MTCMOS power switch insertion and placement for implementing a switched domain.
It performs automatic checking and insertion of level shifters and isolation cells into the right locations in a domain, insertion of retention flip-flops in the domain that can be powered down, and always-on buffering for retention of the control signal in the switched domain.
In addition, Magma's placement engines complete all the standard-cell placement in the design using features such as comprehensive congestion analysis and timing-driven placement.
Magma's clock tree synthesis constructs a minimum-skew clock tree. With the GUI clock-tree browser, users can monitor the clock tree implementation during the flow and can select the correct clock tree structures for their design. After clock tree synthesis is completed, Magma's advanced routing engines complete the routing, including signal and power routing, based on UMC's 40-nm design rules.
Magma's integrated IC implementation solution and unified data structure as the basis for the reference flow ensures better quality results for timing, area, power, signal integrity and reliability while minimizing the design cycle.
The reference flow is available from Magma now at no cost to Magma customers.
Friday, July 10, 2009
Silicon Frontline software qualifies for TSMC’s iRCX format for 40/65nm
LOS GATOS, USA: Silicon Frontline Technology, Inc. (SFT) announced that its 3D extraction software for post-layout verification, F3D (Fast 3D), has been qualified by TSMC for its 40 nanometer (nm) and 65nm processes as the tool supports TSMC’s new iRCX format to improve parasitic extraction and modeling accuracy, and ensures EDA tool interoperability for high performance chip designs.
Silicon Frontline post-layout verification software produces accuracy and high performance by using rigorous 3D technology to extract parasitics. Users have the option to specify the level of accuracy desired, net by net, at the block level or with regular expressions. With this technology, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
“We are pleased to have the world’s leading foundry, TSMC, qualify our 3D extraction software for post-layout verification of designs targeting its 40 and 65nm processes,” said Yuri Feinberg, CEO. “With our software, TSMC’s customers can achieve required accuracy with full chip capacity and performance.”
“Through the TSMC Open Innovation PlatformTM, TSMC collaborates with multiple EDA suppliers to create and qualify design tools for designs targeting our advanced semiconductor processes,” added Tom Quan, deputy director, Design Service Marketing at TSMC. “Silicon Frontline’s 3D extraction software is one of the first EDA tools that passes our iRCX Qualification Program, and is now ready to be used by our customers.”
Silicon Frontline post-layout verification software produces accuracy and high performance by using rigorous 3D technology to extract parasitics. Users have the option to specify the level of accuracy desired, net by net, at the block level or with regular expressions. With this technology, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
“We are pleased to have the world’s leading foundry, TSMC, qualify our 3D extraction software for post-layout verification of designs targeting its 40 and 65nm processes,” said Yuri Feinberg, CEO. “With our software, TSMC’s customers can achieve required accuracy with full chip capacity and performance.”
“Through the TSMC Open Innovation PlatformTM, TSMC collaborates with multiple EDA suppliers to create and qualify design tools for designs targeting our advanced semiconductor processes,” added Tom Quan, deputy director, Design Service Marketing at TSMC. “Silicon Frontline’s 3D extraction software is one of the first EDA tools that passes our iRCX Qualification Program, and is now ready to be used by our customers.”
UMC qualifies Silicon Frontline’s parasitic extraction software for 40/65nm
LOS GATOS, USA: Silicon Frontline Technology Inc. (SFT) announced that its 3D extraction software for post-layout verification, F3D (Fast 3D), has been validated by semiconductor foundry United Microelectronics Corp. for 40 and 65nm processes.
F3D provides field solver accuracy for full-chip design, enabling higher quality extraction and faster post-layout verification closure.
UMC qualified Silicon Frontline’s F3D for post-layout verification because it guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics.
Users can specify the level of accuracy desired, net by net, at the block level or with regular expressions. By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
"Qualifying design tools such as Silicon Frontline’s F3D aids our customers in choosing the software they need to design complex, high performance ICs and to confidently achieve silicon success," said Stephen Fu, IP Development and Design Support director, at UMC. "The combination of F3D technology with our advanced manufacturing processes, gives customers a more predictable and smoother flow to silicon success.”
“We are pleased to have one of the world’s leading foundries, UMC, support our 3D extraction software for post-layout verification of designs targeting its advanced processes,” said Yuri Feinberg, CEO. “With our software, UMC customers can experience Guaranteed Accuracy with full-chip capacity and performance.”
F3D provides field solver accuracy for full-chip design, enabling higher quality extraction and faster post-layout verification closure.
UMC qualified Silicon Frontline’s F3D for post-layout verification because it guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics.
Users can specify the level of accuracy desired, net by net, at the block level or with regular expressions. By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
"Qualifying design tools such as Silicon Frontline’s F3D aids our customers in choosing the software they need to design complex, high performance ICs and to confidently achieve silicon success," said Stephen Fu, IP Development and Design Support director, at UMC. "The combination of F3D technology with our advanced manufacturing processes, gives customers a more predictable and smoother flow to silicon success.”
“We are pleased to have one of the world’s leading foundries, UMC, support our 3D extraction software for post-layout verification of designs targeting its advanced processes,” said Yuri Feinberg, CEO. “With our software, UMC customers can experience Guaranteed Accuracy with full-chip capacity and performance.”
Wednesday, July 1, 2009
Virage Logic sees strong adoption of 40nm IP product portfolio
FREMONT, USA: Virage Logic Corp. announced that since being named TSMC’s 40nm early development partner in 2007, the company has seen strong adoption of its extensive 40nm product portfolio.
Comprising embedded SRAMS, embedded memory test and repair, logic libraries, and memory development software, the Company’s silicon-proven 40nm product offering has been designed to optimize area, performance, power and yield.
Today, more than 10 customers rely on Virage Logic’s 40nm product portfolio to design more efficient chips more quickly and with less risk as they develop products for such end markets as graphics, consumer, enterprise, networking, wireless, and handheld.
“Virage Logic has a long, proven track record of being first-to-market at the advanced process technologies and with our extensive 40nm product portfolio, we are proud to offer our customers a competitive advantage at this advanced process node,” said Brani Buric, Virage Logic’s executive vice president, marketing and sales.
“Our SiWare Memory and SiWare Logic products provide designers with a comprehensive dashboard of options for the flexibility needed to efficiently manage design tradeoffs and meet customers’ specific requirements. For example, this dashboard enables our customers to achieve up to a 90% power savings in 40nm G and LP process nodes.
“Our STAR Memory System embedded test and repair offering extends the value we can deliver by enabling customers to dramatically ramp to volume at advanced nodes such as 40nm,” he said. “Finally, our product portfolio is supported by a range of engagement models to best meet the requirements of our fabless, integrated device manufacturer (IDM) and foundry customers.”
“TSMC selected Virage Logic as an early development partner at 40nm as a continuation of our collaboration in technologies ranging from 250nm to 40nm. Virage Logic and TSMC work closely to qualify IP through both Virage Logic’s procedures and TSMC’s procedures including silicon validation of these advanced technology IP solutions,” said Dan Kochpatcharin, deputy director, IP Portfolio Marketing at TSMC.
“These extensive silicon quality report results are available to designers of advanced SoCs for review when choosing Virage Logic’s broad IP portfolio on TSMC’s 40nm process.”
Comprising embedded SRAMS, embedded memory test and repair, logic libraries, and memory development software, the Company’s silicon-proven 40nm product offering has been designed to optimize area, performance, power and yield.
Today, more than 10 customers rely on Virage Logic’s 40nm product portfolio to design more efficient chips more quickly and with less risk as they develop products for such end markets as graphics, consumer, enterprise, networking, wireless, and handheld.
“Virage Logic has a long, proven track record of being first-to-market at the advanced process technologies and with our extensive 40nm product portfolio, we are proud to offer our customers a competitive advantage at this advanced process node,” said Brani Buric, Virage Logic’s executive vice president, marketing and sales.
“Our SiWare Memory and SiWare Logic products provide designers with a comprehensive dashboard of options for the flexibility needed to efficiently manage design tradeoffs and meet customers’ specific requirements. For example, this dashboard enables our customers to achieve up to a 90% power savings in 40nm G and LP process nodes.
“Our STAR Memory System embedded test and repair offering extends the value we can deliver by enabling customers to dramatically ramp to volume at advanced nodes such as 40nm,” he said. “Finally, our product portfolio is supported by a range of engagement models to best meet the requirements of our fabless, integrated device manufacturer (IDM) and foundry customers.”
“TSMC selected Virage Logic as an early development partner at 40nm as a continuation of our collaboration in technologies ranging from 250nm to 40nm. Virage Logic and TSMC work closely to qualify IP through both Virage Logic’s procedures and TSMC’s procedures including silicon validation of these advanced technology IP solutions,” said Dan Kochpatcharin, deputy director, IP Portfolio Marketing at TSMC.
“These extensive silicon quality report results are available to designers of advanced SoCs for review when choosing Virage Logic’s broad IP portfolio on TSMC’s 40nm process.”
Monday, June 29, 2009
Aquantia deploys Synopsys IC Validator and IC Compiler for 40nm quad 10GBASE-T design
MOUNTAIN VIEW, USA: Synopsys Inc. today announced that Aquantia, an innovator in 10GBASE-T networking, has deployed Synopsys' recently announced IC Validator, the newest addition to the Galaxy Implementation Platform, into production use at 40nm.
IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow.
Compared to the typical implement-then-verify flow, the In-Design flow is instrumental in avoiding late-stage surprises and enabling integrated circuit (IC) providers like Aquantia - which is in the process of delivering an advanced 40nm-based quad 10GBASE-T solution - to achieve a faster, robust hand-off to the foundry.
"A few weeks can mean the difference between meeting or missing the market window in our fast moving market," said Ramin Shirani, vice president of engineering at Aquantia.
"IC Validator's ability to perform In-Design physical verification within IC Compiler reduces the physical verification effort from weeks to days by automating and accelerating one of the most onerous parts of our design cycle. We were impressed by IC Validator's fast convergence in concurrently implementing signoff metal-fill and DRC while reducing the timing impact of such implementation."
Prevailing physical verification flows are predominantly post-processing oriented, relying on modifications to the design after GDSII has been generated. These flows can lead to suboptimal results and can induce multiple discover-then-fix iterations.
Metal-fill insertion, a mandatory manufacturability step at the advanced nodes, exemplifies this issue. Physical designers stream out the timing-closed, post-fill design for signoff validation and then stream it back in to fix any signoff errors flagged during physical verification. This time-intensive discover-then-fix loop is typically repeated on each block until the post-fill design is both signoff qualified and timing clean.
With In-Design physical verification, IC Validator and IC Compiler address the manufacturability issues within the place and route environment. The seamless integration enables an optimal metal-fill flow that is timing aware, signoff quality and void of expensive stream-outs and stream-ins. Additionally, this flow achieves higher density by utilizing a track-less approach.
While In-Design physical verification is enabled through tight integration with place and route, it is founded on a high-performance, foundry-endorsed, signoff-accurate engine in IC Validator. With a native multicore architecture, IC Validator can significantly accelerate the metal-fill process by up to 20 times.
For incremental fixes to metal fill near critical nets or ECOs, the In-Design flow enables rule-based, layer-based and area-based metal fill removal and re-insertion, thereby helping eliminate the need for costly full-chip runs.
"In-Design physical verification with IC Validator and IC Compiler is successfully addressing the increasing design-for-manufacturability needs of our customer base," said Saleem Haider, senior director of marketing, physical design and DFM at Synopsys.
"For meeting foundry-dictated manufacturing needs, Aquantia's adoption of IC Validator demonstrates the value of placing the emphasis on the 'D'in DFM and handling manufacturability requirements during design instead of post-design modifications."
IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow.
Compared to the typical implement-then-verify flow, the In-Design flow is instrumental in avoiding late-stage surprises and enabling integrated circuit (IC) providers like Aquantia - which is in the process of delivering an advanced 40nm-based quad 10GBASE-T solution - to achieve a faster, robust hand-off to the foundry.
"A few weeks can mean the difference between meeting or missing the market window in our fast moving market," said Ramin Shirani, vice president of engineering at Aquantia.
"IC Validator's ability to perform In-Design physical verification within IC Compiler reduces the physical verification effort from weeks to days by automating and accelerating one of the most onerous parts of our design cycle. We were impressed by IC Validator's fast convergence in concurrently implementing signoff metal-fill and DRC while reducing the timing impact of such implementation."
Prevailing physical verification flows are predominantly post-processing oriented, relying on modifications to the design after GDSII has been generated. These flows can lead to suboptimal results and can induce multiple discover-then-fix iterations.
Metal-fill insertion, a mandatory manufacturability step at the advanced nodes, exemplifies this issue. Physical designers stream out the timing-closed, post-fill design for signoff validation and then stream it back in to fix any signoff errors flagged during physical verification. This time-intensive discover-then-fix loop is typically repeated on each block until the post-fill design is both signoff qualified and timing clean.
With In-Design physical verification, IC Validator and IC Compiler address the manufacturability issues within the place and route environment. The seamless integration enables an optimal metal-fill flow that is timing aware, signoff quality and void of expensive stream-outs and stream-ins. Additionally, this flow achieves higher density by utilizing a track-less approach.
While In-Design physical verification is enabled through tight integration with place and route, it is founded on a high-performance, foundry-endorsed, signoff-accurate engine in IC Validator. With a native multicore architecture, IC Validator can significantly accelerate the metal-fill process by up to 20 times.
For incremental fixes to metal fill near critical nets or ECOs, the In-Design flow enables rule-based, layer-based and area-based metal fill removal and re-insertion, thereby helping eliminate the need for costly full-chip runs.
"In-Design physical verification with IC Validator and IC Compiler is successfully addressing the increasing design-for-manufacturability needs of our customer base," said Saleem Haider, senior director of marketing, physical design and DFM at Synopsys.
"For meeting foundry-dictated manufacturing needs, Aquantia's adoption of IC Validator demonstrates the value of placing the emphasis on the 'D'in DFM and handling manufacturability requirements during design instead of post-design modifications."
Friday, June 26, 2009
LSI delivers 40nm read channel to HDD manufacturers
BANGALORE, INDIA: LSI Corp. today announced the TrueStore RC9500, the industry’s first 40nm read channel. Now sampling to hard disk drive (HDD) manufacturers, the RC9500 is designed to support notebook through enterprise HDD form factors and capacity points.
The RC9500’s next-generation low-density parity check (LDPC) iterative decoding technology enables a greater than 10 percent increase in the data storage capacity of HDDs, reduces read channel power consumption and delivers industry-leading performance with data rates exceeding 4.0Gb/s.
"HDD read channel technology is critically important in a disk drive,” said John Rydning, IDC's HDD research director. “Improved read channels made by companies like LSI enable higher capacity disk drives that consume less power. The new LSI read channel, based on 40nm semiconductor process technology and using LDPC iterative decoding technology, will enable HDD OEMs to reach next-generation HDD capacity points."
The RC9500’s next-generation LDPC iterative decoding technology delivers significant improvements in signal-to-noise ratio (SNR), increasing the areal density of stored data. As a result, HDD manufacturers can eliminate the need to implement other costly design changes required to reach the next capacity point. The RC9500 also includes features which are designed to reduce firmware complexity, increase drive yields and lower development costs for HDD makers.
The RC9500 offers energy savings enabled by 40nm process technology and innovative design techniques that provide ultra-low current consumption in sleep mode, which is critical to extending battery life in the notebook market segment. In addition, the lower active power consumption can reduce temperatures, improving drive reliability for desktop and digital video recorder applications, and can translate to significant energy cost savings in data center environments.
“The TrueStore RC9500 is built on a revolutionary new architecture and is part of a total recording system design that includes the LSI preamplifier, customer interconnects, heads and media as part of the complete data path solution,” said Phil Brace, senior vice president and general manager, Storage Peripherals Division, LSI. “No other company can offer the breadth of high-performance storage IC products and systems that LSI delivers.”
Designed for hard disk and tape drive applications, the LSI TrueStore family of ICs include highly integrated high-performance storage SoCs, read channels, preamplifiers, serial PHYs and hard disk drive controller IP. By offering a broad portfolio of integrated SoC solutions, LSI enables its customers to address all segments of the HDD market – from mission-critical enterprise applications and high-capacity desktop PCs to low-power laptops and a variety of consumer electronic devices.
The RC9500’s next-generation low-density parity check (LDPC) iterative decoding technology enables a greater than 10 percent increase in the data storage capacity of HDDs, reduces read channel power consumption and delivers industry-leading performance with data rates exceeding 4.0Gb/s.
"HDD read channel technology is critically important in a disk drive,” said John Rydning, IDC's HDD research director. “Improved read channels made by companies like LSI enable higher capacity disk drives that consume less power. The new LSI read channel, based on 40nm semiconductor process technology and using LDPC iterative decoding technology, will enable HDD OEMs to reach next-generation HDD capacity points."
The RC9500’s next-generation LDPC iterative decoding technology delivers significant improvements in signal-to-noise ratio (SNR), increasing the areal density of stored data. As a result, HDD manufacturers can eliminate the need to implement other costly design changes required to reach the next capacity point. The RC9500 also includes features which are designed to reduce firmware complexity, increase drive yields and lower development costs for HDD makers.
The RC9500 offers energy savings enabled by 40nm process technology and innovative design techniques that provide ultra-low current consumption in sleep mode, which is critical to extending battery life in the notebook market segment. In addition, the lower active power consumption can reduce temperatures, improving drive reliability for desktop and digital video recorder applications, and can translate to significant energy cost savings in data center environments.
“The TrueStore RC9500 is built on a revolutionary new architecture and is part of a total recording system design that includes the LSI preamplifier, customer interconnects, heads and media as part of the complete data path solution,” said Phil Brace, senior vice president and general manager, Storage Peripherals Division, LSI. “No other company can offer the breadth of high-performance storage IC products and systems that LSI delivers.”
Designed for hard disk and tape drive applications, the LSI TrueStore family of ICs include highly integrated high-performance storage SoCs, read channels, preamplifiers, serial PHYs and hard disk drive controller IP. By offering a broad portfolio of integrated SoC solutions, LSI enables its customers to address all segments of the HDD market – from mission-critical enterprise applications and high-capacity desktop PCs to low-power laptops and a variety of consumer electronic devices.
Friday, June 12, 2009
Magma's QuickCap NX certified to support TSMC iRCX format for 40nm
BANGALORE, INDIA: Magma Design Automation Inc. announced that QuickCap NX has been certified to support the parasitic extraction and modeling accuracy requirements of the TSMC iRCX format for ICs targeting 65nm and 40nm processes.
With the consistent data provided by the iRCX format, designers can use Magma QuickCap NX to extract accurate parasitic-capacitance values based on the truest 3D representation of the physical circuit. Accurate capacitance values are critical for calculating many properties of chip performance, including capacitive crosstalk, RC delay time and power consumption.
With QuickCap NX and the iRCX format, designers can more accurately predict IC performance prior to manufacturing, allowing them to either make modifications or proceed with confidence in achieving silicon success.
The TSMC iRCX is an interoperable interconnect modeling data format that ensures the accuracy of resistance/capacitance (RC) extractors, electromigration (EM) tools, power integrity analysis tools and electromagnetic simulators. iRCX is the first of several interoperable EDA interface formats co-developed between TSMC and its design tool partners as part of the TSMC Open Innovation Platform (OIP).
“At the 40nm and 65nm nodes, the ability to generate accurate interconnect models at a high frequency can create a bottleneck in the design flow,” said Tom Quan, deputy director, Design Service Marketing at TSMC. “By working together to qualify QuickCap NX for TSMC iRCX format, TSMC and Magma ensure designers have the most accurate models, breaking design flow bottlenecks and enabling first-pass design success.”
“TSMC has been using QuickCap NX as the standard deviation comparison target for RC extraction tools on special pattern structures and real design samples,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit. “The TSMC qualification of QuickCap NX for the iRCX format provides our mutual customers with further confidence that Magma’s 3D field solver is the industry gold standard for parasitic extraction.”
QuickCap NX: Gold standard in parasitic extraction
QuickCap NX is used by major semiconductor companies as the reference standard for parasitic extraction. It is a highly accurate 3D extractor that precisely models advanced process effects such as optimal proximity correction (OPC), chemical-mechanical polishing (CMP) and trapezoidal wires.
QuickCap NX is proven to closely correlate to exact analytical solutions and silicon measurements, delivering capacitance values that are within 1 percent of silicon measurements.
It provides dial-in accuracy and error-bounds reporting on each net, giving the user complete control and trust in the accuracy of results. Leading foundries have validated QuickCap NX's ability to more closely match silicon measurements. By taking process effects into account, the average difference between QuickCap NX capacitance values and actual silicon measurements has been reduced from 9.79 percent to just 0.11 percent.
QuickCap NX in the Magma flow
QuickCap NX can be used for post-layout analysis in the Magma flow. QuickCap technology is also incorporated into the Talus physical design software system to support highly accurate timing and noise analysis during chip implementation. It is used to compute the highly accurate capacitance rules used within Talus and the Quartz RC sign-off extraction tool.
With the consistent data provided by the iRCX format, designers can use Magma QuickCap NX to extract accurate parasitic-capacitance values based on the truest 3D representation of the physical circuit. Accurate capacitance values are critical for calculating many properties of chip performance, including capacitive crosstalk, RC delay time and power consumption.
With QuickCap NX and the iRCX format, designers can more accurately predict IC performance prior to manufacturing, allowing them to either make modifications or proceed with confidence in achieving silicon success.
The TSMC iRCX is an interoperable interconnect modeling data format that ensures the accuracy of resistance/capacitance (RC) extractors, electromigration (EM) tools, power integrity analysis tools and electromagnetic simulators. iRCX is the first of several interoperable EDA interface formats co-developed between TSMC and its design tool partners as part of the TSMC Open Innovation Platform (OIP).
“At the 40nm and 65nm nodes, the ability to generate accurate interconnect models at a high frequency can create a bottleneck in the design flow,” said Tom Quan, deputy director, Design Service Marketing at TSMC. “By working together to qualify QuickCap NX for TSMC iRCX format, TSMC and Magma ensure designers have the most accurate models, breaking design flow bottlenecks and enabling first-pass design success.”
“TSMC has been using QuickCap NX as the standard deviation comparison target for RC extraction tools on special pattern structures and real design samples,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit. “The TSMC qualification of QuickCap NX for the iRCX format provides our mutual customers with further confidence that Magma’s 3D field solver is the industry gold standard for parasitic extraction.”
QuickCap NX: Gold standard in parasitic extraction
QuickCap NX is used by major semiconductor companies as the reference standard for parasitic extraction. It is a highly accurate 3D extractor that precisely models advanced process effects such as optimal proximity correction (OPC), chemical-mechanical polishing (CMP) and trapezoidal wires.
QuickCap NX is proven to closely correlate to exact analytical solutions and silicon measurements, delivering capacitance values that are within 1 percent of silicon measurements.
It provides dial-in accuracy and error-bounds reporting on each net, giving the user complete control and trust in the accuracy of results. Leading foundries have validated QuickCap NX's ability to more closely match silicon measurements. By taking process effects into account, the average difference between QuickCap NX capacitance values and actual silicon measurements has been reduced from 9.79 percent to just 0.11 percent.
QuickCap NX in the Magma flow
QuickCap NX can be used for post-layout analysis in the Magma flow. QuickCap technology is also incorporated into the Talus physical design software system to support highly accurate timing and noise analysis during chip implementation. It is used to compute the highly accurate capacitance rules used within Talus and the Quartz RC sign-off extraction tool.
Sunday, May 10, 2009
Cadence Encounter system used by Gennum’s Snowbush IP Group
SAN JOSE, USA: Cadence Design Systems Inc. announced that Gennum Corp.'s Snowbush IP Group utilized the Cadence Encounter Digital Implementation System to develop the industry’s first 45-nanometer SuperSpeed USB 3.0 PHY IP core.
Encounter was used for timing closure and layout on the digital portion of the PHY. Introduced in March, the new IP from Gennum’s Snowbush IP Group features an integrated USB 3.0 PHY and controller IP with a 5-gigabit per second (Gb/s) transfer rate in each direction. The Encounter Digital Implementation System helped Gennum’s Snowbush IP design team quickly target the digital portion of the PHY to advanced 45nm and 40nm process technologies at multiple foundries, further expanding its market potential.
“The high-speed timing constraints of the PCS layer of the new USB 3.0 PHY require the highly capable design methodology offered by Encounter,” said John Wilby, director of engineering-PHY, for the Snowbush IP Group at Gennum. “The move from a competitor’s design environment to the Cadence Encounter Digital Implementation System took just three months from installation to first-pass silicon success. Key benefits with Encounter include its native signoff quality timing closure and support for advanced DFM rules in deep submicron technologies. In combination with low-power signoff, we also gained improved productivity, a high quality of silicon and ultimately faster time to market.”
Wilby also noted that the fully integrated Encounter Digital Implementation System allowed Gennum to raise the bar on its design specifications and improve the competitive differentiation of its customizable family of IP cores through improved power savings and chip performance, reduced jitter, and optimized noise immunity.
The Encounter Digital Implementation System is a configurable and extensible high-performance, high-capacity, scalable design solution uniquely delivering flat and hierarchical design closure and signoff analysis, as well as low-power, advanced-node, and mixed-signal design solutions in a single integrated environment. The system also delivers interoperability with package, logic, and custom IC design. Cadence design-for-manufacturing (DFM) technologies are an integral part of the Encounter Digital Implementation System, enabling early identification, analysis and repair of yield-limiting design elements present at advanced nodes.
“Gennum’s Snowbush IP Group has a strong track record of success, and we’re pleased to play an integral role in the development of its latest high-speed family of customizable IP cores,” said Chi-Ping Hsu, senior vice president of implementation research and development at Cadence. “This project was a success on multiple levels, but most notably it demonstrated that a full front-to-back design solution can be installed, ramped and used to deliver state-of-the-art advanced-node, low-power designs in a fraction of the time of previous solutions, with first-pass silicon success, lower risk, and faster time to market as the reward.”
Encounter was used for timing closure and layout on the digital portion of the PHY. Introduced in March, the new IP from Gennum’s Snowbush IP Group features an integrated USB 3.0 PHY and controller IP with a 5-gigabit per second (Gb/s) transfer rate in each direction. The Encounter Digital Implementation System helped Gennum’s Snowbush IP design team quickly target the digital portion of the PHY to advanced 45nm and 40nm process technologies at multiple foundries, further expanding its market potential.
“The high-speed timing constraints of the PCS layer of the new USB 3.0 PHY require the highly capable design methodology offered by Encounter,” said John Wilby, director of engineering-PHY, for the Snowbush IP Group at Gennum. “The move from a competitor’s design environment to the Cadence Encounter Digital Implementation System took just three months from installation to first-pass silicon success. Key benefits with Encounter include its native signoff quality timing closure and support for advanced DFM rules in deep submicron technologies. In combination with low-power signoff, we also gained improved productivity, a high quality of silicon and ultimately faster time to market.”
Wilby also noted that the fully integrated Encounter Digital Implementation System allowed Gennum to raise the bar on its design specifications and improve the competitive differentiation of its customizable family of IP cores through improved power savings and chip performance, reduced jitter, and optimized noise immunity.
The Encounter Digital Implementation System is a configurable and extensible high-performance, high-capacity, scalable design solution uniquely delivering flat and hierarchical design closure and signoff analysis, as well as low-power, advanced-node, and mixed-signal design solutions in a single integrated environment. The system also delivers interoperability with package, logic, and custom IC design. Cadence design-for-manufacturing (DFM) technologies are an integral part of the Encounter Digital Implementation System, enabling early identification, analysis and repair of yield-limiting design elements present at advanced nodes.
“Gennum’s Snowbush IP Group has a strong track record of success, and we’re pleased to play an integral role in the development of its latest high-speed family of customizable IP cores,” said Chi-Ping Hsu, senior vice president of implementation research and development at Cadence. “This project was a success on multiple levels, but most notably it demonstrated that a full front-to-back design solution can be installed, ramped and used to deliver state-of-the-art advanced-node, low-power designs in a fraction of the time of previous solutions, with first-pass silicon success, lower risk, and faster time to market as the reward.”
Sunday, May 3, 2009
Fujitsu, TSMC ally on leading-edge process technology
TOKYO, JAPAN & HSIN-CHU, TAIWAN: Fujitsu Microelectronics Ltd and Taiwan Semiconductor Manufacturing Co. Ltd announced that they will collaborate on leading-edge process technology production for the manufacturing of Fujitsu Microelectronics' products.
Under an agreement between the companies, Fujitsu Microelectronics will expand its 40-nanometer generation logic IC business with production at TSMC's fabs.
The collaborative effort will bring together Fujitsu Microelectronics' IC design technologies, leading edge imaging and communication intellectual property (IP), and high-quality technical support to customers, especially in Japan, with TSMC's foundry-leading process technology and capability. This advanced technology engagement should enable both companies to create new business for themselves and for their prospective customers.
The two companies also announced that they intend to initiate discussions on collaborative development of high-performance process technologies for 28-nanometer and below for Fujitsu Microelectronics' product applications.
"From the aspect of its advanced process technologies and large-scale production capacity, TSMC is the most attractive semiconductor foundry partner," said Haruki Okada, president of Fujitsu Microelectronics. "By continuing to create our advantages in fine-pitch process technologies through this partnership, we can further grow our ASIC and ASSP product businesses."
"Fujitsu Microelectronics is clearly a world-class leader in advanced high-speed and low-power technologies, design engineering, and differentiated IP. Given TSMC's long-standing commitment to Japan's semiconductor market, and our on-going investment and dedication to advanced process technology, our collaboration with Fujitsu Microelectronics represents a new best-in-class solution for many system companies," said Dr. Rick Tsai, president & CEO of TSMC.
Under an agreement between the companies, Fujitsu Microelectronics will expand its 40-nanometer generation logic IC business with production at TSMC's fabs.
The collaborative effort will bring together Fujitsu Microelectronics' IC design technologies, leading edge imaging and communication intellectual property (IP), and high-quality technical support to customers, especially in Japan, with TSMC's foundry-leading process technology and capability. This advanced technology engagement should enable both companies to create new business for themselves and for their prospective customers.
The two companies also announced that they intend to initiate discussions on collaborative development of high-performance process technologies for 28-nanometer and below for Fujitsu Microelectronics' product applications.
"From the aspect of its advanced process technologies and large-scale production capacity, TSMC is the most attractive semiconductor foundry partner," said Haruki Okada, president of Fujitsu Microelectronics. "By continuing to create our advantages in fine-pitch process technologies through this partnership, we can further grow our ASIC and ASSP product businesses."
"Fujitsu Microelectronics is clearly a world-class leader in advanced high-speed and low-power technologies, design engineering, and differentiated IP. Given TSMC's long-standing commitment to Japan's semiconductor market, and our on-going investment and dedication to advanced process technology, our collaboration with Fujitsu Microelectronics represents a new best-in-class solution for many system companies," said Dr. Rick Tsai, president & CEO of TSMC.
Friday, March 6, 2009
Altera Nios II processor gets Wind River Linux support
Wind River recently announced the Wind River Linux support for Altera’s Nios II embedded processor.Commenting on the Nios II processor adoptiion, Mikeson Wang, Product Marketing Manager, Asia Pacific, Altera Corp., in Hong Kong, highlighted that it has over 20,000 licensees worldwide, and is used by each one of the top 20 OEMs. The Nios II processor happens to be the industry’s #1 soft core CPU, as per Gartner Dataquest. There exists a very vibrant Nios Forum community of over 10,000 users. It is also used by developers in all Altera markets.
Wind River delivers Linux support for the Nios II processor also means that the #1 FPGA processor is now supported by best-in-class embedded Linux. Also, Nios II plus embedded Linux = BOM cost reduction.
It is a compelling alternative to discrete off-the-shelf processors. Wind River customers have access to Altera’s full spectrum of FPGA and HardCopy ASIC solutions as well.
Wang added that the Nios II is popular because of providing design flexibility. Being a custom fit solution, it is also easy to modify hardware at any time.
Why Linux + Nios II
There are several reasons. First, it provides cost reduction through integration. Users can replace the existing CPU with an FPGA running Embedded Linux. Next, it provides protection from processor obsolescence. This in turn, protects the software legacy code, which happens to be a customer's biggest investment.
This combination also allows design flexibility. Besides providing access to open source software, the time to market gets reduced as well.
Highlighting the reasons for the Altera-Wind River partnership, he added that Wind River is the best-in-class Linux partner, with worldwide sales, support, training and service infrastructure. Wind River is also the no. 1 embedded OS supplier for the communications market.
Altera itself has a strong presence in the communications market. Also, the FPGA processor use is a growing trend in embedded applications; and Nios II is leading FPGA soft processor. There is also a significant overlap of Altera and Wind River's customer base, such as Huawei, ZTE, Motorola, Alcatel-Lucent, etc., to name a few.
Deliveables include:
Altera
* Cyclone III FPGA Development Kit (3C120)
- DK-DEV-3C120
* Linux Hardware Reference Design (Quartus II Project)
- Current design: 125 MHz in 3C120
- Nios II performance: 150 – 300 DMIPS *
Wind River
* Wind River Linux Distribution
* Wind River Workbench for Nios II
- Workbench IDE with Nios II Support
- GNU Tool Chain, Board Support Package
* Flash files (HW & SW for 3C120 board)
The Cyclone III FPGA development kit is a complete platform for prototyping embedded systems.
In summary, the Wind River-Altera partnership helps reduce system cost and TTM, and increases system flexibility. Altera and Wind River already share several customers, and hence, this is a win-win partnership. The strategic partnership with Wind River complements Altera's silicon, soft processor and FPGA development, besides, Wind River's industry-leading embedded Linux distribution.
How will this partnership boost FPGA sales? According to Wang: "The current weak demand is due to recession. We see weak demand in every segment. However, we are still outperforming the market."
Although leading-edge FPGAs are scaling to 40nm and beyond, have the tools caught up with these new and complex processes? Wang added that the process does not have any significant impact.
Wednesday, August 13, 2008
FPGA vs. ASIC and FPGA trends
This semicon blog is a continuation of the recent discussion I had with Vincent Ratford, Senior Vice President, Solutions Development Group, Xilinx.
FPGAs vs. ASICs
Traditionally, there has always been a classic debate: FPGAs vs. ASICs! To find out more on the current status of this ever going discussion, I asked Ratford for his thoughts on this topic.
He said: "To answer this you have to take a long term view and look forward five years to what a 22nm device might look like and the cost to develop it. ASIC starts have declined over the last five years and continue to decline with ASSPs taking their place. For ASSPs to continue, they have to amortize the development cost across multiple customers, but with $50M development costs climbing to $100M, the number of applications that can support this is shrinking.
"FPGAs now look like SoCs with embedded processors, signal processing, multi-gigabit transceivers and a broad portfolio of IPs available from Xilinx or third parties. With shorter design cycles and increasing need to differentiate or die, we believe the world is increasingly turning to programmable devices.
"The investments we [Xilinx] are making in IP and software to enable more complex systems to be designed will carry our silicon platform forward and enable growth. Our challenges, going forward, are reducing power, providing more capability at a lower cost and simplifying the programming. As we make progress on all these fronts, we will take share from the ASIC/ASSP providers."
Global FPGA industry trends
Given the current semiconductor scenario, there is a need to estimate the global FPGA industry. According to iSuppli, the programmable logic market was $3.6 billion in CY2007. Xilinx revenues were $1.841 billion.
Given the wobble in the current global semicon scenario, where is the FPGA industry headed? Ratford said that Xilinx is forecasting 5-9 percent growth in FY09, which started in April 2008.
He added: "Our most recent quarter ending June was a record quarter for the company at $488 million, with 4 percent sequential growth. Our customers' design cycles are 12-18 months, so that tends to delay any weakness. However, design activity has been and still is strong. Our customers are highly diversified with over 20,000 across all the vertical markets. We see strong growth in ISM, automotive, aerospace and defense, and slow growth in telecommunications, which is our largest market at ~46 percent of sales."
According to him, wireless telecom, which constitutes about 40 percent of Xilinx's telecom revenue, is starting to go through a round of infrastructure buildouts with LTE and TD-SCDMA. This occurs about every five years.
"As these start to deploy, we expect to see some growth beyond what we are currently seeing. Finally, customers do a lot of prototyping with our platforms. We see no significant slowdown at this time," he noted.
Taking on Altera
Altera recently released the Stratix IV FPGA and HardCopy ASICs. It would be interesting to find out whether Xilinx has released anything that is close to or better than the Altera Stratix IV FPGA or the HardCopy ASIC.
Xilinx's Ratford said: "Our Virtex-5 products on 65nm have been shipping for 18 months, growing quickly and gaining market share vs. Stratix-3, which is also on 65nm. Since Altera has had difficulty executing on 65nm as far as Stratix III is concerned, they've had to jump to 45/40nm and recently pre-announced Stratix IV. Altera is saying they will ship first samples by December, however it takes quite some time to ramp to volume on a node and to put in place all the software and IP required.
"Our 45/40nm design has been underway for some time and we'll be in the market with a complete solution at the same time as Altera. What matters is when you ramp to production and when you have critical mass of IP so customers can start designs. We have a much larger IP portolio. Customer design activity on high-end FPGA will remain on 65nm devices for sometime to come. We estimate that Xilinx has about a 97 percent market-share in the high-end with our Virtex-5 family.
Alternative to HardCopy
Apparently, Xilinx also has an alternative to Altera's HardCopy. Ratford pointed to Xilinx's EasyPath, which provides similar cost reduction path for customers.
"Our approach doesn't require design compromises like that of HardCopy. Altera's most recent quarter showed HardCopy revenue down 2 percent to about $10M/quarter. It's insignificant!"
The last part of this discussion continues later this week! Watch this space, dear readers.
FPGAs vs. ASICs
Traditionally, there has always been a classic debate: FPGAs vs. ASICs! To find out more on the current status of this ever going discussion, I asked Ratford for his thoughts on this topic.
He said: "To answer this you have to take a long term view and look forward five years to what a 22nm device might look like and the cost to develop it. ASIC starts have declined over the last five years and continue to decline with ASSPs taking their place. For ASSPs to continue, they have to amortize the development cost across multiple customers, but with $50M development costs climbing to $100M, the number of applications that can support this is shrinking.
"FPGAs now look like SoCs with embedded processors, signal processing, multi-gigabit transceivers and a broad portfolio of IPs available from Xilinx or third parties. With shorter design cycles and increasing need to differentiate or die, we believe the world is increasingly turning to programmable devices.
"The investments we [Xilinx] are making in IP and software to enable more complex systems to be designed will carry our silicon platform forward and enable growth. Our challenges, going forward, are reducing power, providing more capability at a lower cost and simplifying the programming. As we make progress on all these fronts, we will take share from the ASIC/ASSP providers."
Global FPGA industry trends
Given the current semiconductor scenario, there is a need to estimate the global FPGA industry. According to iSuppli, the programmable logic market was $3.6 billion in CY2007. Xilinx revenues were $1.841 billion.
Given the wobble in the current global semicon scenario, where is the FPGA industry headed? Ratford said that Xilinx is forecasting 5-9 percent growth in FY09, which started in April 2008.
He added: "Our most recent quarter ending June was a record quarter for the company at $488 million, with 4 percent sequential growth. Our customers' design cycles are 12-18 months, so that tends to delay any weakness. However, design activity has been and still is strong. Our customers are highly diversified with over 20,000 across all the vertical markets. We see strong growth in ISM, automotive, aerospace and defense, and slow growth in telecommunications, which is our largest market at ~46 percent of sales."
According to him, wireless telecom, which constitutes about 40 percent of Xilinx's telecom revenue, is starting to go through a round of infrastructure buildouts with LTE and TD-SCDMA. This occurs about every five years.
"As these start to deploy, we expect to see some growth beyond what we are currently seeing. Finally, customers do a lot of prototyping with our platforms. We see no significant slowdown at this time," he noted.
Taking on Altera
Altera recently released the Stratix IV FPGA and HardCopy ASICs. It would be interesting to find out whether Xilinx has released anything that is close to or better than the Altera Stratix IV FPGA or the HardCopy ASIC.
Xilinx's Ratford said: "Our Virtex-5 products on 65nm have been shipping for 18 months, growing quickly and gaining market share vs. Stratix-3, which is also on 65nm. Since Altera has had difficulty executing on 65nm as far as Stratix III is concerned, they've had to jump to 45/40nm and recently pre-announced Stratix IV. Altera is saying they will ship first samples by December, however it takes quite some time to ramp to volume on a node and to put in place all the software and IP required.
"Our 45/40nm design has been underway for some time and we'll be in the market with a complete solution at the same time as Altera. What matters is when you ramp to production and when you have critical mass of IP so customers can start designs. We have a much larger IP portolio. Customer design activity on high-end FPGA will remain on 65nm devices for sometime to come. We estimate that Xilinx has about a 97 percent market-share in the high-end with our Virtex-5 family.
Alternative to HardCopy
Apparently, Xilinx also has an alternative to Altera's HardCopy. Ratford pointed to Xilinx's EasyPath, which provides similar cost reduction path for customers.
"Our approach doesn't require design compromises like that of HardCopy. Altera's most recent quarter showed HardCopy revenue down 2 percent to about $10M/quarter. It's insignificant!"
The last part of this discussion continues later this week! Watch this space, dear readers.
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