Altera expands low-cost Cyclone FPGA series

Altera Corp. today introduced the Cyclone IV FPGAs, thereby expanding the success of the low-cost Cyclone series. The Cyclone IV GX is said to be the lowest cost, lowest power FPGAs with transceivers, and the Cyclone IV E has helped it extend the lead in combining low cost, low power, and high functionality. Simultaneously, Altera also extended its transceiver portfolio leadership.

The Cyclone IV FPGA family offers two variants. Cyclone IV GX devices have up to 150K logic elements (LEs), up to 6.5-Mbits of RAM, up to 360 multipliers, and up to eight integrated 3.125-Gbps transceivers supporting mainstream protocols including Gigabit Ethernet (GbE), SDI, CPRI, V-by-One and Cyclone IV GX has hard IP for PCI Express (PCIe).

According to Jennifer Lo, Senior Marketing Manager, Altera, the company is pushing bandwidth limits in cost-sensitive markets and products -- specifically, smartphones, wireless communications, industrial Ethernet, broadcast and 3D displays.

There is said to be a huge demand from Latin America, Asia, etc., specifically in wireless. Altera is providing a low cost, low power solution. Next, the trend is also moving from 2D to 3D displays. In broadcast it is moving to high bandwidth, in order to support HD video.

Product goals to address market requirements
Commenting on the product features, the Cyclone IV FPGA family supports mainstream transceiver protocols and has the core functionality to address targeted applications.

The new FPGA family also facilitates probably the lowest system cost -- in terms of lowest device cost, reduced board and BOM cost, and fastest time to volume production. Also, it meets most strict power budgets with increased functionality.

Focusing on Altera's transceiver portfolio leadership, the company is said to be the only supplier shipping FPGAs with 11.3Gbps transceivers.

The Altera Cyclone IV GX has 3.125Gbps transceivers. The Arria II GX, shipping now, features 3.75 Gbps transceivers, while the HardCopy IV GX and Stratix IV GX feature 8.5Gbps transceivers. The Stratix IV GT features 11.3Gbps transceivers. Lo added that the company needs to make sure that the products supports all latest transceiver protocols.

Cyclone IIV FPGAs
Altera's Cyclone IV FPGAs are currently said to be the lowest cost, lowest power, integrated transceivers.

Lowest system cost
* Smallest density FPGA with transceivers
* Integrated hard IP
-- PCIe x1, x2, x4
-- Transceivers built from ground up for low cost
* Requires only two power supplies
* Wirebond packages

Lowest power
* 60nm low-power process
* PCIe to GbE bridge for <1.5W

High functionality
* Up to 150K logic elements (LEs)
* Up to 6.5-Mbit RAM and 360 multipliers for DSP-intensive applications
* Up to eight integrated 3.125-Gbps transceivers

As an example, when used in consumer video displays, the new family will meet high video-quality requirements fast and cost effectively. When used in a broadcast video capture card, it helps save over 30 percent system cost.

ASSP replacement
Cyclone IV FPGAs provide a cost that rivals ASSPs. It also offers unmatched flexibility to support multiple protocols. Besides, being obsolescence proof, it reduces cost as well. It cal also replace simple bridge ASSPs -- for example, PCI to PCIe, PCIe to GbE, etc. The FPGA family can also replace industrial Ethernet ASICs/ASSPs.

The Cyclone IV FPGAs can be used across all market segments -- wireless, wireline, consumer, industrial, broadcast, and test and medical -- to address cost-sensitive applications. It aims to help designers meet their cost-sensitive product targets for increased bandwidth.

Altera's Stratix IV GX FPGAs move to volume production

BANGALORE, INDIA: Altera Corp. today announced it is shipping volume production of its 40-nm Stratix IV GX EP4SGX230 FPGAs.

The Stratix IV device was the industry's first 40-nm FPGA available when it began shipping at the end of 2008 and it continues to lead the market as the only 40-nm FPGA in volume production.

The Stratix IV family offers the highest density and highest performance FPGAs available today, and is used in a variety of end customer's high-speed backplane and cabling interfaces, chip-to-chip interconnects and protocol-bridging applications.

Stratix IV GX FPGAs deliver an unprecedented combination of power, performance and I/O bandwidth to designers manufacturing multi-gigabit interconnected systems. The high-performance FPGAs feature Altera's latest generation of proven transceiver technology.

The 36 transceivers embedded in the EP4SGX230 FPGA offer superior signal integrity with excellent jitter performance at data rates operating between 600 Mbps and 8.5 Gbps. The transceivers support several key industry standards and serial protocols such as PCI Express Gen1 and Gen2 (x1, x4 and x8), Serial RapidIO, Gigabit Ethernet, XAUI, CPRI (including 6G CPRI), CEI 6G, GPON, SFI-5.1 and Interlaken.

The EP4SGX230 FPGA features 230K logic elements (LEs), 13.9 Mbits of embedded memory and 1,288 18x18 multipliers.

"The significant lead we have on the competition at the 40-nm node has enabled us to establish Stratix IV FPGAs as the most widely adopted 40-nm FPGAs in the industry," said Luanne Schirrmeister, senior director of component product marketing at Altera. "We continue to hit every key milestone in rolling out our 40-nm devices and remain on target to deliver our entire family of Stratix IV FPGAs to customers."

The Stratix IV GX EP4SGX230 FPGA is now shipping in volume production. Engineering samples of Altera Stratix IV E, Stratix IV GX and Stratix IV GT FPGAs are also available today.

Altera remains on schedule to ship its entire Stratix IV FPGA family in volume production by April 2010. Contact your Altera sales representative for pricing.

Xilinx extends next generation serial connectivity portfolio

BANGALORE, INDIA: Xilinx announced design support for Virtex-6 HXT FPGAs with the 11.3 release of the ISE Design Suite software. Optimized for 40G/100G wired telecommunications and data communications, Virtex-6 HXT FPGAs deliver serial interface technology to designers of ultra-high bandwidth systems with line rates in excess of 11 Gigabits per second (Gbps).

The availability of ISE Design Suite 11.3 gives designers access to a portfolio of connectivity-domain FPGAs spanning the complete spectrum of mainstream, high-end, and ultra high-end serial design applications.

Ultra-high bandwidth to nainstream
In addition to design support for Virtex-6 HXT FPGAs, the ISE 11.3 release expands protocol support for Spartan-6 and Virtex-6 LXT FPGAs and Virtex-6 SXT FPGAs.

XGEMAC, XAUI and RXAUI, Tri-mode Ethernet MAC, Ethernet AVB, SPI4.2 and SPI-3 link are just some of the nearly forty protocols supported by Xilinx serial technology today.

Designers now have their choice of connectivity-optimized devices with embedded low-power transceiver options for meeting their SoC (system-on-a-chip) power, reliability, and protocol requirements for a broad range of markets and applications:

* For mainstream applications, Spartan-6 FPGAs with up to eight GTP 3.125Gbps transceivers satisfy the cost, ease-of-use, and low-power needs of high-volume electronics, such as automotive infotainment systems and high-resolution consumer displays.

* For high-end applications, Virtex-6 LXT and SXT FPGAs with up to 36 GTX 6.5Gbps transceivers and performance margins that exceed the demands of high-speed protocols (e.g., Interlaken and PCIe 2.0) are ideal for multi-protocol systems, such as wireless base stations, switches and routers, and professional video equipment.

* For ultra high-end applications, Virtex-6 HXT FPGAs with up to 72 serial I/O channels (48 GTX and 24 11Gbps GTH) transceivers save over 80 percent in transceiver power compared to solutions with external physical layer (PHY) for 40G/100G applications. These include transponders/muxponders, traffic managers, and packet processors for wired communications; high-performance data encryption engines; advanced medical imaging; and digital video production, editing, and broadcast equipment. Xilinx was the first FPGA vendor to offer a single-chip 100G solution for these applications with the introduction of Virtex-5 TXT FPGAs in 2008.

“Digital convergence in nearly all markets is driving the demand for higher bandwidth connectivity between chips, over backplanes, and across networks. At the same time, parallel I/O has reached its limit and serial solutions once relegated to only high-end designs are becoming ubiquitous,” said Mustafa Veziroglu, vice president of product solutions and management for Xilinx.

“These trends create system complexity, performance, and cost issues that can’t be addressed with a one-size-fits-all approach. Our market-driven focus enables designers to develop and deploy serial solutions faster with the right set of resources, performance, and capabilities for their applications.”

Targeted design platforms increase productivity
Xilinx Targeted Design Platforms enable designers to quickly start SoC development, evaluate Xilinx technology, and rapidly adapt targeted reference designs to the specific feature requirements of their systems.

As part of the Xilinx Base Targeted Design Platform, the Spartan-6 FPGA SP601 and Virtex-6 FPGA ML605 Evaluation Kits provide everything needed to evaluate the serial capabilities in Virtex-6 LXT and Spartan-6 LXT FPGA devices.

Xilinx will roll out its Connectivity Targeted Design Platform later this year with complete targeted reference designs for implementing XAUI to PCIe and Gigabit Ethernet to PCIe bridging solutions, including Direct Memory Access (DMA) cores to achieve optimized bandwidth.

As part of this platform, Virtex-6 HXT devices provide the silicon foundation for the Xilinx deployment of ultra high-speed connectivity development kits and market-specific development kits targeting broadcast video and wired connectivity, packet processing, and traffic management applications.

Five generations of serial technology
Virtex-6 HXT FPGAs extend Xilinx serial technology leadership with the new high-speed serial GTH transceiver. This latest innovation in transceiver technology is part of Xilinx’s holistic approach to serial system design that goes beyond silicon to address system-level connectivity requirements.

Xilinx considers use models, ease-of-use, signal and data integrity, IP, and board designs to enable faster deployment of customer solutions, starting from the architecture phase through product rollout.

With five generations of serial design experience and the most advanced 40 and 45-nanometer process technologies, Xilinx is able to provide designers with the right transceiver for the application at hand.

Altera extends leadership with 820K-LE Stratix IV FPGA

SAN JOSE, USA: Altera Corp. has increased the high-end density range of its 40-nm Stratix IV E FPGAs to an industry-leading 820K logic elements (LEs). The Stratix IV EP4SE820 FPGA is the industry's highest density, highest performance and lowest power FPGA in its class.

The EP4SE820 FPGA is ideally suited for a variety of high-end digital applications that require resource-rich FPGAs, including ASIC prototyping and emulation, wireline, wireless, military, and computer and storage applications.

Altera's Stratix IV E FPGAs feature four devices ranging in density from 230K to 820K LEs. The new EP4SE820 delivers 53 percent higher density than Altera's EP4SE530 device and is at least one speed grade faster than the closest competitor's largest offering.

The density, performance and power-saving features in the EP4SE820 FPGA enable customers to simplify their design partitioning, accelerate their verification cycle, and reduce their total system power.

Increasing the number of LEs in Stratix IV E FPGAs to 820K gives ASIC-prototyping designers the ability to implement much larger ASIC designs on a single FPGA, which simplifies board design and minimizes the number of design partitions.

For designers wanting to move their design into an ASIC after FPGA prototyping, Altera offers a low-risk, low-cost migration path to ASIC production with its HardCopy IV ASICs.

Altera updates Q3 guidance

SAN JOSE, USA: Altera Corp. announced that, based on quarter-to-date results and a broad improvement in market conditions, the company now expects third quarter sales to be in a range of flat to up 3 percent from the second quarter. Previous guidance had been for sales to decline 1 to 5 percent sequentially.

All market segments, except for the telecom and wireless segment, will be up sequentially in the third quarter. The decline in telecom and wireless is more moderate than previously anticipated as a result of better than forecast demand from OEMs supplying Asian wireless networks.

As previously announced, third quarter results will include approximately $4.5 million in severance costs, with nearly all of these costs being included in third quarter operating expense.

These actions will create approximately $1.0 million in operating expense savings in the third quarter and, when fully implemented, approximately $9 million in annual run rate savings. Including the net effect of this restructuring, Altera now anticipates that third quarter operating expense will be in the range of $126 to $128 million compared with prior guidance of $122 to $126 million.

Design wins for Altera's newly launched 40-nm products continue to be very strong. As anticipated, third quarter sales of 40-nm products are likely to approximate $10 million, more than double second quarter levels.

ACTEL announces availability of RTAX-DSP prototype FPGAs

HYDERABAD, INDIA: Actel Corp. today announced the availability of RTAX-DSP prototype FPGAs, enabling hardware demonstration and timing validation of designs targeted to Actel’s RTAX-DSP space-flight FPGAs.

The newly available RTAX-DSP prototype devices have the same pin assignment, mechanical footprint and identical timing properties across the full military temperature range (-55°C to 125°C) as their space-qualified counterparts.

RTAX-DSP space-flight FPGAs add embedded radiation-tolerant multiply-accumulate blocks to the tested and proven industry-standard RTAX-S product family.

The result is a dramatic increase in device performance and utilization when implementing arithmetic functions, such as those encountered in hardware DSP algorithms, without sacrificing reliability or radiation tolerance.

“The availability of RTAX-DSP prototype FPGAs enable designers to demonstrate their RTAX-DSP designs in hardware across the full operational temperature range,” said Ken O'Neill, director of high-reliability marketing for Actel.

“With the availability of these prototype devices, the RTAX-DSP program has achieved another important milestone in providing the high performance combined with high reliability needed by designers of signal processing systems for space-flight applications.”

RTAX-DSP features
Providing a flexible alternative to expensive radiation-hardened ASICs, RTAX-DSP FPGAs feature up to 120 multiply-accumulate DSP mathblocks, protected against radiation-induced single event upsets (SEU) and single event transients (SET).

The RTAX-DSP FPGAs use the same 0.15 µm UMC wafer fabrication process and the same antifuse programmable interconnect technology that are used in the industry-standard RTAX-S FPGA family, which is now accumulating space-flight heritage on as many as nine space programs.

RTAX-DSP FPGAs offer high performance at densities of up to four million equivalent system gates and 840 user I/Os for space-based applications. The embedded DSP mathblocks feature 18 bit x 18 bit multiply-accumulate blocks enabling efficient implementation of DSP building blocks, such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and fast Fourier transforms (FFT). Each mathblock is capable of operating at 125 MHz across the full military temperature range.

The RTAX-DSP family of FPGAs is fully supported by the Actel Libero Integrated Design Environment (IDE). From design, synthesis and simulation, through floorplanning, place-and-route, timing constraints and analysis, power analysis and program file generation, Libero IDE manages the entire design flow quickly and efficiently.

TI applies digital power management to next-gen Xilinx FPGA designs

BANGALORE, INDIA: Texas Instruments (TI) announced that Xilinx is using TI power management technology to simplify power design in its new Virtex-6 ML605 FPGA evaluation kit.

TI’s Fusion Digital Power controllers give FPGA users advanced power management capability and design flexibility, including the ability to monitor a power system’s behavior in real time.

“As FPGA designs become increasingly sophisticated, there is a growing need for intelligent power management solutions with accurate current monitoring and control,” said Brent Przybus, Director of platform marketing at Xilinx.

“New developments in digital control technology from Texas Instruments give Virtex-6 FPGA customers a high degree of power system optimization, while accelerating design time with the Xilinx Base Platform.”

TI’s UCD9240 integrated power system controller, along with complementary power stage ICs and plug-in modules, intelligently manage today’s high-density, high-performance power systems, such as those used in telecom and datacom infrastructure applications.

The controller supports up to four independent digital control loops and up to eight phases. Two UCD9240 devices manage the power for the Virtex-6 FPGA ML605 evaluation kit. The kit also includes the INA333, the industry’s lowest power zero-drift instrumentation amplifier. Xilinx’s soon to be released Spartan-6 FPGA SP605 kit also includes TI’s digital power products.

Easy-to-use Fusion Digital Power design tool
The evaluation kit features TI’s digital power design tool with an easy-to-use graphical user interface, which helps designers configure key design parameters, optimize control loop design, and meet specific supply voltage sequencing criteria – with no programming required.

The tool contains real-time monitoring, control loop modeling and impedance measuring features that support Virtex-6 FPGA design requirements.

“A major focus for Xilinx’s new generation of products is reducing power consumption without compromising performance,” said Steve Bakota, manager of TI’s digital power business. “Power measurement and control are important features in Xilinx’s new development boards. Customers using our digital power products can take full advantage of advances this technology delivers.”

Semiconductors and ICs update: Gauging fallout from ITC's Tessera ruling

USA: Presenting Converge's Market Intelligence Report, August 2009.

Overall, the general IC activity has remained relatively flat compared to last month. However, the shortages discussed in last month’s Market Insights report for the Xilinx Virtex 5 product line continue, as do those mentioned from TI, Altera and Freescale.

Activity for ST Micro has increased over the last several weeks, most likely out of concerns regarding the ITC's Tessera ruling. Consumer/telecom demand is still subdued, but demand in the industrial PC and embedded technology sectors are showing some signs of life.

Fallout from the ITC's Tessera ruling has been difficult to gauge, as specific information regarding the judgment has been slow to emerge. Some suppliers have adhered immediately to what they perceive will be the strictest letter of the law, while others have been quick to move inventory to make it available for sale in anticipation of enforcement.

In addition, increased customs enforcement by nations in Asia and Europe have made it much more difficult and time-consuming to move certain products, including FPGAs, from one region to another. Converge is advising our customers to add an additional one to two weeks to lead times on parts originating from these countries.

Altera opens 66th joint lab and training center in China

BEIJING, CHINA: Altera Corp. announced the opening of the new Peking University and Altera International Ltd Joint EDA/SOPC Lab at the Peking University School of Software and Microelectronics (Wuxi), Jiangsu Province, China.

This is the 66th Joint Lab and Training Center (JLTC) that Altera has established with major universities in China. As part of Altera's worldwide University Program, the JLTCs are equipped with the latest Altera Quartus II design software and a set of Altera DE2-70 development kits to aid professors in conducting hands-on training with students.

The university will use the lab for courses in digital logic circuits, HDL language, computer principles, principles of television, and modern digital system design featuring Altera's FPGA development environment. The lab will also be used to help design the electronics curriculum used for graduate and postgraduate studies.

"With the establishment of this joint lab and with the cooperation in teaching, project researching and training, we will be able to take full advantage of the Altera relationship with Peking University,” said Professor Xin Zhang, dean of the school of Software and Microelectronics at Peking University.

“This new lab boosts our universities enterprise cooperation to a new depth, which will enable us to make more contributions to the development of China SOPC."

In conjunction with the opening of the Peking University and Altera International Ltd Joint EDA/SOPC Lab, Altera has invited key professors from the other 65 JLTCs to attend the opening ceremony and participate in a three-day training on Altera products and technology.

"Through our University Program, we cultivate designers and support innovation around the world by working with professors and lecturers to help teach students about digital technology," said Stephen Brown, worldwide director of the University Program for Altera Corporation.

"Universities and students in China are very important for the future of the electronics industry, and we are proud to have a world-leading educational program in China. Altera invests heavily in universities and students worldwide, and has helped to create hundreds of university labs in a number of countries over the past few years."

Embedded processors: Global market demand analysis

DUBLIN, IRELAND: Research and Markets has announced the addition of the "Embedded Processors: Global Market Demand Analysis" report to their offering.

This new report on Embedded Processors, proves market intelligence on processor platforms used in embedded computing applications. The report provides detailed data and segmentation on CPUs, DSPs, FPGAs, and MCUs used in embedded applications.

These four major processing technologies covered are segmented by individual classification as well as collectively to measure how many units of each individual processor architecture proliferate in each of the many fragmented embedded vertical markets relative to each other. The primary data collected for this project includes supply-side data and two separate demand-side data sets.

Research highlights
The current global recession is creating an extremely challenging environment for the entire semiconductor industry.

The embedded processor segment will not be immune to negative effects from the current downturn, but it offers elements that are somewhat shielded compared to other semiconductor segments:

* Certain embedded markets are far enough removed from consumers to gain some protection from the tapped out consumer market.
* These markets are also highly diversified -- by application, account type and technical solution.
* Many markets are made up of mission critical applications.
* A number of products offer attractive ROI in this environment.
* The embedded processors market is driven by ROI regardless of macroeconomic conditions.
* Time to market pressures for OEMs developing on embedded processors and their customers.
* Demand to drive revenue from new products and services.
* Need to control costs across the technical value chain is driving more OEMS to reconsider their platform selections.
* Investment migration from hardware to software/ services continues in virtually every embedded segment, placing additional cost, price, performance and support pressures on suppliers.

Achronix demos 1066Mbps DDR3 reference design

SAN JOSE, USA: Achronix Semiconductor, makers of the world’s fastest field-programmable gate arrays (FPGAs), announced the availability of a complete 1066Mbps DDR3 solution for its Speedster FPGAs.

The newly developed SPC60, a compact development kit for the Speedster family of 1.5 GHz FPGAs, demonstrates an impressive 1066 Mbps DDR3 reference design available for “out of the box” integration with customer designs; hence, eliminating difficult memory interface implementation and verification challenges.

The SPD60 FPGA has four embedded DDR3 controllers. A full-speed (533 MHz, 1066 Mbps), full-width (72-bit) DDR3 interface can be built using no programmable logic resources.

It comes complete with reference design RTL code and documentation, which can be modified as required. Neither the controller nor the reference design requires any license fee.

The development board is designed for systems engineers who need access to both high-end 10.3 Gbps SerDes and DDR3 memory in a compact platform. SPC60 is ideal for applications where there is a growing need for high-performance (both logic and interconnect), such as in the high-end networking, signal processing, and high-performance computing markets.

“The combination of extreme logic throughput and DDR3 memory bandwidth in our Speedster FPGAs enable engineers to create high-performance designs never before achievable,” said Yousef Khalilollahi, Achronix vice president of worldwide sales and marketing.

“By embedding the 1066 Mbps DDR3 controllers in the FPGA and offering a complete DDR3 reference design, we have removed the burden of FPGA memory interface implementation and verification.”

With the SPC60 development board, designers can exercise the full performance of the Speedster device, run prepared designs provided with the kit, configure the device with a new design, and debug that design on a common platform. Achronix-specific and industry-standard development tools are provided, along with a collection of standard reference designs.

The SPC60 board and development tools are available now.

Altera's CPRI v4.1 IP core for wireless base station and remote radio head design

SAN JOSE, USA: Altera Corp. today announced the availability of its Common Public Radio Interface (CPRI) v4.1 intellectual property (IP) core.

Supporting channel speeds up to 6.144 Gbps, the CPRI v4.1 IP core supports the LTE and WiMAX standards and offers legacy support for WCDMA, CDMA and other air-interface standards in a single system.

It enables developers to easily upgrade from proprietary CPRI implementations to a highly configurable solution supporting today's standards, improving customer productivity and cost of ownership.

This fully configurable, off-the-shelf solution complements Altera's 40-nm portfolio of Arria II GX FPGAs for up to 3.072G CPRI line rates and Stratix IV GX FPGAs and HardCopy IV ASIC solutions for up to 6.144G CPRI line rates.

The IP core targets a wide range of wireless applications including multi-mode air-interface support, single-hop and multi-hop system topologies and advanced MIMO antenna configurations.

It comes complete with test benches that perform start-up sequences for common configuration modes so developers can get up to speed quickly and focus on differentiating their product.

“There is an increasing demand from our customers worldwide to provide off-the-shelf solutions for implementing common functions in wireless basestations,” said Arun Iyengar, senior director of Altera's broadcast and communications business units.

“The Altera CPRI IP core enables customers to minimize design efforts and accelerate time to market for standards-based radio access products while still retaining the ability to customize for the unique requirements of their applications. With increasing demand for bandwidth in the CPRI links, this core combined with our transceiver technology solidly positions OEMs to address future basestation requirements including 10-Gbps CPRI links.”

The Altera CPRI v4.1 IP core includes key features such as:

* Built-in support for CPRI v4.1 and backward compatible mapping methods.
* Line rate support up to 6.144 Gbps requiring a clock rate as low as 153.6 MHz to ease timing closure.
* Up to 24 antenna carriers per IP core.
* Integrated 10/100 Ethernet MAC and HDLC controllers.

“We are pleased that Altera has selected our CPRI v4.1 IP technology to expand their IP portfolio offering,” said Christian Lanzani, senior product manager in Radiocomp ApS. “This technology is the most compact, flexible and in-the-field fully verified CPRI interface solution available for distributed base stations.”

This new CPRI v4.1 core adds to Altera's broad portfolio of wireless basestation technology including IP, reference designs and DSP Builder tool support for creating optimized digital downconverters (DDC), digital upconverters (DUC), crest factor reduction (CFR), digital predistortion (DPD), and other functions.

The CPRI v4.1 core is available either in encrypted IP or as source code for complete user control.

Altera extends temperature range of Stratix III FPGAs for military apps

SAN JOSE, USA: Altera Corp. has extended the temperature range for selected members of its Stratix III FPGA family to support military applications operating in rugged environments.

Offering Stratix III FPGAs with an extended temperature range is part of Altera's enhanced commercial off-the-shelf (COTS) strategy, which ensures military customers have access to the technology and economy of scale advantages provided by commercially available products.

Components used in military applications such as radar, electronic countermeasures and ground-combat communications equipment are required to operate in extreme environments. Selected members of Altera's high-performance Stratix III FPGAs support these applications by enabling operation between -55°C to +125°C.

Altera's military-grade Stratix III FPGAs deliver a core clock performance up to 600 MHz, offer 533-MHz DDR3 DIMM support and feature up to 150K logic elements (LEs), 8 Mbits of embedded memory and up to 896 18x18 embedded multipliers. Stratix III FPGAs also feature Altera's innovative Programmable Power Technology, enabling customers to minimize power consumption and maximize performance in military applications.

"Altera's enhanced COTS strategy strives to meet the DOD's mandate of using commercially available products in military systems that meet their reliability, risk and performance requirements," said Amr El-Ashmawi, senior business unit manager of Altera's military/aerospace business unit. "With our military-grade Stratix III FPGAs, Altera delivers an FPGA solution that specifically addresses the military's size, weight and power constraints while helping keep costs in check."

Altera's Stratix III FPGA family is currently shipping in volume, offering broad support across commercial, industrial and military temperature ranges.

NI extends platforms to digital embedded sensors

AUSTIN, USA: National Instruments announced the availability of free communications intellectual property (IP) blocks for the NI LabVIEW FPGA Module that make it possible to add serial peripheral interface (SPI) and inter-integrated circuit (I2C) devices to embedded systems developed on NI reconfigurable I/O (RIO) hardware platforms.

National Instruments also has been working with component suppliers such as Analog Devices to develop drivers for common components such as microelectromechanical system (MEMS) sensors so that engineers and scientists quickly can integrate accelerometers, gyroscopes, temperature and other sensors into their embedded systems.

“With the new embedded sensor drivers for Analog Devices MEMS sensors, we are giving LabVIEW users an easy way to integrate ADI’s state-of-the-art sensors into their embedded devices,” said Bob Scannell, business development manager at Analog Devices.

Digital embedded sensors, which are used in applications ranging from automobiles to medical devices and consumer electronics, provide measurement feedback that is important to overall system performance.

Examples include sensors for monitoring environmental conditions such as temperature, humidity and pressure; ultrasonic detectors for medical devices or sensors such as light detection and ranging (LIDAR); and inertial measurement unit (IMU) devices for mobile robotics.

Using new LabVIEW FPGA IP, engineers and scientists easily can incorporate devices based on SPI and I2C, two of the most widely used types of embedded digital communication protocols, with NI RIO hardware including the CompactRIO programmable automation controller (PAC), NI Single-Board RIO embedded devices and R Series multifunction RIO devices.

NI RIO hardware platforms, which share an architecture composed of a real-time processor, a field-programmable gate array (FPGA) and I/O modules, are ideal for applications that need the reliability of validated, off-the-shelf hardware and the flexibility of custom hardware and high-performance I/O capabilities.

Engineers and scientists with limited or no hardware design experience easily can program the FPGA on NI RIO platforms using the LabVIEW FPGA Module, which provides a graphical programming tool that abstracts the VHDL code used to configure the FPGA. LabVIEW also makes it easy to build and modify custom communication IP and inline digital processing in addition to integrating a wide array of analog and digital signals and sensors for future devices.

Readers can visit www.ni.com/ipnet to download the free LabVIEW FPGA IP for SPI and I2C sensors as well as the sensor drivers for Analog Devices MEMS sensors.

Readers can visit NI Developer Zone on www.ni.com to download a resource kit with more information on how to add digital embedded sensors to NI RIO-based systems.

NI's FlexRIO expands capabilities of FPGA-enabled instruments

AUSTIN, USA: National Instruments announced the expansion of its NI FlexRIO product line with multiple forthcoming adapter modules, which provide engineers with application-specific I/O for RF, digital, time-domain and vision inspection systems.

The NI FlexRIO family is the industry’s first commercial off-the-shelf (COTS) solution to provide engineers the flexibility of NI LabVIEW FPGA technology combined with high-speed, instrument-class, reconfigurable and user-defined I/O on the PXI platform.

All NI FlexRIO solutions require two distinct hardware pieces –- an I/O-specific adapter module and a PXI-based NI FlexRIO FPGA module, which features a Xilinx Virtex-5 FPGA. With a variety of NI FlexRIO adapter modules, engineers can directly interface FPGAs to new types of I/O for measurements across automated test applications that require real-time performance.

The software-defined, reconfigurable I/O capabilities of NI FlexRIO make it possible for engineers to employ techniques such as in-line signal processing, hardware-in-the-loop control and protocol-aware test for designing and testing many complex electronic devices.

National Instruments has already released two NI FlexRIO adapter modules, the NI 6581 100 MHz digital I/O (DIO) adapter module and the NI 6585 200 MHz low-voltage differential signaling (LVDS) DIO module.

In addition to these products, NI soon will release several new specialized adapter modules including a dual-channel, 100 MS/s, 14-bit input, 16-bit output baseband transceiver for radio prototyping and stimulus-response applications; a 3 GS/s, eight-bit digitizer for time-domain measurements and ultra-wideband spectral analysis; a four-channel, 250 MS/s, 14-bit digitizer for signal intelligence and other applications requiring high speed and resolution; and a full-configuration Camera Link interface for high-speed image processing and low-latency control.

As part of the open nature of the NI FlexRIO platform, NI also has been collaborating with several National Instruments Alliance Partner companies on third-party adapter modules, including the already-released NexFrontier NF1208 100 MHz vector rate pin electronics digital I/O adapter module and Averna IEEE 1394b adapter module.

Other companies, including SET, Prevas AB, Cosylab and Adsys Controls, are finalizing additional NI FlexRIO adapter module designs for future release.

For applications requiring highly customized I/O, engineers with PCB design and HDL experience can create their own adapter modules using the NI FlexRIO Adapter Module Development Kit (MDK).

The MDK features full documentation on electrical, firmware, software and mechanical design details, including CAD files and example HDL, as well as various metal adapter module enclosures.

Xilinx Virtex-6 FPGAs enable highest PCIe bandwidth

BANGALORE, INDIA: Xilinx today announced that its newest generation Virtex-6 FPGA family is compliant with the PCI Express 2.0 specification, delivering up to 50 percent lower power than previous generations and 15 percent higher performance than competitive offerings.

The second-generation PCIe block integrated in Xilinx Virtex-6 FPGAs has passed PCI-SIG PCI Express version 2.0 compliance and interoperability testing for 1 to 8-lane configurations, adding to the broad range of design resources from Xilinx and its alliance members that support the widely adopted serial interconnect standard.

This significant industry milestone is expected to accelerate mainstream development of high bandwidth PCIe 2.0 systems for communications, multimedia, server and mobile platforms, enabling applications such as high definition video, high-end medical imaging, and industrial instrumentation among others.

In addition, Xilinx has once again teamed up with key alliance members Northwest Logic Inc. and PLDA to provide Direct Memory Access (DMA) intellectual property (IP) cores for Virtex-6 FPGAs.

This latest collaboration builds on their existing PCIe 2.0 soft IP for Virtex-5 FXT devices, the first FPGA to provide PCIe 2.0 x8-lane support with the Northwest Logic DMA core. DMA engines enable the efficient movement of data in systems, ensuring that the PCIe block in Virtex-6 FPGAs delivers maximum performance and bandwidth.

“With increasing adoption of PCIe Gen 2 for meeting high bandwidth connectivity requirements, many of the VLSI/System design houses in India are increasingly engaging global customers in use of this protocol as part of their overall system designs,” said Neeraj Varma, Country Manager - Sales, for India and Australia and New Zealand at Xilinx.

“By offering this as Hard IP in Virtex-6 along with reference designs, the design houses in India can offer a very compelling solution to their end customers -- by reducing the overall project timeline along with the total cost of ownership."

Designers can immediately begin the evaluation and design of PCI Express 2.0 compliant systems in Virtex-6 FPGAs. To assist in this effort, the Xilinx CORE Generator system delivered in the ISE Design Suite provides the PCIe core, reference design and all the scripts, basic testbench, and simulation models needed to streamline integration into customer designs.

Designers can download at no charge the ISE WebPACK software or trial version of the full featured ISE Design Suite from Xilinx web site at: www.xilinx.com/tools/webpack.

“The demand for high-bandwidth connectivity is insatiable, and the PCIe 2.0 standard is critical to meeting the requirements of high performance, low power applications, especially in the telecommunications and server markets,” said Tom Feist, senior marketing director for ISE Design Suite at Xilinx.

“Integrated PCIe FPGA blocks eliminate the I/O bottleneck in maximizing system performance, and were first introduced with our Virtex-5 FPGAs. Now with Virtex-6 FPGAs, designers in the pursuit of even higher bandwidth can take full advantage of our production-proven PCIe implementation with up to 50 percent lower power than the nearest competitive offering.”

Production-proven PCIe support
Xilinx continues to lead the FPGA industry in support for PCI Express solutions. Xilinx was the first to integrate compliant PCIe version 1.1 blocks into programmable devices with its Virtex-5 FPGA family.

PCIe 2.0 soft IP support soon followed for Virtex-5 FXT and Virtex-5 TXT devices, delivering the first FPGA-based solution to be compliant with the 5Gbps version of the standard.

By leveraging all the application expertise and customer successes of its production-proven Virtex-5 FPGA PCIe solutions, Xilinx was able to achieve PCI-SIG compliance with Virtex-6 FPGAs for both PCIe 1.1 and 2.0 multi-lane configurations.

PCIe 2.0 blocks are integrated in all Virtex-6 devices with serial transceivers and are supported in all speed grades. These blocks include the complete transaction data link and physical layers, which use the Xilinx GTX transceiver technology and integrated BRAM.

The GTX serial transceivers in Virtex-6 LXT and SXT FPGAs are fully characterized across process, voltage and temperature (PVT), and the complete PCI-SIG compliance report is available for download at: www.pcisig.com/developers/compliance_program/integrators_list/pcie_2.0

The Virtex-6 FPGA Endpoint block for PCI Express also incorporates many easy-to-use features to simplify the design process, as well as configurations optimized for PCIe Endpoint and Root Port applications with additional resources to create a complete PCIe solution.

Altera 40-nm Arria II GX FPGAs achieve PCI-SIG compliance for PCIe Express 2.0

SAN JOSE, USA: Altera Corp. today announced that its 40-nm Arria II GX FPGAs are compliant with the PCI Express (PCIe) 2.0 specification.

The device successfully passed the PCI-SIG® Compliance and Interoperability Tests at the PCI-SIG Workshop and is now included on the PCI-SIG Integrators List. Arria II GX FPGAs achieved compliance for up to x8 lane configurations for PCIe Gen1 end-point applications.

Currently shipping, Altera's mid-range Arria II GX FPGAs feature integrated transceivers with data rates up to 3.75 Gbps, and have a hard, configurable PCIe interface embedded within the device.

The device's hard IP block implements PCIe Gen1 (PIPE) PHY-MAC, data link, and transaction layers. This IP block is highly configurable to meet the requirements to support end-point and root-port applications, and is PCIe 2.0 compliant in x1-, x4- and x8-lane configurations.

"Arria II GX FPGAs are the only mid-range FPGAs that have attained PCIe 2.0 compliance," said Luanne Schirrmeister, senior director of component product marketing at Altera. "They offer 25 percent higher performance, up to 50 percent lower price and up to 50 percent lower power compared to competitive FPGAs."

Arria II GX FPGAs are targeted for applications using mainstream protocols such as PCIe and Gigabit Ethernet (GbE). The devices have up to sixteen 3.75-Gbps transceivers, 256K logic elements (LEs) and 8.5 Mbits of internal RAM.

The Arria II GX EP2AGX125 device is currently available.

Altera announces Arria II GX development kit

SAN JOSE, USA: Altera Corp. announced the availability of the Arria II GX FPGA Development Kit.

The kit features hardware and software resources that enable customers to rapidly evaluate and adopt Arria II GX devices, Altera's mid-range 40-nm FPGAs, for implementing a wide range of high-performance digital functions in communications, broadcast, computer and storage, test and measurement, medical and military applications.

The Arria II GX FPGA Development Kit reduces development time by providing a complete system of pre-verified components and supporting hardware reference designs. For example, the development kit offers an entire PCI Express (PCIe) Gen1 end-point design package, featuring a PCI-SIG-compliant Arria II GX FPGA-based development board with an embedded PCIe Gen1 hard intellectual property (IP) core.

A wide range of development resources are available on Altera website, including free PCIe training, PCIe, Gigabit Ethernet (GbE) and SDI-based reference designs to help designers get up-to-speed quickly, and a database of over 20 readily available mezzanine cards to address specific application and market needs.

"The Arria II GX Development Kit allows customers to rapidly evaluate Arria II GX FPGAs and quickly move their product designs from concept to reality," said Luanne Schirrmeister, senior director of component product marketing at Altera.

"This development kit offers a range of high-performance features that will enable Arria II GX customers to create custom hardware-based product differentiation in a broad range of applications."

The Arria II GX FPGA Development Kit comes complete with a development board featuring an Arria II GX (EP2AGX125EF35) FPGA with twelve transceivers, a one-year license for Quartus II Design Software, Development Kit Edition and access to Altera's MegaCore IP library including the Nios II Embedded Design Suite.

Arria II GX FPGAs provide customers with industry-leading innovations, including up to sixteen 3.75-Gbps transceivers, 256K logic elements (LEs) and 8.5 Mbits of internal RAM. Arria II GX devices are targeted for applications using mainstream transceiver protocols including PCIe, GbE, triple-speed SDI, CPRI, GPON, and XAUI.

The Arria II GX FPGA Development Kit is currently available and priced at $1,495.

Achronix deploys Synopsys IC Validator and IC Compiler for next-gen FPGA design

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Achronix Semiconductor Corporation, maker of ultra-fast field-programmable gate arrays (FPGAs), has deployed Synopsys' IC Compiler and the recently announced IC Validator, the newest addition to the Galaxy Implementation Platform, for designing their next generation of high-end FPGAs.

IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow.

Targeting a wide range of telecommunications, networking, video and DSP applications, Achronix's FGPAs will offer multimillion gate capacities, a wide array of high- performance embedded IP components, high-speed I/Os, memory blocks and dedicated DSP function building blocks.

"As process nodes shrink and next generation FPGA architecture grows more complex, we are seeing an increase in design challenges and manufacturing rule count and complexity," said Ravi Sunkavalli, vice president of hardware engineering at Achronix.

"Unique challenges, especially in design planning, clock tree synthesis, full chip placement and routing, and RDL routing and placement, necessitate a highly automated implementation system with integrated flows for manufacturing compliance. By leveraging IC Compiler and IC Validator, we are confident that we can cost effectively meet our time-to-market objectives."

At advanced nodes (45nm and below), the productivity gap between physical implementation and signoff is becoming a serious bottleneck that can lead to significant schedule delays. Prevailing approaches to physical design, which can be described as "implement-then-verify," can result in multiple iterations between design and signoff.

The implement-then-verify approach may also complicate convergence, as physical-verification-induced corrections can alter other design objectives such as area, timing and power. In-Design physical verification with IC Validator helps to ensure clean layout upon leaving the design environment and avoid late-stage surprises.

With In-Design physical verification, specific errors and selected areas of layout can be targeted incrementally, providing a speed-up in overall design completion time.

Metal fill insertion, a mandatory requirement for manufacturability, exemplifies the drawbacks of the implement-then-verify approach. The high speed, coupled with the dense routing requirements of Achronix's FPGA design requires accurate manufacturing compliance flows for metal fill to be timing aware and of optimal density.

With In-Design physical verification, IC Validator and IC Compiler address this need within the place and route environment. The seamless integration enables an optimal metal-fill flow that is timing aware, signoff quality and void of expensive stream-outs and stream-ins. Additionally, this flow achieves higher density by utilizing a track-less approach.

"Designing at advanced process nodes with point tool driven "implement-then-verify" loops makes tapeout schedules extremely unpredictable," said Sanjay Bali, director of physical verification and DFM marketing at Synopsys. "By adopting IC Compiler and IC Validator for In-Design Physical Verification, Achronix is taking full advantage of Synopsys' ability to bridge the productivity gap between design implementation and physical verification."

A guide to FPGAs for communications

MOUNTAIN VIEW, USA: The Linley Group has published A Guide to FPGAs for Communications, First Edition. Authored by Jag Bolaria and Joseph Byrne, the 146-page book comes for a single License: $2,995 (single copy).

Evaluating and comparing FPGAs for communications applications
Despite a downturn in the market in 2008, FPGA revenue continues to grow due to strong demand from communications market customers and OEMs. To ensure long-term growth and stability, FPGA vendors are diversifying their product portfolios. Although only a handful of FPGA vendors are serving the networking and communications segment, the abundance of offerings makes it a challenge to compare and select products.

This report covers a range of commercially available FPGA devices for communications equipment. We provide in-depth coverage of midrange FPGAs and high-end FPGAs for wireless and wireline infrastructure systems as well as an overview of low-end FPGAs.

We provide a roadmap to the complex product lines of market leaders Xilinx (Spartan and Virtex) and Altera (Arria, Stratix, and Cyclone) as well as smaller supplier such as Lattice, Achronix, and Cswitch.

For wireless applications, we cover FPGAs for base stations, including remote radio heads, turbo coding, and modulation. For wireline applications, it covers typical functions performed by FPGAs, including framers, mappers, MACs, and coprocessors.

The report discusses the pros and cons of using FPGAs or alternatives such as ASSPs, ASICs, and processors. For each vendor, we discuss its FPGA products as well as the available IP (intellectual property) for communications applications.

Unlike typical market research, this report provides technology analysis and head-to-head product comparisons. Which FPGAs will win designs and why? Which device is best-suited for which application? How will these vendors be positioned as the market evolves? Only The Linley Group's unique technology analysis can provide this forward-looking view.

We sort out the technology and the vendors
We begin with an extensive overview of this growing market, providing several introductory chapters that define and describe basic concepts and key technologies.

We explore the target markets and applications for FPGAs, followed by an explanation of the common attributes of these products. Following these introductory chapters, the report delivers a complete chapter on the major vendors that offer products in multiple segments.

This handy guide, packed with valuable information, brings you up-to-date on the newest developments in this important market and gives you the analysis you need to help choose a supplier or partner in this field.

"A Guide to FPGAs for Communications" cuts through the vendor hype to analyze each vendor and each product, probe their strengths and weaknesses, and present relevant details in a consistent, easy to compare fashion.

The report provides background on these technologies, with in-depth coverage of the vendors in each segment, including product details and roadmap information where available. Finally, we provide our outlook for the leading vendors in each segment and for the overall market.