MOUNTAIN VIEW, USA: Synopsys Inc. today introduced its In-Design Rail Analysis capability to accelerate design closure.
Part of Synopsys' IC Compiler in-design ecosystem, In-Design Rail Analysis utilizes embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation.
By identifying and fixing voltage-drop and electromigration issues earlier in the flow, designers can eliminate costly iterations late in the design process.
Working in concert with IC Compiler's Power Network Synthesis (PNS) and In-Design Physical Verification capabilities, In-Design Rail Analysis provides designers with a comprehensive solution for both the implementation and verification of power networks.
"Performing rail analysis and fixing within the IC Compiler place-and-route environment will greatly improve our designers' productivity, a significant benefit of Synopsys' Galaxy Implementation Platform," said Hitoshi Sugihara, Department Manager of DFM & Digital EDA Technology Development Department at Renesas Technology Corp.
"We worked with Synopsys early in the development of this technology to ensure that it is easy to use, and have confirmed PrimeRail accuracy and correlation with HSPICE and silicon. We plan to standardize on a design methodology that takes advantage of In-Design Rail Analysis."
Traditional approaches to power network design consist of separate implementation and verification steps, often performed by different engineers using many tools and environments in a complex flow.
With leading-edge system-on-chip (SoC) designs, this approach often results in multiple iterations between physical implementation and signoff, adding significant risk to project schedules. By eliminating complicated data exchanges and with no new tools to learn, In-Design Rail Analysis helps IC Compiler users ensure the integrity of their power network early and frequently during the physical implementation process, avoiding late-stage surprises close to tapeout.
In-Design Rail Analysis works in tandem with IC Compiler's PNS capability to enable designers to efficiently implement, optimize and refine power networks, significantly reducing overdesign. In addition, In-Design Physical Verification helps ensure that power networks are design-rule clean as refinements and fixes are implemented.
IC Compiler's ecosystem of PNS, In-Design Rail Analysis and In-Design Physical Verification today offers a fast and comprehensive solution for power network design.
"The charter of our IC Compiler in-design ecosystem is to bring advanced analysis and verification capabilities into the hands of place-and-route engineers," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group.
"Complementing our recent introduction of In-Design Physical Verification with IC Validator, In-Design Rail Analysis is the latest innovation aimed at significantly reducing design iterations which can seriously impact time-to-tapeout."
Showing posts with label IC Compiler. Show all posts
Showing posts with label IC Compiler. Show all posts
Monday, July 20, 2009
Friday, July 17, 2009
Achronix deploys Synopsys IC Validator and IC Compiler for next-gen FPGA design
MOUNTAIN VIEW, USA: Synopsys Inc. announced that Achronix Semiconductor Corporation, maker of ultra-fast field-programmable gate arrays (FPGAs), has deployed Synopsys' IC Compiler and the recently announced IC Validator, the newest addition to the Galaxy Implementation Platform, for designing their next generation of high-end FPGAs.
IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow.
Targeting a wide range of telecommunications, networking, video and DSP applications, Achronix's FGPAs will offer multimillion gate capacities, a wide array of high- performance embedded IP components, high-speed I/Os, memory blocks and dedicated DSP function building blocks.
"As process nodes shrink and next generation FPGA architecture grows more complex, we are seeing an increase in design challenges and manufacturing rule count and complexity," said Ravi Sunkavalli, vice president of hardware engineering at Achronix.
"Unique challenges, especially in design planning, clock tree synthesis, full chip placement and routing, and RDL routing and placement, necessitate a highly automated implementation system with integrated flows for manufacturing compliance. By leveraging IC Compiler and IC Validator, we are confident that we can cost effectively meet our time-to-market objectives."
At advanced nodes (45nm and below), the productivity gap between physical implementation and signoff is becoming a serious bottleneck that can lead to significant schedule delays. Prevailing approaches to physical design, which can be described as "implement-then-verify," can result in multiple iterations between design and signoff.
The implement-then-verify approach may also complicate convergence, as physical-verification-induced corrections can alter other design objectives such as area, timing and power. In-Design physical verification with IC Validator helps to ensure clean layout upon leaving the design environment and avoid late-stage surprises.
With In-Design physical verification, specific errors and selected areas of layout can be targeted incrementally, providing a speed-up in overall design completion time.
Metal fill insertion, a mandatory requirement for manufacturability, exemplifies the drawbacks of the implement-then-verify approach. The high speed, coupled with the dense routing requirements of Achronix's FPGA design requires accurate manufacturing compliance flows for metal fill to be timing aware and of optimal density.
With In-Design physical verification, IC Validator and IC Compiler address this need within the place and route environment. The seamless integration enables an optimal metal-fill flow that is timing aware, signoff quality and void of expensive stream-outs and stream-ins. Additionally, this flow achieves higher density by utilizing a track-less approach.
"Designing at advanced process nodes with point tool driven "implement-then-verify" loops makes tapeout schedules extremely unpredictable," said Sanjay Bali, director of physical verification and DFM marketing at Synopsys. "By adopting IC Compiler and IC Validator for In-Design Physical Verification, Achronix is taking full advantage of Synopsys' ability to bridge the productivity gap between design implementation and physical verification."
IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow.
Targeting a wide range of telecommunications, networking, video and DSP applications, Achronix's FGPAs will offer multimillion gate capacities, a wide array of high- performance embedded IP components, high-speed I/Os, memory blocks and dedicated DSP function building blocks.
"As process nodes shrink and next generation FPGA architecture grows more complex, we are seeing an increase in design challenges and manufacturing rule count and complexity," said Ravi Sunkavalli, vice president of hardware engineering at Achronix.
"Unique challenges, especially in design planning, clock tree synthesis, full chip placement and routing, and RDL routing and placement, necessitate a highly automated implementation system with integrated flows for manufacturing compliance. By leveraging IC Compiler and IC Validator, we are confident that we can cost effectively meet our time-to-market objectives."
At advanced nodes (45nm and below), the productivity gap between physical implementation and signoff is becoming a serious bottleneck that can lead to significant schedule delays. Prevailing approaches to physical design, which can be described as "implement-then-verify," can result in multiple iterations between design and signoff.
The implement-then-verify approach may also complicate convergence, as physical-verification-induced corrections can alter other design objectives such as area, timing and power. In-Design physical verification with IC Validator helps to ensure clean layout upon leaving the design environment and avoid late-stage surprises.
With In-Design physical verification, specific errors and selected areas of layout can be targeted incrementally, providing a speed-up in overall design completion time.
Metal fill insertion, a mandatory requirement for manufacturability, exemplifies the drawbacks of the implement-then-verify approach. The high speed, coupled with the dense routing requirements of Achronix's FPGA design requires accurate manufacturing compliance flows for metal fill to be timing aware and of optimal density.
With In-Design physical verification, IC Validator and IC Compiler address this need within the place and route environment. The seamless integration enables an optimal metal-fill flow that is timing aware, signoff quality and void of expensive stream-outs and stream-ins. Additionally, this flow achieves higher density by utilizing a track-less approach.
"Designing at advanced process nodes with point tool driven "implement-then-verify" loops makes tapeout schedules extremely unpredictable," said Sanjay Bali, director of physical verification and DFM marketing at Synopsys. "By adopting IC Compiler and IC Validator for In-Design Physical Verification, Achronix is taking full advantage of Synopsys' ability to bridge the productivity gap between design implementation and physical verification."
Monday, June 29, 2009
Aquantia deploys Synopsys IC Validator and IC Compiler for 40nm quad 10GBASE-T design
MOUNTAIN VIEW, USA: Synopsys Inc. today announced that Aquantia, an innovator in 10GBASE-T networking, has deployed Synopsys' recently announced IC Validator, the newest addition to the Galaxy Implementation Platform, into production use at 40nm.
IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow.
Compared to the typical implement-then-verify flow, the In-Design flow is instrumental in avoiding late-stage surprises and enabling integrated circuit (IC) providers like Aquantia - which is in the process of delivering an advanced 40nm-based quad 10GBASE-T solution - to achieve a faster, robust hand-off to the foundry.
"A few weeks can mean the difference between meeting or missing the market window in our fast moving market," said Ramin Shirani, vice president of engineering at Aquantia.
"IC Validator's ability to perform In-Design physical verification within IC Compiler reduces the physical verification effort from weeks to days by automating and accelerating one of the most onerous parts of our design cycle. We were impressed by IC Validator's fast convergence in concurrently implementing signoff metal-fill and DRC while reducing the timing impact of such implementation."
Prevailing physical verification flows are predominantly post-processing oriented, relying on modifications to the design after GDSII has been generated. These flows can lead to suboptimal results and can induce multiple discover-then-fix iterations.
Metal-fill insertion, a mandatory manufacturability step at the advanced nodes, exemplifies this issue. Physical designers stream out the timing-closed, post-fill design for signoff validation and then stream it back in to fix any signoff errors flagged during physical verification. This time-intensive discover-then-fix loop is typically repeated on each block until the post-fill design is both signoff qualified and timing clean.
With In-Design physical verification, IC Validator and IC Compiler address the manufacturability issues within the place and route environment. The seamless integration enables an optimal metal-fill flow that is timing aware, signoff quality and void of expensive stream-outs and stream-ins. Additionally, this flow achieves higher density by utilizing a track-less approach.
While In-Design physical verification is enabled through tight integration with place and route, it is founded on a high-performance, foundry-endorsed, signoff-accurate engine in IC Validator. With a native multicore architecture, IC Validator can significantly accelerate the metal-fill process by up to 20 times.
For incremental fixes to metal fill near critical nets or ECOs, the In-Design flow enables rule-based, layer-based and area-based metal fill removal and re-insertion, thereby helping eliminate the need for costly full-chip runs.
"In-Design physical verification with IC Validator and IC Compiler is successfully addressing the increasing design-for-manufacturability needs of our customer base," said Saleem Haider, senior director of marketing, physical design and DFM at Synopsys.
"For meeting foundry-dictated manufacturing needs, Aquantia's adoption of IC Validator demonstrates the value of placing the emphasis on the 'D'in DFM and handling manufacturability requirements during design instead of post-design modifications."
IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow.
Compared to the typical implement-then-verify flow, the In-Design flow is instrumental in avoiding late-stage surprises and enabling integrated circuit (IC) providers like Aquantia - which is in the process of delivering an advanced 40nm-based quad 10GBASE-T solution - to achieve a faster, robust hand-off to the foundry.
"A few weeks can mean the difference between meeting or missing the market window in our fast moving market," said Ramin Shirani, vice president of engineering at Aquantia.
"IC Validator's ability to perform In-Design physical verification within IC Compiler reduces the physical verification effort from weeks to days by automating and accelerating one of the most onerous parts of our design cycle. We were impressed by IC Validator's fast convergence in concurrently implementing signoff metal-fill and DRC while reducing the timing impact of such implementation."
Prevailing physical verification flows are predominantly post-processing oriented, relying on modifications to the design after GDSII has been generated. These flows can lead to suboptimal results and can induce multiple discover-then-fix iterations.
Metal-fill insertion, a mandatory manufacturability step at the advanced nodes, exemplifies this issue. Physical designers stream out the timing-closed, post-fill design for signoff validation and then stream it back in to fix any signoff errors flagged during physical verification. This time-intensive discover-then-fix loop is typically repeated on each block until the post-fill design is both signoff qualified and timing clean.
With In-Design physical verification, IC Validator and IC Compiler address the manufacturability issues within the place and route environment. The seamless integration enables an optimal metal-fill flow that is timing aware, signoff quality and void of expensive stream-outs and stream-ins. Additionally, this flow achieves higher density by utilizing a track-less approach.
While In-Design physical verification is enabled through tight integration with place and route, it is founded on a high-performance, foundry-endorsed, signoff-accurate engine in IC Validator. With a native multicore architecture, IC Validator can significantly accelerate the metal-fill process by up to 20 times.
For incremental fixes to metal fill near critical nets or ECOs, the In-Design flow enables rule-based, layer-based and area-based metal fill removal and re-insertion, thereby helping eliminate the need for costly full-chip runs.
"In-Design physical verification with IC Validator and IC Compiler is successfully addressing the increasing design-for-manufacturability needs of our customer base," said Saleem Haider, senior director of marketing, physical design and DFM at Synopsys.
"For meeting foundry-dictated manufacturing needs, Aquantia's adoption of IC Validator demonstrates the value of placing the emphasis on the 'D'in DFM and handling manufacturability requirements during design instead of post-design modifications."
Wednesday, June 10, 2009
Synopsys IC Compiler with Zroute achieves successful tapeout for Infineon automotive MCU
MOUNTAIN VIEW, USA: Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that IC Compiler with Zroute technology drove silicon success for automotive microcontrollers of Infineon Technologies AG.
IC Compiler's Zroute provided a near 100 percent redundant via rate, enabling leading-edge device reliability and allowing Infineon to successfully tape out the lead product of its high-performance automotive 32-bit MCU platform in an advanced embedded Flash technology.
In addition, by deploying a hierarchical design implementation flow together with intelligent Multi Corner Multi Mode (MCMM) optimization across different scenarios, IC Compiler achieved outstanding quality of results, meeting the high performance, area and power targets, specifically of the Infineon TriCore 32-bit MCUs.
"Being on the leading edge of automotive applications, Infineon is striving to supply intelligent chips that increase the energy efficiency and safety of vehicles while offering optimal quality and reliability," said Hartmut Hiller, senior director, Design Methodology and Implementation at Infineon. "As single vias are one of the major factors impacting reliability, we are always looking for design implementation tools that deliver the highest redundant via rate possible."
Zroute's unique architecture takes advantage of best-in-class routing technologies to meet the demands of companies like Infineon that are developing complex chips with high reliability targets to fulfill the ever increasing quality requirements of automotive tier1 and original equipment manufacturers (OEMs) all over the world.
Utilizing concurrent design-for-manufacturability (DFM) optimization techniques, including soft rules and via redundancy, Zroute makes an efficient trade-off between manufacturability and the traditional design goals of timing, area, power and signal integrity. In addition, Zroute's native multicore support takes advantage of the latest microprocessor architectures to deliver near-linear scalability of runtimes as the number of cores increase.
"The selection of IC Compiler by Infineon and the recent complex automotive device tapeouts with Zroute are examples of Synopsys' IC Compiler technology driving customer success across the board," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "Synopsys values the relationship with Infineon and is committed to working closely with Infineon to evolve our product and methodologies based on feedback and requirements from the design teams of their leading-edge automotive applications."
IC Compiler's Zroute provided a near 100 percent redundant via rate, enabling leading-edge device reliability and allowing Infineon to successfully tape out the lead product of its high-performance automotive 32-bit MCU platform in an advanced embedded Flash technology.
In addition, by deploying a hierarchical design implementation flow together with intelligent Multi Corner Multi Mode (MCMM) optimization across different scenarios, IC Compiler achieved outstanding quality of results, meeting the high performance, area and power targets, specifically of the Infineon TriCore 32-bit MCUs.
"Being on the leading edge of automotive applications, Infineon is striving to supply intelligent chips that increase the energy efficiency and safety of vehicles while offering optimal quality and reliability," said Hartmut Hiller, senior director, Design Methodology and Implementation at Infineon. "As single vias are one of the major factors impacting reliability, we are always looking for design implementation tools that deliver the highest redundant via rate possible."
Zroute's unique architecture takes advantage of best-in-class routing technologies to meet the demands of companies like Infineon that are developing complex chips with high reliability targets to fulfill the ever increasing quality requirements of automotive tier1 and original equipment manufacturers (OEMs) all over the world.
Utilizing concurrent design-for-manufacturability (DFM) optimization techniques, including soft rules and via redundancy, Zroute makes an efficient trade-off between manufacturability and the traditional design goals of timing, area, power and signal integrity. In addition, Zroute's native multicore support takes advantage of the latest microprocessor architectures to deliver near-linear scalability of runtimes as the number of cores increase.
"The selection of IC Compiler by Infineon and the recent complex automotive device tapeouts with Zroute are examples of Synopsys' IC Compiler technology driving customer success across the board," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "Synopsys values the relationship with Infineon and is committed to working closely with Infineon to evolve our product and methodologies based on feedback and requirements from the design teams of their leading-edge automotive applications."
Tuesday, June 2, 2009
Synopsys IC Compiler MCMM capability delivers 2X faster design closure
MOUNTAIN VIEW, USA: Synopsys Inc. announced that New Japan Radio Co. Ltd (NJR), a leading supplier of linear IC devices for professional audio and high reliability automotive products, successfully deployed IC Compiler's multi-corner/multi-mode (MCMM) capability to achieve two times (2X) faster design closure.
Previously, NJR performed half a dozen place-and-route iterations to close timing across all design modes and process corners, resulting in costly tapeout delays. IC Compiler's concurrent MCMM optimization is designed to simultaneously optimize across all modes and corners to eliminate multiple iterations and deliver faster time to results.
"We are facing shrinking time-to-market windows and intense competitive pressure," said Shoichi Matsumoto, general manager, IC Design Department IV, IC Division at NJR. "In order to retain our competitive edge, it is necessary to have a design closure flow that can deliver best-in-class results in half the time. IC Compiler's concurrent MCMM capability enabled us to reliably and efficiently meet these goals."
Being in the very competitive high-end consumer and automotive market segments requires NJR to deliver high accuracy and reliability in their finished product. These complex devices must operate correctly across all design modes and be 100 percent reliable across all process corners.
With several back-to-back tapeouts a year, NJR typically has only a six-week period to place and route a single design. This tight schedule cannot be met if multiple iterations must be performed to close timing. IC Compiler provides them with precisely the solution they need, with concurrent MCMM capability performing simultaneous analysis and optimization across all modes, corners and design costs.
With powerful core engines like the IC Compiler placer and Zroute DFM-focused router, combined with tight correlation to the technology-leading PrimeTime signoff tool, IC Compiler helps deliver optimal results with predictable and accelerated time-to-design closure.
"MCMM, long available in IC Compiler, is now a mainstream design requirement, and dozens of companies worldwide rely on IC Compiler's concurrent MCMM capability to successfully tapeout their complex designs," said Bijan Kiani, vice president, Product Marketing and Business Development Group at Synopsys. "NJR has deployed IC Compiler and experienced the benefits of its concurrent MCMM capability to achieve faster design closure."
Previously, NJR performed half a dozen place-and-route iterations to close timing across all design modes and process corners, resulting in costly tapeout delays. IC Compiler's concurrent MCMM optimization is designed to simultaneously optimize across all modes and corners to eliminate multiple iterations and deliver faster time to results.
"We are facing shrinking time-to-market windows and intense competitive pressure," said Shoichi Matsumoto, general manager, IC Design Department IV, IC Division at NJR. "In order to retain our competitive edge, it is necessary to have a design closure flow that can deliver best-in-class results in half the time. IC Compiler's concurrent MCMM capability enabled us to reliably and efficiently meet these goals."
Being in the very competitive high-end consumer and automotive market segments requires NJR to deliver high accuracy and reliability in their finished product. These complex devices must operate correctly across all design modes and be 100 percent reliable across all process corners.
With several back-to-back tapeouts a year, NJR typically has only a six-week period to place and route a single design. This tight schedule cannot be met if multiple iterations must be performed to close timing. IC Compiler provides them with precisely the solution they need, with concurrent MCMM capability performing simultaneous analysis and optimization across all modes, corners and design costs.
With powerful core engines like the IC Compiler placer and Zroute DFM-focused router, combined with tight correlation to the technology-leading PrimeTime signoff tool, IC Compiler helps deliver optimal results with predictable and accelerated time-to-design closure.
"MCMM, long available in IC Compiler, is now a mainstream design requirement, and dozens of companies worldwide rely on IC Compiler's concurrent MCMM capability to successfully tapeout their complex designs," said Bijan Kiani, vice president, Product Marketing and Business Development Group at Synopsys. "NJR has deployed IC Compiler and experienced the benefits of its concurrent MCMM capability to achieve faster design closure."
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