BANGALORE, INDIA: Xilinx Inc. today announced demonstrations of the latest developments in serial connectivity that lower the cost and power of serial digital interfaces and enable the rapid adoption of emerging DisplayPort and Ethernet AVB protocols.
At the heart of these innovations is the Xilinx Broadcast Connectivity Targeted Design Platform that simplifies development of complete broadcast audio and video interface solutions with support for standard definition (SD), high definition (HD), and 3G-SDI standards in a single programmable device. The new capabilities are designed to enable faster time to market and greater product differentiation of professional broadcast systems.
Based on latest generation Virtex-6 and Spartan-6 FPGAs, Xilinx is demonstrating the scalable performance and cost-saving integration advantages of its common platform approach for broadcast audio, video and network connectivity applications.
Xilinx’s broadcast connectivity platform is the first FPGA offering with low-cost, low-power serial transceivers supporting HD video for professional broadcast applications. It also incorporates the new DisplayPort interface LogiCORE IP core from Xilinx enabling transmission and reception of serial digital video for professional and consumer displays.
“SDI is ubiquitous throughout the broadcast industry today. Companies don’t want to spend effort, time, and money on interfaces,” said Ben Runyan, senior manager, Broadcast Marketing at Xilinx.
”Our broadcast connectivity platform and DisplayPort IP simplify interface development, so manufacturers can improve time to market, lower implementation costs, and focus on creating value for their end customers. They can spend time finding innovative ways to differentiate and put limited engineering resources to better use developing advanced, higher quality video processing. These are compelling market advantages, especially for the many companies that already use Xilinx FPGAs in their broadcast systems.”
Live demonstrations of the broadcast connectivity platform and DisplayPort IP are being held at the IBC2009 Exhibition in Amsterdam from September 11th through 15th in Xilinx Booth #10.B30. Xilinx is also showcasing the first fully certified Dolby Digital Professional Encoder on Xilinx FPGAs announced separately today (see related news release).
Broadcast Connectivity Targeted Design Platform
The Xilinx Broadcast Connectivity Targeted Design Platform encompasses all the connectivity elements needed by hardware and software developers to build serial digital interface (SDI) solutions and fully characterize and verify performance for the targeted applications.
Developers can choose Virtex-6 FPGAs for the highest-speed serial connectivity with up to 72 serial transceivers and line rates in excess of 11Gbps for SD/HD/3G-SDI and embedded audio applications, as well as fully integrated support for 10G SDI designs.
For the lowest risk and lowest cost serial connectivity, Spartan-6 FPGAs with up to eight 3.125Gbps transceivers support SD and HD resolution applications with up to 60 percent lower system cost and less than 50 percent the power of previous offerings.
In addition to silicon devices, the broadcast connectivity platform integrates a predictable and intelligently optimized set of design technologies and methodologies that make it easy for broadcast development engineers to implement triple rate SDI designs.
These include Xilinx and third-party domain and application-specific IP cores, complete design environments, and demonstration and reference designs, along with a base set of digital audio/video development boards and industry-standard FPGA Mezzanine Card (FMC) daughter boards.
Xilinx will rollout a series of market-specific development kits for the broadcast connectivity platform so developers can get started quickly using the targeted reference design and development board, and then modify the design as needed to meet the specific feature requirements and design goals of their applications. Targeted applications include cameras, switchers, routers, encoders, professional monitors, and cinema projectors.
Broadcast Connectivity Video Standards
Xilinx continues to drive development of new technologies that reduce the risk and cost of adopting emerging broadcast video standards aimed at improving video display quality and bandwidth across content creation and distribution networks.
The Xilinx DisplayPort interface IP core supports the digital-video-I/O standard introduced by VESA (Video Electronics Standards Association) to provide higher resolution and richer color than traditional VGA or DVI interfaces.
The scalable and extensible open-standard core is fully compliant with the DisplayPort version 1.1a specification. It provides a small design footprint that improves signal integrity and reduces EMI, while providing faster speeds and lower power.
Broadcast developers can integrate the DisplayPort core into Xilinx FPGA-based designs without the added expense and development time of a discrete interface component. Advanced features like content protection using HDCP are also part of the standard DisplayPort interface IP core.
Earlier this year, Xilinx introduced the industry’s first Ethernet Audio/Video Bridging (AVB) Endpoint. Developed in collaboration with Harman International Industries, the Xilinx Ethernet AVB LogiCORE IP enables reliable, high quality of service (QoS) and low latency connectivity for streaming media (audio and video).
The parameterizable core uses cutting-edge programmable technology to easily adapt to changes in the IEEE 802.1 Ethernet AVB standard and support custom features. It is ideally suited to video control applications for professional cameras, mixers and projectors, as well as digital signage for movie theatres, stadiums, shopping malls, etc.
Xilinx recently became a founding member of the AVnu Alliance (www.AVnu.org), an industry forum dedicated to enhancing professional-quality audio/video by promoting emerging IEEE 802.1 AVB networking standards.
Showing posts with label 40nm FPGAs. Show all posts
Showing posts with label 40nm FPGAs. Show all posts
Wednesday, September 23, 2009
Wednesday, July 15, 2009
A guide to FPGAs for communications
MOUNTAIN VIEW, USA: The Linley Group has published A Guide to FPGAs for Communications, First Edition. Authored by Jag Bolaria and Joseph Byrne, the 146-page book comes for a single License: $2,995 (single copy).
Evaluating and comparing FPGAs for communications applications
Despite a downturn in the market in 2008, FPGA revenue continues to grow due to strong demand from communications market customers and OEMs. To ensure long-term growth and stability, FPGA vendors are diversifying their product portfolios. Although only a handful of FPGA vendors are serving the networking and communications segment, the abundance of offerings makes it a challenge to compare and select products.
This report covers a range of commercially available FPGA devices for communications equipment. We provide in-depth coverage of midrange FPGAs and high-end FPGAs for wireless and wireline infrastructure systems as well as an overview of low-end FPGAs.
We provide a roadmap to the complex product lines of market leaders Xilinx (Spartan and Virtex) and Altera (Arria, Stratix, and Cyclone) as well as smaller supplier such as Lattice, Achronix, and Cswitch.
For wireless applications, we cover FPGAs for base stations, including remote radio heads, turbo coding, and modulation. For wireline applications, it covers typical functions performed by FPGAs, including framers, mappers, MACs, and coprocessors.
The report discusses the pros and cons of using FPGAs or alternatives such as ASSPs, ASICs, and processors. For each vendor, we discuss its FPGA products as well as the available IP (intellectual property) for communications applications.
Unlike typical market research, this report provides technology analysis and head-to-head product comparisons. Which FPGAs will win designs and why? Which device is best-suited for which application? How will these vendors be positioned as the market evolves? Only The Linley Group's unique technology analysis can provide this forward-looking view.
We sort out the technology and the vendors
We begin with an extensive overview of this growing market, providing several introductory chapters that define and describe basic concepts and key technologies.
We explore the target markets and applications for FPGAs, followed by an explanation of the common attributes of these products. Following these introductory chapters, the report delivers a complete chapter on the major vendors that offer products in multiple segments.
This handy guide, packed with valuable information, brings you up-to-date on the newest developments in this important market and gives you the analysis you need to help choose a supplier or partner in this field.
"A Guide to FPGAs for Communications" cuts through the vendor hype to analyze each vendor and each product, probe their strengths and weaknesses, and present relevant details in a consistent, easy to compare fashion.
The report provides background on these technologies, with in-depth coverage of the vendors in each segment, including product details and roadmap information where available. Finally, we provide our outlook for the leading vendors in each segment and for the overall market.
Evaluating and comparing FPGAs for communications applications
Despite a downturn in the market in 2008, FPGA revenue continues to grow due to strong demand from communications market customers and OEMs. To ensure long-term growth and stability, FPGA vendors are diversifying their product portfolios. Although only a handful of FPGA vendors are serving the networking and communications segment, the abundance of offerings makes it a challenge to compare and select products.
This report covers a range of commercially available FPGA devices for communications equipment. We provide in-depth coverage of midrange FPGAs and high-end FPGAs for wireless and wireline infrastructure systems as well as an overview of low-end FPGAs.
We provide a roadmap to the complex product lines of market leaders Xilinx (Spartan and Virtex) and Altera (Arria, Stratix, and Cyclone) as well as smaller supplier such as Lattice, Achronix, and Cswitch.
For wireless applications, we cover FPGAs for base stations, including remote radio heads, turbo coding, and modulation. For wireline applications, it covers typical functions performed by FPGAs, including framers, mappers, MACs, and coprocessors.
The report discusses the pros and cons of using FPGAs or alternatives such as ASSPs, ASICs, and processors. For each vendor, we discuss its FPGA products as well as the available IP (intellectual property) for communications applications.
Unlike typical market research, this report provides technology analysis and head-to-head product comparisons. Which FPGAs will win designs and why? Which device is best-suited for which application? How will these vendors be positioned as the market evolves? Only The Linley Group's unique technology analysis can provide this forward-looking view.
We sort out the technology and the vendors
We begin with an extensive overview of this growing market, providing several introductory chapters that define and describe basic concepts and key technologies.
We explore the target markets and applications for FPGAs, followed by an explanation of the common attributes of these products. Following these introductory chapters, the report delivers a complete chapter on the major vendors that offer products in multiple segments.
This handy guide, packed with valuable information, brings you up-to-date on the newest developments in this important market and gives you the analysis you need to help choose a supplier or partner in this field.
"A Guide to FPGAs for Communications" cuts through the vendor hype to analyze each vendor and each product, probe their strengths and weaknesses, and present relevant details in a consistent, easy to compare fashion.
The report provides background on these technologies, with in-depth coverage of the vendors in each segment, including product details and roadmap information where available. Finally, we provide our outlook for the leading vendors in each segment and for the overall market.
Altera Q2 results: Sales up 6pc from prior quarter
SAN JOSE, USA: Altera Corp. announced second quarter sales of $279.2 million, up 6 percent from the first quarter of 2009 and down 22 percent from the second quarter of 2008. New products grew 16 percent sequentially.
Second quarter net income was $47.4 million, $0.16 per diluted share, up from net income of $44.0 million, $0.15 per diluted share, in the first quarter of 2009 and down from $98.0 million, $0.32 per diluted share, in the second quarter of 2008.
Second quarter 2009 tax expense includes an additional $11.5 million charge as a result of a United States court ruling announced during the quarter related to worldwide equity compensation cost sharing. Altera was not a party to the case. The additional tax expense reduced second quarter earnings by $0.04 per diluted share.
Year-to-date cash flow from operating activities was $90.9 million. Altera ended the quarter with $1.3 billion in cash and short-term investments.
Altera’s board of directors has declared a quarterly cash dividend of $0.05 per share payable on September 1, 2009 to stockholders of record on August 10, 2009.
"With a more than doubling of our 40-nm sales and surging 65-nm sales, new products resumed sequential growth and drove our top line results this quarter," said John Daane, president, chief executive officer, and chairman of the board. "Combined, our three 40-nm FPGA families continue to set design win value records. We believe that these newest Altera FPGAs will be our most successful ever."
Several recent accomplishments mark the company’s continuing progress.
With the arrival of the newest members of the Stratix IV GT FPGA family, Altera is now shipping the industry's highest density and highest bandwidth FPGAs.
These 40-nm FPGAs feature 11.3-Gbps transceivers and 530K logic elements (LEs). Stratix IV GT FPGAs support next-generation 40G/100G technologies used in communications systems, military systems, and high-end test equipment.
The unprecedented density and bandwidth in Stratix IV GT FPGAs provide designers of 40G/100G applications the flexibility to incorporate traffic management, packet processing, and their own custom functionality into a single device.
Telecommunications industry OEMs are quickly ramping their new 40G/100G networks to handle HDTV and Internet video broadband content. Stratix IV GT FPGAs deliver a single-chip solution that is optimized specifically to address the demanding bandwidth requirements of this emerging market.
Altera now is shipping its third 40-nm FPGA, the Arria II GX family. Optimized for midrange applications in broadcast, communications, and military systems, the Arria II GX family features fast core performance combined with a cost-optimized 3-Gbps transceiver architecture. With logic densities ranging from 20K–260K LEs, and over 8 Mbits of RAM, this new product offering complements the Stratix IV GX and GT flagship families.
Altera announced the immediate availability of its latest addition to the Cyclone FPGA series — the Cyclone III LS family. This new device family offers the lowest power FPGA that includes security features, including anti-tamper, design security, and design separation.
These devices are the lowest power FPGAs at less than 0.25W of static power for 200K LEs. These devices address challenging security and power requirements in military and industrial markets. The software is publicly available, and the first devices are shipping now.
Business Outlook for the Third Quarter 2009
Sequential Sales Growth Down 1% to 5%
Gross Margin 67% +/- .5%
R&D $67 to $69 million
SG&A $55 to $57 million
Other Income Approximately $0.5 million
Tax Rate 13% to 14%
Second quarter net income was $47.4 million, $0.16 per diluted share, up from net income of $44.0 million, $0.15 per diluted share, in the first quarter of 2009 and down from $98.0 million, $0.32 per diluted share, in the second quarter of 2008.
Second quarter 2009 tax expense includes an additional $11.5 million charge as a result of a United States court ruling announced during the quarter related to worldwide equity compensation cost sharing. Altera was not a party to the case. The additional tax expense reduced second quarter earnings by $0.04 per diluted share.
Year-to-date cash flow from operating activities was $90.9 million. Altera ended the quarter with $1.3 billion in cash and short-term investments.
Altera’s board of directors has declared a quarterly cash dividend of $0.05 per share payable on September 1, 2009 to stockholders of record on August 10, 2009.
"With a more than doubling of our 40-nm sales and surging 65-nm sales, new products resumed sequential growth and drove our top line results this quarter," said John Daane, president, chief executive officer, and chairman of the board. "Combined, our three 40-nm FPGA families continue to set design win value records. We believe that these newest Altera FPGAs will be our most successful ever."
Several recent accomplishments mark the company’s continuing progress.
With the arrival of the newest members of the Stratix IV GT FPGA family, Altera is now shipping the industry's highest density and highest bandwidth FPGAs.
These 40-nm FPGAs feature 11.3-Gbps transceivers and 530K logic elements (LEs). Stratix IV GT FPGAs support next-generation 40G/100G technologies used in communications systems, military systems, and high-end test equipment.
The unprecedented density and bandwidth in Stratix IV GT FPGAs provide designers of 40G/100G applications the flexibility to incorporate traffic management, packet processing, and their own custom functionality into a single device.
Telecommunications industry OEMs are quickly ramping their new 40G/100G networks to handle HDTV and Internet video broadband content. Stratix IV GT FPGAs deliver a single-chip solution that is optimized specifically to address the demanding bandwidth requirements of this emerging market.
Altera now is shipping its third 40-nm FPGA, the Arria II GX family. Optimized for midrange applications in broadcast, communications, and military systems, the Arria II GX family features fast core performance combined with a cost-optimized 3-Gbps transceiver architecture. With logic densities ranging from 20K–260K LEs, and over 8 Mbits of RAM, this new product offering complements the Stratix IV GX and GT flagship families.
Altera announced the immediate availability of its latest addition to the Cyclone FPGA series — the Cyclone III LS family. This new device family offers the lowest power FPGA that includes security features, including anti-tamper, design security, and design separation.
These devices are the lowest power FPGAs at less than 0.25W of static power for 200K LEs. These devices address challenging security and power requirements in military and industrial markets. The software is publicly available, and the first devices are shipping now.
Business Outlook for the Third Quarter 2009
Sequential Sales Growth Down 1% to 5%
Gross Margin 67% +/- .5%
R&D $67 to $69 million
SG&A $55 to $57 million
Other Income Approximately $0.5 million
Tax Rate 13% to 14%
Thursday, June 4, 2009
Altera eases development of 40nm FPGAs with Stratix IV GX FPGA Development Kit
SAN JOSE, USA: Altera Corp. announced availability of the Stratix IV GX FPGA Development Kit.
The kit features hardware and software solutions for the rapid creation of designs using Altera's high-performance 40-nm Stratix IV GX FPGAs with integrated 8.5-Gbps transceivers. The development kit provides an ideal environment for designing and testing high-speed serial interfaces, such as PCI Express (PCIe) Gen2, with up to x8-lane configurations.
The Stratix IV GX FPGA Development Kit offers a complete PCIe Gen2 end-point hardware design package, featuring a PCI-SIG-compliant board and two PCIe Gen2 hard intellectual property (IP) cores in the Stratix IV GX FPGA.
A PCIe high-performance reference design that demonstrates both the software and hardware elements of a PCIe system is available for download on the Altera website.
The two elements of this reference design communicate with drivers created using Jungo's PCIe WinDriver tool forming a fully functional PCIe system. Several other popular protocols are supported by the development kit through the use of high-speed mezzanine cards available from Altera partners, including 10 Gigabit Ethernet (10 GbE), CPRI, OBSAI, SAS/SATA and Serial RapidIO (SRIO).
"We work closely with Altera to ensure our PCIe WinDriver development toolkit complement and work seamlessly with the PCIe hard IP cores in Stratix IV GX FPGAs," said Ophir Herbst, general manager of Jungo's connectivity business unit. "Our proven software drivers in combination with Altera's Stratix IV GX FPGA Development Kit provide our mutual customers a complete environment to design and implement leading-edge PCIe 2.0 x8 solutions."
The Stratix IV GX FPGA Development Kit provides customers with industry-leading innovations within Stratix IV GX FPGAs, including 36 full-duplex transceivers (24 of which operate at up to 8.5 Gbps), two PCIe hard IP blocks, 230K logic elements (LEs) and 13.9 Mbits of embedded memory.
The development kit features a Stratix IV GX EP4SGX230 FPGA-based development board, a one-year license of Quartus II Software, Development Kit Edition and access to Altera's MegaCore IP library including the Nios II Embedded Design Suite.
The kit features hardware and software solutions for the rapid creation of designs using Altera's high-performance 40-nm Stratix IV GX FPGAs with integrated 8.5-Gbps transceivers. The development kit provides an ideal environment for designing and testing high-speed serial interfaces, such as PCI Express (PCIe) Gen2, with up to x8-lane configurations.
The Stratix IV GX FPGA Development Kit offers a complete PCIe Gen2 end-point hardware design package, featuring a PCI-SIG-compliant board and two PCIe Gen2 hard intellectual property (IP) cores in the Stratix IV GX FPGA.
A PCIe high-performance reference design that demonstrates both the software and hardware elements of a PCIe system is available for download on the Altera website.
The two elements of this reference design communicate with drivers created using Jungo's PCIe WinDriver tool forming a fully functional PCIe system. Several other popular protocols are supported by the development kit through the use of high-speed mezzanine cards available from Altera partners, including 10 Gigabit Ethernet (10 GbE), CPRI, OBSAI, SAS/SATA and Serial RapidIO (SRIO).
"We work closely with Altera to ensure our PCIe WinDriver development toolkit complement and work seamlessly with the PCIe hard IP cores in Stratix IV GX FPGAs," said Ophir Herbst, general manager of Jungo's connectivity business unit. "Our proven software drivers in combination with Altera's Stratix IV GX FPGA Development Kit provide our mutual customers a complete environment to design and implement leading-edge PCIe 2.0 x8 solutions."
The Stratix IV GX FPGA Development Kit provides customers with industry-leading innovations within Stratix IV GX FPGAs, including 36 full-duplex transceivers (24 of which operate at up to 8.5 Gbps), two PCIe hard IP blocks, 230K logic elements (LEs) and 13.9 Mbits of embedded memory.
The development kit features a Stratix IV GX EP4SGX230 FPGA-based development board, a one-year license of Quartus II Software, Development Kit Edition and access to Altera's MegaCore IP library including the Nios II Embedded Design Suite.
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