BANGALORE, INDIA: Xilinx Inc. today announced demonstrations of the latest developments in serial connectivity that lower the cost and power of serial digital interfaces and enable the rapid adoption of emerging DisplayPort and Ethernet AVB protocols.
At the heart of these innovations is the Xilinx Broadcast Connectivity Targeted Design Platform that simplifies development of complete broadcast audio and video interface solutions with support for standard definition (SD), high definition (HD), and 3G-SDI standards in a single programmable device. The new capabilities are designed to enable faster time to market and greater product differentiation of professional broadcast systems.
Based on latest generation Virtex-6 and Spartan-6 FPGAs, Xilinx is demonstrating the scalable performance and cost-saving integration advantages of its common platform approach for broadcast audio, video and network connectivity applications.
Xilinx’s broadcast connectivity platform is the first FPGA offering with low-cost, low-power serial transceivers supporting HD video for professional broadcast applications. It also incorporates the new DisplayPort interface LogiCORE IP core from Xilinx enabling transmission and reception of serial digital video for professional and consumer displays.
“SDI is ubiquitous throughout the broadcast industry today. Companies don’t want to spend effort, time, and money on interfaces,” said Ben Runyan, senior manager, Broadcast Marketing at Xilinx.
”Our broadcast connectivity platform and DisplayPort IP simplify interface development, so manufacturers can improve time to market, lower implementation costs, and focus on creating value for their end customers. They can spend time finding innovative ways to differentiate and put limited engineering resources to better use developing advanced, higher quality video processing. These are compelling market advantages, especially for the many companies that already use Xilinx FPGAs in their broadcast systems.”
Live demonstrations of the broadcast connectivity platform and DisplayPort IP are being held at the IBC2009 Exhibition in Amsterdam from September 11th through 15th in Xilinx Booth #10.B30. Xilinx is also showcasing the first fully certified Dolby Digital Professional Encoder on Xilinx FPGAs announced separately today (see related news release).
Broadcast Connectivity Targeted Design Platform
The Xilinx Broadcast Connectivity Targeted Design Platform encompasses all the connectivity elements needed by hardware and software developers to build serial digital interface (SDI) solutions and fully characterize and verify performance for the targeted applications.
Developers can choose Virtex-6 FPGAs for the highest-speed serial connectivity with up to 72 serial transceivers and line rates in excess of 11Gbps for SD/HD/3G-SDI and embedded audio applications, as well as fully integrated support for 10G SDI designs.
For the lowest risk and lowest cost serial connectivity, Spartan-6 FPGAs with up to eight 3.125Gbps transceivers support SD and HD resolution applications with up to 60 percent lower system cost and less than 50 percent the power of previous offerings.
In addition to silicon devices, the broadcast connectivity platform integrates a predictable and intelligently optimized set of design technologies and methodologies that make it easy for broadcast development engineers to implement triple rate SDI designs.
These include Xilinx and third-party domain and application-specific IP cores, complete design environments, and demonstration and reference designs, along with a base set of digital audio/video development boards and industry-standard FPGA Mezzanine Card (FMC) daughter boards.
Xilinx will rollout a series of market-specific development kits for the broadcast connectivity platform so developers can get started quickly using the targeted reference design and development board, and then modify the design as needed to meet the specific feature requirements and design goals of their applications. Targeted applications include cameras, switchers, routers, encoders, professional monitors, and cinema projectors.
Broadcast Connectivity Video Standards
Xilinx continues to drive development of new technologies that reduce the risk and cost of adopting emerging broadcast video standards aimed at improving video display quality and bandwidth across content creation and distribution networks.
The Xilinx DisplayPort interface IP core supports the digital-video-I/O standard introduced by VESA (Video Electronics Standards Association) to provide higher resolution and richer color than traditional VGA or DVI interfaces.
The scalable and extensible open-standard core is fully compliant with the DisplayPort version 1.1a specification. It provides a small design footprint that improves signal integrity and reduces EMI, while providing faster speeds and lower power.
Broadcast developers can integrate the DisplayPort core into Xilinx FPGA-based designs without the added expense and development time of a discrete interface component. Advanced features like content protection using HDCP are also part of the standard DisplayPort interface IP core.
Earlier this year, Xilinx introduced the industry’s first Ethernet Audio/Video Bridging (AVB) Endpoint. Developed in collaboration with Harman International Industries, the Xilinx Ethernet AVB LogiCORE IP enables reliable, high quality of service (QoS) and low latency connectivity for streaming media (audio and video).
The parameterizable core uses cutting-edge programmable technology to easily adapt to changes in the IEEE 802.1 Ethernet AVB standard and support custom features. It is ideally suited to video control applications for professional cameras, mixers and projectors, as well as digital signage for movie theatres, stadiums, shopping malls, etc.
Xilinx recently became a founding member of the AVnu Alliance (www.AVnu.org), an industry forum dedicated to enhancing professional-quality audio/video by promoting emerging IEEE 802.1 AVB networking standards.
Showing posts with label Virtex-6. Show all posts
Showing posts with label Virtex-6. Show all posts
Wednesday, September 23, 2009
Tuesday, June 30, 2009
Cadence, Xilinx simplify SoC development for FPGA targeted design platforms
SAN JOSE, USA: Cadence Design Systems Inc. has teamed with Xilinx to enable delivery of encrypted simulation models of Xilinx intellectual property (IP) in the latest 11.2 release of the Xilinx ISE Design Suite.
The result is an expanded library of design IP and complementary simulation models supported by the Cadence Incisive functional verification platform for the new Xilinx Base Targeted Design Platform.
Used in conjunction with the Open Verification Methodology (OVM) to provide multi-language verification and reuse, this approach can help mutual customers reduce risk and boost schedule predictability and quality.
Xilinx Targeted Design Platforms enable embedded, digital signal processing (DSP) and hardware designers alike to develop FPGA-based systems on chip (SoCs) faster with access to a wide array of silicon devices supported by open standards, common design flows, reusable IP, development tools, and run-time platforms.
Using the high-performance IEEE-standard encryption donated by Cadence, Xilinx is now able to deliver Xilinx SecureIP models to speed development of designs targeting its latest Virtex-6 FPGAs and Spartan-6 FPGAs.
“Our customers have been building larger and more complex FPGA-based SoCs, which require more advanced verification techniques,” said Tom Feist, senior marketing director for ISE Design Suite at Xilinx.
“Working closely with Cadence, we are able to deploy our SecureIP models using the new IEEE encryption with users gaining 2X performance improvements in simulation. When used in conjunction with the OVM, this enables greater verification efficiency throughout the FPGA development ecosystem.”
“Advances in technology announced by Xilinx and Cadence can translate into real time-to-market and quality boosts for our mutual customers,” said Michal Siwinski, marketing group director of Enterprise Verification at Cadence.
“Xilinx Targeted Design Platforms enable rapid creation of SoCs that scale to the sweet spot for both the OVM and the Cadence Incisive functional verification, helping customers to reduce overall project costs and risks.”
The result is an expanded library of design IP and complementary simulation models supported by the Cadence Incisive functional verification platform for the new Xilinx Base Targeted Design Platform.
Used in conjunction with the Open Verification Methodology (OVM) to provide multi-language verification and reuse, this approach can help mutual customers reduce risk and boost schedule predictability and quality.
Xilinx Targeted Design Platforms enable embedded, digital signal processing (DSP) and hardware designers alike to develop FPGA-based systems on chip (SoCs) faster with access to a wide array of silicon devices supported by open standards, common design flows, reusable IP, development tools, and run-time platforms.
Using the high-performance IEEE-standard encryption donated by Cadence, Xilinx is now able to deliver Xilinx SecureIP models to speed development of designs targeting its latest Virtex-6 FPGAs and Spartan-6 FPGAs.
“Our customers have been building larger and more complex FPGA-based SoCs, which require more advanced verification techniques,” said Tom Feist, senior marketing director for ISE Design Suite at Xilinx.
“Working closely with Cadence, we are able to deploy our SecureIP models using the new IEEE encryption with users gaining 2X performance improvements in simulation. When used in conjunction with the OVM, this enables greater verification efficiency throughout the FPGA development ecosystem.”
“Advances in technology announced by Xilinx and Cadence can translate into real time-to-market and quality boosts for our mutual customers,” said Michal Siwinski, marketing group director of Enterprise Verification at Cadence.
“Xilinx Targeted Design Platforms enable rapid creation of SoCs that scale to the sweet spot for both the OVM and the Cadence Incisive functional verification, helping customers to reduce overall project costs and risks.”
Wednesday, June 24, 2009
Mentor's logic and physical synthesis support for Xilinx Virtex-6 and Spartan-6 FPGAs
WILSONVILLE, USA: Mentor Graphics Corp. today announced that its suite of advanced synthesis products support Xilinx Virtex-6 and Spartan-6 FPGAs.
Support for the new Virtex-6 and Spartan-6 FPGA families is available now in the Mentor Graphics Precision RTL and Precision RTL Plus products, providing state-of-the-art logic and physical synthesis to quickly implement complex designs that meet target specifications.
Mentor is the first EDA synthesis provider to offer physical synthesis support for Virtex-6 and Spartan-6 designs. Its push-button physical synthesis capability works in conjunction with the new Xilinx ISE Design Suite 11.2 to provide superior Quality-of-Results (QoR).
Designers can also leverage Precision’s industry-leading SystemVerilog and mixed language support to implement their designs for Virtex-6 and Spartan-6 FPGAs. During the implementation cycle, customers with large designs can reduce run time by utilizing Precision’s unique automatic incremental synthesis and its integration with Xilinx SmartCompile technology.
Xilinx and Mentor Graphics engineering teams worked together to provide a superior implementation methodology. “We’re committed to delivering complete, fully integrated design flows with development environments that reflect the way designers work,” stated Tom Feist, senior marketing director for ISE Design Suite at Xilinx.
“Our collaboration with Mentor Graphics is a key element of this strategy, and ensures a smooth transition for early adopters of our newest device families and targeted design platforms. As a result, our mutual customers can implement their Virtex-6 and Spartan-6 designs faster, while achieving excellent quality-of-results using the Precision-ISE tool flow.”
Virtex-6 and Spartan-6 FPGAs offer over 200 percent more logic capacity and greater than 300 percent increase in register density as compared to previous generations.
“The latest additions to the Xilinx device portfolio provide faster performance at lower cost and with reduction in power consumption,” said Daniel Platzker, product line director, Mentor Graphics Design and Synthesis Division. “Thanks to the joint effort with Xilinx, Precision Synthesis was enhanced to take advantage of Xilinx’s latest silicon architecture, accelerating the time to market of our mutual customers.”
Support for the new Virtex-6 and Spartan-6 FPGA families is available now in the Mentor Graphics Precision RTL and Precision RTL Plus products, providing state-of-the-art logic and physical synthesis to quickly implement complex designs that meet target specifications.
Mentor is the first EDA synthesis provider to offer physical synthesis support for Virtex-6 and Spartan-6 designs. Its push-button physical synthesis capability works in conjunction with the new Xilinx ISE Design Suite 11.2 to provide superior Quality-of-Results (QoR).
Designers can also leverage Precision’s industry-leading SystemVerilog and mixed language support to implement their designs for Virtex-6 and Spartan-6 FPGAs. During the implementation cycle, customers with large designs can reduce run time by utilizing Precision’s unique automatic incremental synthesis and its integration with Xilinx SmartCompile technology.
Xilinx and Mentor Graphics engineering teams worked together to provide a superior implementation methodology. “We’re committed to delivering complete, fully integrated design flows with development environments that reflect the way designers work,” stated Tom Feist, senior marketing director for ISE Design Suite at Xilinx.
“Our collaboration with Mentor Graphics is a key element of this strategy, and ensures a smooth transition for early adopters of our newest device families and targeted design platforms. As a result, our mutual customers can implement their Virtex-6 and Spartan-6 designs faster, while achieving excellent quality-of-results using the Precision-ISE tool flow.”
Virtex-6 and Spartan-6 FPGAs offer over 200 percent more logic capacity and greater than 300 percent increase in register density as compared to previous generations.
“The latest additions to the Xilinx device portfolio provide faster performance at lower cost and with reduction in power consumption,” said Daniel Platzker, product line director, Mentor Graphics Design and Synthesis Division. “Thanks to the joint effort with Xilinx, Precision Synthesis was enhanced to take advantage of Xilinx’s latest silicon architecture, accelerating the time to market of our mutual customers.”
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