BANGALORE, INDIA: Xilinx announced design support for Virtex-6 HXT FPGAs with the 11.3 release of the ISE Design Suite software. Optimized for 40G/100G wired telecommunications and data communications, Virtex-6 HXT FPGAs deliver serial interface technology to designers of ultra-high bandwidth systems with line rates in excess of 11 Gigabits per second (Gbps).
The availability of ISE Design Suite 11.3 gives designers access to a portfolio of connectivity-domain FPGAs spanning the complete spectrum of mainstream, high-end, and ultra high-end serial design applications.
Ultra-high bandwidth to nainstream
In addition to design support for Virtex-6 HXT FPGAs, the ISE 11.3 release expands protocol support for Spartan-6 and Virtex-6 LXT FPGAs and Virtex-6 SXT FPGAs.
XGEMAC, XAUI and RXAUI, Tri-mode Ethernet MAC, Ethernet AVB, SPI4.2 and SPI-3 link are just some of the nearly forty protocols supported by Xilinx serial technology today.
Designers now have their choice of connectivity-optimized devices with embedded low-power transceiver options for meeting their SoC (system-on-a-chip) power, reliability, and protocol requirements for a broad range of markets and applications:
* For mainstream applications, Spartan-6 FPGAs with up to eight GTP 3.125Gbps transceivers satisfy the cost, ease-of-use, and low-power needs of high-volume electronics, such as automotive infotainment systems and high-resolution consumer displays.
* For high-end applications, Virtex-6 LXT and SXT FPGAs with up to 36 GTX 6.5Gbps transceivers and performance margins that exceed the demands of high-speed protocols (e.g., Interlaken and PCIe 2.0) are ideal for multi-protocol systems, such as wireless base stations, switches and routers, and professional video equipment.
* For ultra high-end applications, Virtex-6 HXT FPGAs with up to 72 serial I/O channels (48 GTX and 24 11Gbps GTH) transceivers save over 80 percent in transceiver power compared to solutions with external physical layer (PHY) for 40G/100G applications. These include transponders/muxponders, traffic managers, and packet processors for wired communications; high-performance data encryption engines; advanced medical imaging; and digital video production, editing, and broadcast equipment. Xilinx was the first FPGA vendor to offer a single-chip 100G solution for these applications with the introduction of Virtex-5 TXT FPGAs in 2008.
“Digital convergence in nearly all markets is driving the demand for higher bandwidth connectivity between chips, over backplanes, and across networks. At the same time, parallel I/O has reached its limit and serial solutions once relegated to only high-end designs are becoming ubiquitous,” said Mustafa Veziroglu, vice president of product solutions and management for Xilinx.
“These trends create system complexity, performance, and cost issues that can’t be addressed with a one-size-fits-all approach. Our market-driven focus enables designers to develop and deploy serial solutions faster with the right set of resources, performance, and capabilities for their applications.”
Targeted design platforms increase productivity
Xilinx Targeted Design Platforms enable designers to quickly start SoC development, evaluate Xilinx technology, and rapidly adapt targeted reference designs to the specific feature requirements of their systems.
As part of the Xilinx Base Targeted Design Platform, the Spartan-6 FPGA SP601 and Virtex-6 FPGA ML605 Evaluation Kits provide everything needed to evaluate the serial capabilities in Virtex-6 LXT and Spartan-6 LXT FPGA devices.
Xilinx will roll out its Connectivity Targeted Design Platform later this year with complete targeted reference designs for implementing XAUI to PCIe and Gigabit Ethernet to PCIe bridging solutions, including Direct Memory Access (DMA) cores to achieve optimized bandwidth.
As part of this platform, Virtex-6 HXT devices provide the silicon foundation for the Xilinx deployment of ultra high-speed connectivity development kits and market-specific development kits targeting broadcast video and wired connectivity, packet processing, and traffic management applications.
Five generations of serial technology
Virtex-6 HXT FPGAs extend Xilinx serial technology leadership with the new high-speed serial GTH transceiver. This latest innovation in transceiver technology is part of Xilinx’s holistic approach to serial system design that goes beyond silicon to address system-level connectivity requirements.
Xilinx considers use models, ease-of-use, signal and data integrity, IP, and board designs to enable faster deployment of customer solutions, starting from the architecture phase through product rollout.
With five generations of serial design experience and the most advanced 40 and 45-nanometer process technologies, Xilinx is able to provide designers with the right transceiver for the application at hand.
Showing posts with label Base Targeted Design Platform. Show all posts
Showing posts with label Base Targeted Design Platform. Show all posts
Tuesday, September 22, 2009
Tuesday, June 30, 2009
Cadence, Xilinx simplify SoC development for FPGA targeted design platforms
SAN JOSE, USA: Cadence Design Systems Inc. has teamed with Xilinx to enable delivery of encrypted simulation models of Xilinx intellectual property (IP) in the latest 11.2 release of the Xilinx ISE Design Suite.
The result is an expanded library of design IP and complementary simulation models supported by the Cadence Incisive functional verification platform for the new Xilinx Base Targeted Design Platform.
Used in conjunction with the Open Verification Methodology (OVM) to provide multi-language verification and reuse, this approach can help mutual customers reduce risk and boost schedule predictability and quality.
Xilinx Targeted Design Platforms enable embedded, digital signal processing (DSP) and hardware designers alike to develop FPGA-based systems on chip (SoCs) faster with access to a wide array of silicon devices supported by open standards, common design flows, reusable IP, development tools, and run-time platforms.
Using the high-performance IEEE-standard encryption donated by Cadence, Xilinx is now able to deliver Xilinx SecureIP models to speed development of designs targeting its latest Virtex-6 FPGAs and Spartan-6 FPGAs.
“Our customers have been building larger and more complex FPGA-based SoCs, which require more advanced verification techniques,” said Tom Feist, senior marketing director for ISE Design Suite at Xilinx.
“Working closely with Cadence, we are able to deploy our SecureIP models using the new IEEE encryption with users gaining 2X performance improvements in simulation. When used in conjunction with the OVM, this enables greater verification efficiency throughout the FPGA development ecosystem.”
“Advances in technology announced by Xilinx and Cadence can translate into real time-to-market and quality boosts for our mutual customers,” said Michal Siwinski, marketing group director of Enterprise Verification at Cadence.
“Xilinx Targeted Design Platforms enable rapid creation of SoCs that scale to the sweet spot for both the OVM and the Cadence Incisive functional verification, helping customers to reduce overall project costs and risks.”
The result is an expanded library of design IP and complementary simulation models supported by the Cadence Incisive functional verification platform for the new Xilinx Base Targeted Design Platform.
Used in conjunction with the Open Verification Methodology (OVM) to provide multi-language verification and reuse, this approach can help mutual customers reduce risk and boost schedule predictability and quality.
Xilinx Targeted Design Platforms enable embedded, digital signal processing (DSP) and hardware designers alike to develop FPGA-based systems on chip (SoCs) faster with access to a wide array of silicon devices supported by open standards, common design flows, reusable IP, development tools, and run-time platforms.
Using the high-performance IEEE-standard encryption donated by Cadence, Xilinx is now able to deliver Xilinx SecureIP models to speed development of designs targeting its latest Virtex-6 FPGAs and Spartan-6 FPGAs.
“Our customers have been building larger and more complex FPGA-based SoCs, which require more advanced verification techniques,” said Tom Feist, senior marketing director for ISE Design Suite at Xilinx.
“Working closely with Cadence, we are able to deploy our SecureIP models using the new IEEE encryption with users gaining 2X performance improvements in simulation. When used in conjunction with the OVM, this enables greater verification efficiency throughout the FPGA development ecosystem.”
“Advances in technology announced by Xilinx and Cadence can translate into real time-to-market and quality boosts for our mutual customers,” said Michal Siwinski, marketing group director of Enterprise Verification at Cadence.
“Xilinx Targeted Design Platforms enable rapid creation of SoCs that scale to the sweet spot for both the OVM and the Cadence Incisive functional verification, helping customers to reduce overall project costs and risks.”
Wednesday, June 24, 2009
Xilinx's Base Targeted Design Platform to accelerate development of SoC solutions
BANGALORE, INDIA: Xilinx has released the Xilinx Base Targeted Design Platform aimed at accelerating the development of system-on-chip (SoC) solutions with Xilinx Virtex-6 and Spartan-6 FPGAs.
This base-level targeted design platform combines the 11.2 release of the ISE Design Suite, expanded intellectual property (IP) portfolio, and pre-verified reference designs targeting Virtex-6 or Spartan-6 FPGAs within fully integrated evaluation kits that enable design teams to dramatically shorten development cycles and focus engineering resources on creating greater product differentiation.
The new Virtex-6 FPGA and Spartan-6 FPGA Evaluation Kits are the first in a series of kits Xilinx will offer throughout the year designed to simplify the evaluation and development of SoCs with the latest generation of programmable technologies from Xilinx.
These kits provide all the elements needed to design right out of the box, so both new and experienced FPGA users can achieve the best performance, lowest power, highest bandwidth, and most feature-rich utilization.
In addition, the built-in scalability and plug-in expandability of the base targeted design platform kits lay the foundation for rapid deployment by Xilinx of domain-specific platform kits targeting connectivity, embedded, and digital signal processing (DSP) applications.
Base Targeted Design Platform
The Xilinx Base Targeted Design Platform, or base platform, is tuned to the needs of logic and connectivity designers with evaluation kits that contain the basic building blocks common in virtually all system designs to address a broad set of markets and applications.
By utilizing these key system functions that have been pre-validated to work together in the base platform, designers are able to slash development time by as much as half compared to traditional design methodologies.
Reference designs then guide designers on best practices for integrating custom elements into the base design and implementing advanced features, such as DDR2 and DDR3 memory interfaces, high-speed serial I/O, and on-chip clocking resources. Board schematics and layout files further streamline the design process.
“The Xilinx base platform is a complete FPGA development environment that reflects the way traditional hardware designers work. It gives them immediate access to the new Spartan-6 or Virtex-6 FPGA families, tools, IP, and development boards combined in a way that lets them work smarter,” said Vin Ratford, senior vice president of Worldwide Marketing and Business Development at Xilinx.
“Designers can leverage common IP and reference designs to shorten design time and realize productivity gains that greatly exceed conventional a la carte offerings. By spending less time on developing the infrastructure of an application, designers can spend more time adding value through innovation for their next-generation systems.”
The new 11.2 version of the ISE Design Suite supports both Virtex-6 and Spartan-6 FPGA families and is designed to work with the latest software from Cadence Design Systems, Inc., Mentor Graphics Corporation, and Synopsys, Inc.
The ISE Design Suite 11.2 Editions enable logic, DSP, embedded hardware/software designers and system integrators to take advantage of the new features and capabilities of Virtex-6 and Spartan-6 FPGAs with optimized design environments aligned to the Xilinx Base Targeted Design Platform, as well as to future domain-specific platforms.
Out-of-the Box design
Virtex-6 and Spartan-6 FPGA Evaluation Kits provide a fully integrated base platform that supports a wide range of markets and applications:
Virtex-6 FPGA ML605 Evaluation Kit is a full-featured, highly scalable environment for developing sophisticated system designs with Virtex-6 LX240T FPGA targeted at wired telecom, wireless infrastructure, broadcast and other high performance applications. System-level capabilities supported include high-speed serial transceivers, PCIe Gen2 endpoints, DDR3 memory control, Gigabit Ethernet, and DVI.
Spartan-6 FPGA SP601 Evaluation Kit is a low-cost, entry-level environment for developing consumer, infotainment, video and other cost and power-sensitive applications using the Spartan-6 LX16 FPGA. System design capabilities include DDR2 memory control, flash, Ethernet, general purpose I/O and UART to name a few.
Availability and pricing
The Xilinx Base Targeted Design Platform with Virtex-6 and Spartan-6 FPGAs enables development of SoC applications using the ISE Design Suite 11 and Virtex-6 and Spartan-6 FPGA Evaluation Kits.
The Spartan-6 FPGA SP601 Evaluation Kit is available now for order entry from the Xilinx web site or distributors priced at US$295. The Virtex-6 FPGA ML605 Evaluation Kit will be available for order entry at the end of July priced at $1,995.
A fully featured edition of the ISE Design Suite 11 is available as part of the Virtex-6 FPGA kit with device support limited to the Vitex-6 LX240T-FF1156. The Spartan-6 FPGA kit includes the ISE Design Suite 11 WebPACK software.
The ISE Design Suite is available separately with full device support for a list price starting at US$2,995 for the Logic Edition. Customers can download full-featured 30-day evaluation versions of ISE Design Suite 11 from the Xilinx web site at no charge.
This base-level targeted design platform combines the 11.2 release of the ISE Design Suite, expanded intellectual property (IP) portfolio, and pre-verified reference designs targeting Virtex-6 or Spartan-6 FPGAs within fully integrated evaluation kits that enable design teams to dramatically shorten development cycles and focus engineering resources on creating greater product differentiation.
The new Virtex-6 FPGA and Spartan-6 FPGA Evaluation Kits are the first in a series of kits Xilinx will offer throughout the year designed to simplify the evaluation and development of SoCs with the latest generation of programmable technologies from Xilinx.
These kits provide all the elements needed to design right out of the box, so both new and experienced FPGA users can achieve the best performance, lowest power, highest bandwidth, and most feature-rich utilization.
In addition, the built-in scalability and plug-in expandability of the base targeted design platform kits lay the foundation for rapid deployment by Xilinx of domain-specific platform kits targeting connectivity, embedded, and digital signal processing (DSP) applications.
Base Targeted Design Platform
The Xilinx Base Targeted Design Platform, or base platform, is tuned to the needs of logic and connectivity designers with evaluation kits that contain the basic building blocks common in virtually all system designs to address a broad set of markets and applications.
By utilizing these key system functions that have been pre-validated to work together in the base platform, designers are able to slash development time by as much as half compared to traditional design methodologies.
Reference designs then guide designers on best practices for integrating custom elements into the base design and implementing advanced features, such as DDR2 and DDR3 memory interfaces, high-speed serial I/O, and on-chip clocking resources. Board schematics and layout files further streamline the design process.
“The Xilinx base platform is a complete FPGA development environment that reflects the way traditional hardware designers work. It gives them immediate access to the new Spartan-6 or Virtex-6 FPGA families, tools, IP, and development boards combined in a way that lets them work smarter,” said Vin Ratford, senior vice president of Worldwide Marketing and Business Development at Xilinx.
“Designers can leverage common IP and reference designs to shorten design time and realize productivity gains that greatly exceed conventional a la carte offerings. By spending less time on developing the infrastructure of an application, designers can spend more time adding value through innovation for their next-generation systems.”
The new 11.2 version of the ISE Design Suite supports both Virtex-6 and Spartan-6 FPGA families and is designed to work with the latest software from Cadence Design Systems, Inc., Mentor Graphics Corporation, and Synopsys, Inc.
The ISE Design Suite 11.2 Editions enable logic, DSP, embedded hardware/software designers and system integrators to take advantage of the new features and capabilities of Virtex-6 and Spartan-6 FPGAs with optimized design environments aligned to the Xilinx Base Targeted Design Platform, as well as to future domain-specific platforms.
Out-of-the Box design
Virtex-6 and Spartan-6 FPGA Evaluation Kits provide a fully integrated base platform that supports a wide range of markets and applications:
Virtex-6 FPGA ML605 Evaluation Kit is a full-featured, highly scalable environment for developing sophisticated system designs with Virtex-6 LX240T FPGA targeted at wired telecom, wireless infrastructure, broadcast and other high performance applications. System-level capabilities supported include high-speed serial transceivers, PCIe Gen2 endpoints, DDR3 memory control, Gigabit Ethernet, and DVI.
Spartan-6 FPGA SP601 Evaluation Kit is a low-cost, entry-level environment for developing consumer, infotainment, video and other cost and power-sensitive applications using the Spartan-6 LX16 FPGA. System design capabilities include DDR2 memory control, flash, Ethernet, general purpose I/O and UART to name a few.
Availability and pricing
The Xilinx Base Targeted Design Platform with Virtex-6 and Spartan-6 FPGAs enables development of SoC applications using the ISE Design Suite 11 and Virtex-6 and Spartan-6 FPGA Evaluation Kits.
The Spartan-6 FPGA SP601 Evaluation Kit is available now for order entry from the Xilinx web site or distributors priced at US$295. The Virtex-6 FPGA ML605 Evaluation Kit will be available for order entry at the end of July priced at $1,995.
A fully featured edition of the ISE Design Suite 11 is available as part of the Virtex-6 FPGA kit with device support limited to the Vitex-6 LX240T-FF1156. The Spartan-6 FPGA kit includes the ISE Design Suite 11 WebPACK software.
The ISE Design Suite is available separately with full device support for a list price starting at US$2,995 for the Logic Edition. Customers can download full-featured 30-day evaluation versions of ISE Design Suite 11 from the Xilinx web site at no charge.
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