WILSONVILLE, USA: Mentor Graphics Corp. announced that its low power RTL-to-GDSII tool flow has been included in Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) Reference Flow 10.0. TSMC and Mentor worked together nearly a year to validate and deliver a robust set of tools with proven support for the Unified Power Format (UPF).
“In addition to expanding the Mentor reference flow to add both functional verification and implementation technologies, Mentor is addressing new challenges such as low power,” said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.
The Mentor low power track includes the 0-In CDC, Questa, FormalPro, Olympus-SoC and TestKompress tools.
The 0-In CDC tool provides a three-fold verification approach for clock domain crossings, checking for appropriate synchronization through structural analysis, protocol verification, and accurate simulation of metastability effects.
The Questa platform enables early verification and evaluation of power architectures starting with RTL, through automatic insertion of power management logic based on UPF specifications. The Questa platform provides silicon-accurate simulation of isolation and retention protocols during power down/up, non-operational bias modes, and dynamic voltage scaling, as well as static and dynamic checks for power management functional correctness that pinpoint any failures to simplify debugging.
The FormalPro tool verifies the pre- and post-routed netlists against the RTL + UPF specification from which they were derived, to ensure that retention registers, isolation buffers, and level shifters are equivalent, as well as verifying logic equivalence.
The Olympus-SoC implementation system provides true multi-corner multi-mode (MCMM) optimization of timing, power, signal integrity and die size, and MCMM clock tree synthesis and optimization. The Olympus-SoC system provides UPF hierarchical low power automation with both top-down and bottom-up flows. It also provides a completely automated, multi-voltage flow with support for Dynamic Voltage and Frequency Scaling (DVFS) handles varying supply voltages and clock frequencies, as well as special power-related cells such as level shifters, isolation cells, and MTCMOS switches.
The TestKompress ATPG tool reduces power dissipation during all phases of scan test using a constant-fill decompressor, which reduces unnecessary logic transitions, and power-aware control of clock gates.
“Mutual customers of Mentor and TSMC continue to push the design envelope to create complex SoCs that require adoption of advanced, low-power technologies,” said John Lenyo, Mentor Graphics functional verification division general manager. “Our collaboration with TSMC gives design teams access to a comprehensive low-power flow that addresses the low-power challenges from design inception to tapeout.”
Showing posts with label Mentor Graphics. Show all posts
Showing posts with label Mentor Graphics. Show all posts
Tuesday, September 22, 2009
Tuesday, September 15, 2009
Mentor Graphics, Applied Materials deploy OASIS.MASK open data standard for higher efficiency mask manufacturing
WILSONVILLE & SANTA CLARA, USA: Mentor Graphics Corp. and Applied Materials Inc. announced an important milestone in the adoption of open data formats for mask manufacturing. The first volume production deployment of the new OASIS.MASK (SEMI standard P44) format was performed on Applied’s Aera2 advanced mask inspection systems using Mentor Graphics’ mask data preparation software technology.
The new format greatly simplifies the task of creating the complex, high fidelity photomasks that are vital to fabricating semiconductor devices at 32nm and below technology nodes.
OASIS.MASK (Open Artwork System Interchange Standard for Photomasks) is an open standard interchange format used to represent and express chip level physical and mask layout data.
The OASIS.MASK format reduces the size of mask data files by approximately one-half, eliminating the file transfer bottleneck between software tools and mask manufacturing equipment –- a key benefit with today’s near-terabyte file sizes. As an open interface, it enables the same data file to be used for pattern generation, metrology and inspection, simplifying mask manufacturing process flows by eliminating complex format conversion steps.
“We are working with Mentor Graphics, a leader in the adoption of OASIS standards, to improve efficiency up and down the mask-making value chain by encouraging the adoption of open standards,” said Tom St. Dennis, senior vice president and general manager of Applied’s Silicon Systems Group.
“By incorporating the OASIS.MASK format in our Aera2 systems, we can continue to provide the most competitive, high throughput, die-to-database inspection solutions for our most advanced customers.”
“Applied Materials’ decision to implement OASIS.MASK in their products shows the value of OASIS mask data format,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics.
“Mentor’s experience with OASIS goes back to the development of the original OASIS format (SEMI standard P39), so incorporating our technology into Aera2 was a logical extension of our product efforts. The use of OASIS.MASK for mask manufacturing is fully supported by the Calibre platform in the Calibre FRACTUREv, Calibre MDPverify, and Calibre MDPview products, which are all available today.”
Applied and Mentor will showcase their pioneering deployment of OASIS.MASK in a production environment at SPIE Photomask 2009, the mask-making industry’s premier technical symposium, to be held September 14-17 in Monterey, California.
The new format greatly simplifies the task of creating the complex, high fidelity photomasks that are vital to fabricating semiconductor devices at 32nm and below technology nodes.
OASIS.MASK (Open Artwork System Interchange Standard for Photomasks) is an open standard interchange format used to represent and express chip level physical and mask layout data.
The OASIS.MASK format reduces the size of mask data files by approximately one-half, eliminating the file transfer bottleneck between software tools and mask manufacturing equipment –- a key benefit with today’s near-terabyte file sizes. As an open interface, it enables the same data file to be used for pattern generation, metrology and inspection, simplifying mask manufacturing process flows by eliminating complex format conversion steps.
“We are working with Mentor Graphics, a leader in the adoption of OASIS standards, to improve efficiency up and down the mask-making value chain by encouraging the adoption of open standards,” said Tom St. Dennis, senior vice president and general manager of Applied’s Silicon Systems Group.
“By incorporating the OASIS.MASK format in our Aera2 systems, we can continue to provide the most competitive, high throughput, die-to-database inspection solutions for our most advanced customers.”
“Applied Materials’ decision to implement OASIS.MASK in their products shows the value of OASIS mask data format,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics.
“Mentor’s experience with OASIS goes back to the development of the original OASIS format (SEMI standard P39), so incorporating our technology into Aera2 was a logical extension of our product efforts. The use of OASIS.MASK for mask manufacturing is fully supported by the Calibre platform in the Calibre FRACTUREv, Calibre MDPverify, and Calibre MDPview products, which are all available today.”
Applied and Mentor will showcase their pioneering deployment of OASIS.MASK in a production environment at SPIE Photomask 2009, the mask-making industry’s premier technical symposium, to be held September 14-17 in Monterey, California.
Friday, September 4, 2009
Mentor Graphics launches Precise-IP vendor-independent IP platform for FPGA design
WILSONVILLE, USA: Mentor Graphics Corp. announced the Precise-IP — a new vendor-independent IP (Intellectual Property) platform as part of the Mentor Graphics Precision Synthesis product line.
The platform includes vendor-independent configurable IP from Mentor Graphics and links to categorized third-party IP from leading vendors. The third-party IP was certified by the respective IP vendor to ensure high quality of results with the Precision Synthesis technology.
As part of a complete vendor-independent IP methodology, the Precise-IP platform contains a library of configurable IP for use with the Precision Synthesis solution. The easy-to-use wizard creates frequently used synthesizable IP based on user parameter settings. The configuration parameters are then validated by a self-checking GUI to ensure configuration conformance. The IP cores are optimized for best quality of results (QoR) across FPGA families.
A comprehensive catalog of complex cores — such as processors, interface controllers, and application-specific cores — are provided by leading IP vendors and available for multiple FPGA families. Participating vendors of the Precise-IP Partner Program are ARC, ARM, Aeroflex Gaisler, CAST, Eureka Technology, Helion, IPextreme, Innovative Logic, and OptNgn. Mentor Graphics continues to add new configurable IP and new partners to expand its catalog of supported cores.
“Mentor’s Precise-IP is a big win for design engineers,” stated Gary Smith, principal of Gary Smith EDA. “Non-proprietary, commercial IP that is vendor independent gives the FPGA designer the freedom to select the device that delivers the best results.”
“An effective vendor-neutral design methodology requires vendor-independent IP to complement EDA design tools,” stated Daniel Platzker, Mentor Graphics FPGA division product line director. “With Precision Synthesis’ Precise-IP platform, designers can easily create widely used IP and find high-quality cores from leading IP vendors, thus retaining the flexibility to retarget their designs to different FPGA silicon as the need arises.”
The Precise-IP platform is available within the Precision Synthesis product.
The platform includes vendor-independent configurable IP from Mentor Graphics and links to categorized third-party IP from leading vendors. The third-party IP was certified by the respective IP vendor to ensure high quality of results with the Precision Synthesis technology.
As part of a complete vendor-independent IP methodology, the Precise-IP platform contains a library of configurable IP for use with the Precision Synthesis solution. The easy-to-use wizard creates frequently used synthesizable IP based on user parameter settings. The configuration parameters are then validated by a self-checking GUI to ensure configuration conformance. The IP cores are optimized for best quality of results (QoR) across FPGA families.
A comprehensive catalog of complex cores — such as processors, interface controllers, and application-specific cores — are provided by leading IP vendors and available for multiple FPGA families. Participating vendors of the Precise-IP Partner Program are ARC, ARM, Aeroflex Gaisler, CAST, Eureka Technology, Helion, IPextreme, Innovative Logic, and OptNgn. Mentor Graphics continues to add new configurable IP and new partners to expand its catalog of supported cores.
“Mentor’s Precise-IP is a big win for design engineers,” stated Gary Smith, principal of Gary Smith EDA. “Non-proprietary, commercial IP that is vendor independent gives the FPGA designer the freedom to select the device that delivers the best results.”
“An effective vendor-neutral design methodology requires vendor-independent IP to complement EDA design tools,” stated Daniel Platzker, Mentor Graphics FPGA division product line director. “With Precision Synthesis’ Precise-IP platform, designers can easily create widely used IP and find high-quality cores from leading IP vendors, thus retaining the flexibility to retarget their designs to different FPGA silicon as the need arises.”
The Precise-IP platform is available within the Precision Synthesis product.
Monday, August 24, 2009
Mentor Graphics reports strong bookings in Q2
WILSONVILLE, USA: Mentor Graphics Corp. recently announced results for the fiscal second quarter 2010, ending July 31, 2009. For the quarter, the company reported revenues of $182.6 million, non-GAAP earnings per share of $.02, and a GAAP loss per share of $.22. Bookings for the quarter rose 15 percent over the prior fiscal second quarter.
“The quarter’s strong bookings performance was driven by new customers and new products. Though the business climate is still difficult, we did see strong sequential increases in consulting and distributor bookings during the quarter, both signs we take as indicators of an improving customer environment,” said Walden C. Rhines, CEO and chairman of Mentor Graphics.
“The company continues to build its strength in new markets, expanding its electronic system level design (ESL) and low-power product offerings during the quarter. Taiwan Semiconductor Manufacturing Co.'s (TSMC) inclusion of a full Mentor low-power implementation flow in their Reference Flow 10.0 further strengthens the company’s position in the physical implementation market.”
During the quarter, Mentor released a new version of its Catapult C synthesis tool enabling full chip synthesis, including control logic, and better power management. The company also released its PADS 9.0 printed circuit board flow which incorporated new collaboration, manufacturing and analysis tools.
At the Design Automation Conference (DAC) in July, Mentor advanced its full system low-power strategy by launching its VistaTM platform which enables engineers to model power early in the design cycle. Also at DAC, Mentor and its partners detailed the company’s multi-operating system, multi-core embedded system strategy featuring Linux, Android, and Nucleus operating systems.
Last Tuesday, the company closed its acquisition of LogicVision announced during the second quarter. The acquisition strengthens the company’s market-leading position in the design-for-test market by combining LogicVision’s strength in built-in-self-test (BIST) with the company’s strength in automated test pattern generation (ATPG) and embedded test pattern compression technology.
“With a tight rein on costs and the beginnings of an improving economic climate, the company performed better than we were confident to predict,” said Gregory K. Hinckley, president of Mentor Graphics. “The contract renewals we had in the quarter were at similar levels to their previous contract values, which was an improvement from the first quarter’s renewal rates. And despite acquisitions, headcount and operating expenses are down from a year ago, as the company continued to attack costs like travel, facilities and outside services.”
Outlook
For the third quarter fiscal 2010, the company expects revenue of about $183 million, non-GAAP earnings per share of about $.01 and a GAAP loss per share of about $.19.
“The quarter’s strong bookings performance was driven by new customers and new products. Though the business climate is still difficult, we did see strong sequential increases in consulting and distributor bookings during the quarter, both signs we take as indicators of an improving customer environment,” said Walden C. Rhines, CEO and chairman of Mentor Graphics.
“The company continues to build its strength in new markets, expanding its electronic system level design (ESL) and low-power product offerings during the quarter. Taiwan Semiconductor Manufacturing Co.'s (TSMC) inclusion of a full Mentor low-power implementation flow in their Reference Flow 10.0 further strengthens the company’s position in the physical implementation market.”
During the quarter, Mentor released a new version of its Catapult C synthesis tool enabling full chip synthesis, including control logic, and better power management. The company also released its PADS 9.0 printed circuit board flow which incorporated new collaboration, manufacturing and analysis tools.
At the Design Automation Conference (DAC) in July, Mentor advanced its full system low-power strategy by launching its VistaTM platform which enables engineers to model power early in the design cycle. Also at DAC, Mentor and its partners detailed the company’s multi-operating system, multi-core embedded system strategy featuring Linux, Android, and Nucleus operating systems.
Last Tuesday, the company closed its acquisition of LogicVision announced during the second quarter. The acquisition strengthens the company’s market-leading position in the design-for-test market by combining LogicVision’s strength in built-in-self-test (BIST) with the company’s strength in automated test pattern generation (ATPG) and embedded test pattern compression technology.
“With a tight rein on costs and the beginnings of an improving economic climate, the company performed better than we were confident to predict,” said Gregory K. Hinckley, president of Mentor Graphics. “The contract renewals we had in the quarter were at similar levels to their previous contract values, which was an improvement from the first quarter’s renewal rates. And despite acquisitions, headcount and operating expenses are down from a year ago, as the company continued to attack costs like travel, facilities and outside services.”
Outlook
For the third quarter fiscal 2010, the company expects revenue of about $183 million, non-GAAP earnings per share of about $.01 and a GAAP loss per share of about $.19.
Wednesday, August 19, 2009
Mentor Graphics acquires LogicVision
WILSONVILLE & SAN JOSE, USA: Mentor Graphics Corp. and LogicVision Inc. announced that LogicVision stockholders have voted to approve, and the parties have closed, the previously-announced merger. Former LogicVision stockholders will receive 0.2006 share of Mentor Graphics common stock in exchange for each share of LogicVision common stock.
LogicVision is a leading provider of Built-in-Self-Test (BIST) technologies for testing today’s System-on-Chip (SoC) designs. The combination of Mentor’s industry-leading Automated Test Pattern Generation (ATPG) and embedded test pattern compression technology, and LogicVision’s BIST products, enables Mentor to provide customers with comprehensive and integrated solutions to address the growing complexity of silicon test.
“Our customers are facing significant new test challenges as they move to each new technology node,” said Walden C. Rhines, chairman and CEO, Mentor Graphics. “We believe the combination of the Mentor and LogicVision silicon test solutions will enable them to address all aspects of their full-chip test requirements with a unified test platform.
“Combining our industry-leading ATPG and embedded compression with the LogicVision memory and logic BIST technologies enables our customers to maintain high product quality and test standards, while reducing manufacturing costs and improving profitability.”
“The partnership we started over two years ago that integrated the Mentor TestKompress ATPG and compression tool with the LogicVision ScanBurst at-speed scan technology paved the way for a successful merger of the organizations,” said James Healy, former president and CEO of LogicVision.
“We now intend to build on that cooperation to address the critical challenges of silicon test, such as cost-effective nanometer SoC testing, extreme pattern compression, advanced at-speed testing, embedded memory test and repair, high-speed I/O testing, and leveraging test data for rapid yield analysis.”
The combined silicon test solutions from Mentor Graphics and LogicVision provide customers with the best-in-class technologies to address the test challenges of the digital logic and memory portions of their designs, as well as the increasingly common high-speed SerDes analog and DDR-based interfaces.
LogicVision’s unique test bring-up and silicon characterization tools -- combined with Mentor’s leading failure diagnosis capabilities —- will also help customers accelerate yield ramps, reducing time-to-volume.
LogicVision resources will be fully integrated into the Silicon Test Solutions group within the Mentor Design-to-Silicon division led by vice president and general manager, Joseph Sawicki. The division also includes the Olympus-SoC place-and-route, and the Calibre physical verification, Design for Manufacturing and Resolution Enhancement Technology product groups.
LogicVision is a leading provider of Built-in-Self-Test (BIST) technologies for testing today’s System-on-Chip (SoC) designs. The combination of Mentor’s industry-leading Automated Test Pattern Generation (ATPG) and embedded test pattern compression technology, and LogicVision’s BIST products, enables Mentor to provide customers with comprehensive and integrated solutions to address the growing complexity of silicon test.
“Our customers are facing significant new test challenges as they move to each new technology node,” said Walden C. Rhines, chairman and CEO, Mentor Graphics. “We believe the combination of the Mentor and LogicVision silicon test solutions will enable them to address all aspects of their full-chip test requirements with a unified test platform.
“Combining our industry-leading ATPG and embedded compression with the LogicVision memory and logic BIST technologies enables our customers to maintain high product quality and test standards, while reducing manufacturing costs and improving profitability.”
“The partnership we started over two years ago that integrated the Mentor TestKompress ATPG and compression tool with the LogicVision ScanBurst at-speed scan technology paved the way for a successful merger of the organizations,” said James Healy, former president and CEO of LogicVision.
“We now intend to build on that cooperation to address the critical challenges of silicon test, such as cost-effective nanometer SoC testing, extreme pattern compression, advanced at-speed testing, embedded memory test and repair, high-speed I/O testing, and leveraging test data for rapid yield analysis.”
The combined silicon test solutions from Mentor Graphics and LogicVision provide customers with the best-in-class technologies to address the test challenges of the digital logic and memory portions of their designs, as well as the increasingly common high-speed SerDes analog and DDR-based interfaces.
LogicVision’s unique test bring-up and silicon characterization tools -- combined with Mentor’s leading failure diagnosis capabilities —- will also help customers accelerate yield ramps, reducing time-to-volume.
LogicVision resources will be fully integrated into the Silicon Test Solutions group within the Mentor Design-to-Silicon division led by vice president and general manager, Joseph Sawicki. The division also includes the Olympus-SoC place-and-route, and the Calibre physical verification, Design for Manufacturing and Resolution Enhancement Technology product groups.
Thursday, August 13, 2009
Mentor Graphics, KACST to develop electronics design technology
WILSONVILLE, USA: Mentor Graphics and King Abdulaziz City for Science and Technology (KACST) in Saudi Arabia have announced their co-operation for the promotion and development of Electronics Design Technology in Saudi Arabia.
This co-operation is based on the agreement signed by both parties to establish the Advanced Microelectronics Technology Center (AMTC) at KACST. This Center will contribute to the Saudi National Strategic Plan through the Advanced Technology Program (ATP), the Professional Training Program (PTP) and the Incubation Support Program (ISP).
These programs are the first steps of cooperation between KACST and Mentor Graphics, with more programs running under KACST’s AMTC to be initiated later. Under the initial agreement, Mentor Graphics will provide comprehensive design automation software as well as consulting and training services.
As part of the agreement, the company will cooperate with government bodies, as well as extend its university outreach program in Saudi Arabia.
“The Kingdom of Saudi Arabia has developed a strategic national science and technology plan to be carried out over the next 20 years. KACST was assigned the responsibility of planning and managing the execution of the Science and Technology plan. This plan promotes and encourages research in many areas, a very important one being advanced technology in microelectronics,” explained Prince Turki Saud Mohamed Al-Saud, Vice President for research at KACST.
“Mentor Graphics, one of the leading companies in the Electronics Design Automation (EDA) industry in the region through its Egyptian Development Center established in 1995, is pleased to be able to help build the Advanced Microelectronics Technology Center (AMTC). This co-operation framework will promote and encourage electronics design in the Kingdom of Saudi Arabia,” said Gregory K. Hinckley, President of Mentor Graphics.
Dr. Sami Alhamidi, the Electronics, Communications and Photonics Program Director at KACST, emphasizes: “In order to initiate and establish an innovation cycle in the field of electronics design, the electronics community in the kingdom must become proficient with state-of-the-art electronic technologies.
"Therefore, one of the principal drivers for the successful implementation of the microelectronics R&D plan is the cooperation with world-class global companies specialized in EDA technologies such as Mentor Graphics.”
“To support KACST in building their expertise in electronic design methodologies, Mentor Graphics will provide access to certain expertise that already exists in its branch in Egypt. Our consulting division will also provide its knowledge and experience to selected teams at KACST and will cooperate on research in advanced technology areas with KACST and local universities,” explains Dr. Hazem Eltahawy, Managing Director of the Egypt operation.
This co-operation is based on the agreement signed by both parties to establish the Advanced Microelectronics Technology Center (AMTC) at KACST. This Center will contribute to the Saudi National Strategic Plan through the Advanced Technology Program (ATP), the Professional Training Program (PTP) and the Incubation Support Program (ISP).
These programs are the first steps of cooperation between KACST and Mentor Graphics, with more programs running under KACST’s AMTC to be initiated later. Under the initial agreement, Mentor Graphics will provide comprehensive design automation software as well as consulting and training services.
As part of the agreement, the company will cooperate with government bodies, as well as extend its university outreach program in Saudi Arabia.
“The Kingdom of Saudi Arabia has developed a strategic national science and technology plan to be carried out over the next 20 years. KACST was assigned the responsibility of planning and managing the execution of the Science and Technology plan. This plan promotes and encourages research in many areas, a very important one being advanced technology in microelectronics,” explained Prince Turki Saud Mohamed Al-Saud, Vice President for research at KACST.
“Mentor Graphics, one of the leading companies in the Electronics Design Automation (EDA) industry in the region through its Egyptian Development Center established in 1995, is pleased to be able to help build the Advanced Microelectronics Technology Center (AMTC). This co-operation framework will promote and encourage electronics design in the Kingdom of Saudi Arabia,” said Gregory K. Hinckley, President of Mentor Graphics.
Dr. Sami Alhamidi, the Electronics, Communications and Photonics Program Director at KACST, emphasizes: “In order to initiate and establish an innovation cycle in the field of electronics design, the electronics community in the kingdom must become proficient with state-of-the-art electronic technologies.
"Therefore, one of the principal drivers for the successful implementation of the microelectronics R&D plan is the cooperation with world-class global companies specialized in EDA technologies such as Mentor Graphics.”
“To support KACST in building their expertise in electronic design methodologies, Mentor Graphics will provide access to certain expertise that already exists in its branch in Egypt. Our consulting division will also provide its knowledge and experience to selected teams at KACST and will cooperate on research in advanced technology areas with KACST and local universities,” explains Dr. Hazem Eltahawy, Managing Director of the Egypt operation.
Friday, August 7, 2009
Mentor's Questa multi-view verification components library supports HDMI
WILSONVILLE, USA: Mentor Graphics Corp. announced that the Questa Multi-view Verification Components (MVC) library now supports HDMI (High-Definition Multimedia Interface), a compact audio/video interface for transmitting uncompressed digital data.
The Questa MVC library helps speed up functional verification of integrated circuits (ICs) incorporating HDMI interface logic, and drastically improves verification coverage for today’s complex multi-media platforms.
Lowering barriers to mixed-abstraction verification
The complexity of today’s SoC verification environments often requires designers to spend valuable time building and verifying multiple, and usually incompatible, verification models of a single block to support system-level, TLM-level and RTL-level verification.
This lack of consistency prevents teams from easily moving up and down in abstraction and maximizing verification effectiveness.
Mentor’s unique Questa Multi-view Verification Components can connect to any level of abstraction from system to gates –- ensuring consistent model behavior and giving the verification team more options to improve performance and increase coverage. The multi-view technology greatly reduces debug time through recognition of protocol stacks.
This allows simulation results, from RTL verification, to be viewed as sequences of initiated transactions and responses, with the RTL signal activity correlated to a higher level transaction view of activity.
Each protocol, such as the HDMI, supported by the Questa MVC library includes a verification plan with full coverage metrics that integrates with the Questa Verification Management system. The verification plan easily incorporates into hierarchical full-chip verification plans.
Questa Verification Management provides visibility into the status of the verification process by providing correlation of coverage metrics to the verification plan.
“The MVC library, which is written in SystemVerilog, supports OVM 2.0 with stimulus generation, reference checking, monitoring and functional coverage for popular protocols such as HDMI,” said Stephen Bailey, director of product marketing for the Design Verification Technology Division of Mentor.
“This enables fast development of tests for all aspects of standard protocols for directed and constrained-random verification environments.”
Questa MVC support for HDMI is available immediately.
Questa functional verification platform
The Questa functional verification platform combines high-performance and high-capacity with the most comprehensive verification capabilities in the industry.
Assertion-based Verification (ABV), intelligent testbench automation, Multi-view Verification Components (MVC), and Coverage-driven Verification (CDV) are supported natively by the Questa platform’s high-performance assertion engine; a modern, high-performance constraint solver; and extensive functional coverage features, including verification management leveraging the Unified Coverage Database (UCDB).
Verification of low power design functionality can be proven in an RTL environment with power-aware functional verification. This full set of advanced verification functionality is enabled by a flexible Open Verification Methodology (OVM 2.0) that delivers unrivaled language and feature support in any design and verification flow.
The Questa MVC library helps speed up functional verification of integrated circuits (ICs) incorporating HDMI interface logic, and drastically improves verification coverage for today’s complex multi-media platforms.
Lowering barriers to mixed-abstraction verification
The complexity of today’s SoC verification environments often requires designers to spend valuable time building and verifying multiple, and usually incompatible, verification models of a single block to support system-level, TLM-level and RTL-level verification.
This lack of consistency prevents teams from easily moving up and down in abstraction and maximizing verification effectiveness.
Mentor’s unique Questa Multi-view Verification Components can connect to any level of abstraction from system to gates –- ensuring consistent model behavior and giving the verification team more options to improve performance and increase coverage. The multi-view technology greatly reduces debug time through recognition of protocol stacks.
This allows simulation results, from RTL verification, to be viewed as sequences of initiated transactions and responses, with the RTL signal activity correlated to a higher level transaction view of activity.
Each protocol, such as the HDMI, supported by the Questa MVC library includes a verification plan with full coverage metrics that integrates with the Questa Verification Management system. The verification plan easily incorporates into hierarchical full-chip verification plans.
Questa Verification Management provides visibility into the status of the verification process by providing correlation of coverage metrics to the verification plan.
“The MVC library, which is written in SystemVerilog, supports OVM 2.0 with stimulus generation, reference checking, monitoring and functional coverage for popular protocols such as HDMI,” said Stephen Bailey, director of product marketing for the Design Verification Technology Division of Mentor.
“This enables fast development of tests for all aspects of standard protocols for directed and constrained-random verification environments.”
Questa MVC support for HDMI is available immediately.
Questa functional verification platform
The Questa functional verification platform combines high-performance and high-capacity with the most comprehensive verification capabilities in the industry.
Assertion-based Verification (ABV), intelligent testbench automation, Multi-view Verification Components (MVC), and Coverage-driven Verification (CDV) are supported natively by the Questa platform’s high-performance assertion engine; a modern, high-performance constraint solver; and extensive functional coverage features, including verification management leveraging the Unified Coverage Database (UCDB).
Verification of low power design functionality can be proven in an RTL environment with power-aware functional verification. This full set of advanced verification functionality is enabled by a flexible Open Verification Methodology (OVM 2.0) that delivers unrivaled language and feature support in any design and verification flow.
Thursday, August 6, 2009
HiSilicon adopts Mentor's Veloce hardware emulator
WILSONVILLE, USA: Mentor Graphics Corp. announced that HiSilicon, the ASIC design centre for Huawei Technologies and provider of solutions for communication networks and digital media, has adopted Mentor’s Veloce for the complete system-level verification of its next-generation SoC chips, including wireless chip sets.
HiSilicon chose Veloce due to its superior debug capabilities, performance, accuracy, and extensive portfolio of iSolveTM vertical market in-circuit emulation (ICE) solutions, for the verification of wireless, networking, and multimedia designs.
“HiSilicon faces significant challenges in meeting time-to-market goals, performance requirements, and reducing the risks involved in the integration of our advanced SoC’s for communication networks and multimedia applications,” stated Teresa He, vice president semiconductor line, HiSilicon Technologies Co. Ltd. “The use of Veloce for the hardware emulation of our SoCs, and the support we have received from Mentor, will play a major role in achieving these goals, and producing high-quality products for our customers.”
Veloce is the industry’s fastest dual-mode accelerator/emulator, providing MHz performance for both transaction-based verification and traditional in-circuit emulation (ICE). With an extensive portfolio of vertical market solutions, the Veloce product is the platform of choice for wireless, networking, multimedia, and embedded systems applications.
”We have worked closely with HiSilicon to provide the best possible emulation solution that meets HiSilicon’s needs and addresses the challenges they face in verifying their SoC designs,” stated Eric Selosse, Mentor Emulation Division (MED) vice president and general manager. “We are delighted that HiSilicon benefits from our latest generation hardware emulation solutions, and that they have adopted Veloce for the verification of their latest communications and digital media products.”
HiSilicon chose Veloce due to its superior debug capabilities, performance, accuracy, and extensive portfolio of iSolveTM vertical market in-circuit emulation (ICE) solutions, for the verification of wireless, networking, and multimedia designs.
“HiSilicon faces significant challenges in meeting time-to-market goals, performance requirements, and reducing the risks involved in the integration of our advanced SoC’s for communication networks and multimedia applications,” stated Teresa He, vice president semiconductor line, HiSilicon Technologies Co. Ltd. “The use of Veloce for the hardware emulation of our SoCs, and the support we have received from Mentor, will play a major role in achieving these goals, and producing high-quality products for our customers.”
Veloce is the industry’s fastest dual-mode accelerator/emulator, providing MHz performance for both transaction-based verification and traditional in-circuit emulation (ICE). With an extensive portfolio of vertical market solutions, the Veloce product is the platform of choice for wireless, networking, multimedia, and embedded systems applications.
”We have worked closely with HiSilicon to provide the best possible emulation solution that meets HiSilicon’s needs and addresses the challenges they face in verifying their SoC designs,” stated Eric Selosse, Mentor Emulation Division (MED) vice president and general manager. “We are delighted that HiSilicon benefits from our latest generation hardware emulation solutions, and that they have adopted Veloce for the verification of their latest communications and digital media products.”
Friday, July 31, 2009
Mentor unveils Android, Embedded Linux strategy by acquiring Embedded Alley
Design Automation Conference 2009, SAN FRANCISCO, USA: Mentor Graphics Corp.unveiled its Android and Linux strategy, including the acquisition of Embedded Alley Solutions Inc., an innovative leader in Android and Linux development systems.
By combining Embedded Alley’s Android and Linux products and services with the Mentor Graphics Nucleus real-time operating system (RTOS), tools and middleware, Mentor can now provide device manufacturers with all the software they need to build their products, and work closely with them throughout their product lifecycle to supply tools and services at every stage.
“Mentor’s strategy acknowledges two strong trends we see in embedded device development today,” stated Glenn Perry, Mentor Graphics Embedded Systems Division General Manager.
“One is a huge demand for Google’s Android platform in new, complex devices beyond the mobile phones for which Android was originally developed. The other is the growing use on multi-core processors of multiple operating systems, usually Linux and an RTOS like Nucleus. Our investment in Embedded Alley, and its products, open source expertise, and services, will allow our customers to innovate and build better products with power savings, performance optimization, and reduced system cost and risk.”
Mentor’s Android, Linux, and Nucleus products and services provide all the tools, runtime components and expertise required for customers to get to production with innovative products.
This ecosystem for Android- and Linux-based devices is supported by leading semiconductor partners, including ARM, Freescale, Marvell, MIPS, RMI, and Texas Instruments (TI). In separate announcements today, Mentor Graphics revealed support for the ARM Mali graphics processing unit family, Freescale Power Architecture processors and Marvell Sheeva MV78200 Dual-core Embedded Processors.
Embedded Alley was the first to market commercial Android tools and services in May 2009, for the RMI Au1250 SoC and the MIPS architecture.
“The Embedded Alley team is excited to bring our vast experience in open source development to Mentor Graphics,” said Pete Popov, CEO of Embedded Alley. “This is a huge win for our customers, who can now benefit from the combination of Embedded Alley's services and development systems with Mentor's products, services and outstanding support.”
“TI is pleased to learn that Mentor Graphics has acquired Embedded Alley, allowing Mentor to provide additional value to our customers developing with Android and/or Linux on our various TI solutions, including our OMAP35x platform,” said Gerard Andrews, OMAP35x product line manager, TI.
“With the combined expertise from Mentor Graphics and Embedded Alley, we’re confident that they will be able to deliver innovative and even stronger multi-OS/multi-core products that inspire new Linux- and Android-based designs. We’re excited and look forward to seeing the synergy between these two companies and their solutions that ultimately addresses our customers’ key careabouts on an open software platform, community participation and support.”
Perry continued: “As early developers in embedded Linux, Embedded Alley is well-known in the open source community, both as active participants in major projects such as OpenEmbedded, Advanced Linux Sound Architecture, and Linux kernel development, and as leaders in commercial development based on open source software. Their strong reputation follows them into the Android commercial tool market, now placing Mentor Graphics at the forefront of open source software in embedded devices.”
Embedded Alley gained a tremendous lead in Android solutions by investing early and building on their deep Linux/open source experience and technologies. As pioneers in the embedded Linux community, the Embedded Alley team has been instrumental in defining product offerings, shaping business models and building market strategies for embedded systems.
Its unique approach to commercial open source products avoided “boxed” Linux distributions, and gave developers more flexibility and immediate access to the latest open source innovations.
By combining Embedded Alley’s Android and Linux products and services with the Mentor Graphics Nucleus real-time operating system (RTOS), tools and middleware, Mentor can now provide device manufacturers with all the software they need to build their products, and work closely with them throughout their product lifecycle to supply tools and services at every stage.
“Mentor’s strategy acknowledges two strong trends we see in embedded device development today,” stated Glenn Perry, Mentor Graphics Embedded Systems Division General Manager.
“One is a huge demand for Google’s Android platform in new, complex devices beyond the mobile phones for which Android was originally developed. The other is the growing use on multi-core processors of multiple operating systems, usually Linux and an RTOS like Nucleus. Our investment in Embedded Alley, and its products, open source expertise, and services, will allow our customers to innovate and build better products with power savings, performance optimization, and reduced system cost and risk.”
Mentor’s Android, Linux, and Nucleus products and services provide all the tools, runtime components and expertise required for customers to get to production with innovative products.
This ecosystem for Android- and Linux-based devices is supported by leading semiconductor partners, including ARM, Freescale, Marvell, MIPS, RMI, and Texas Instruments (TI). In separate announcements today, Mentor Graphics revealed support for the ARM Mali graphics processing unit family, Freescale Power Architecture processors and Marvell Sheeva MV78200 Dual-core Embedded Processors.
Embedded Alley was the first to market commercial Android tools and services in May 2009, for the RMI Au1250 SoC and the MIPS architecture.
“The Embedded Alley team is excited to bring our vast experience in open source development to Mentor Graphics,” said Pete Popov, CEO of Embedded Alley. “This is a huge win for our customers, who can now benefit from the combination of Embedded Alley's services and development systems with Mentor's products, services and outstanding support.”
“TI is pleased to learn that Mentor Graphics has acquired Embedded Alley, allowing Mentor to provide additional value to our customers developing with Android and/or Linux on our various TI solutions, including our OMAP35x platform,” said Gerard Andrews, OMAP35x product line manager, TI.
“With the combined expertise from Mentor Graphics and Embedded Alley, we’re confident that they will be able to deliver innovative and even stronger multi-OS/multi-core products that inspire new Linux- and Android-based designs. We’re excited and look forward to seeing the synergy between these two companies and their solutions that ultimately addresses our customers’ key careabouts on an open software platform, community participation and support.”
Perry continued: “As early developers in embedded Linux, Embedded Alley is well-known in the open source community, both as active participants in major projects such as OpenEmbedded, Advanced Linux Sound Architecture, and Linux kernel development, and as leaders in commercial development based on open source software. Their strong reputation follows them into the Android commercial tool market, now placing Mentor Graphics at the forefront of open source software in embedded devices.”
Embedded Alley gained a tremendous lead in Android solutions by investing early and building on their deep Linux/open source experience and technologies. As pioneers in the embedded Linux community, the Embedded Alley team has been instrumental in defining product offerings, shaping business models and building market strategies for embedded systems.
Its unique approach to commercial open source products avoided “boxed” Linux distributions, and gave developers more flexibility and immediate access to the latest open source innovations.
Mentor enables Android on Freescale products
Design Automation Conference 2009, SAN FRANCISCO, USA: Mentor Graphics Corp., through its acquisition of Embedded Alley, a leading provider of embedded Linux and Android solutions, announced that the company is extending the popular Android mobile applications platform to support Freescale’s QorIQ and PowerQUICC III processors, which are built on Power Architecture technology.
Mentor now adds the Embedded Alley Development System to the ESD product offering, enabling device OEMs to deploy Android or Linux on devices built with these industry-leading Freescale products.
With this new release for the Embedded Alley Development System, the company broadens its support for Android and also continues to grow the application space for the Google/OHA software stack.
By supporting Android on QorIQ and PowerQUICC III processors, Mentor Graphics opens numerous industries and applications to Android deployment, including networking and network appliances, storage, printing and imaging, multimedia, and industrial control applications.
“Mentor Graphics’ experience and know-how with Power Architecture technology and in-depth knowledge of the Android platform positions us as a strong ecosystem partner to Freescale and an ideal supplier to OEMs,” said Glenn Perry, Mentor Graphics general manager for the Embedded Systems Division.
“Our support for Android on Freescale’s top Power Architecture processors brings a consumer-grade user interface and applications framework to new realms of intelligent devices and industrial equipment.”
“Enabling Android for QorIQ and PowerQUICC III processors offers Freescale’s customers additional choices and flexibility to help enable differentiated end-user experiences,” said Kamal Khouri, senior manager, Platform Product Management for Freescale’s Networking and Multimedia Group.
“Our collaboration with Mentor Graphics allows OEMs to build smart, feature-rich devices based on Freescale processors using either their own value-added applications or shrink-wrapped software from the Android Marketplace.”
Mentor Graphics’ engineering and productization efforts to enable Android for processors built on Power Architecture technology begins with the integration of Android-specific Linux kernel patches (for 2.6.28), and encompasses a range of other investments that include:
* Porting the Dalvik virtual machine underlying Android to Freescale’s PowerQUICC and QorIQ processors, including architecture and build support and comprehensive optimization for Dalvik acceleration.
* Extending Android bionic run-time library and linker support to accommodate Power Architecture technology.
* Utilizes SPE APU, and/or Power Architecture FPU performance enhancement across all software modules.
* Integrating and testing board support and industry-specific device drivers, CODECs and other middleware.
* Supporting Power Architecture technology in the Android Software Development Kit (SDK) and Android targets in the Mentor Graphics customizable Development System
Platform and integration testing of Android stack components and shrink-wrap Android applications.
The Embedded Alley Development System for Android-based devices from Mentor Graphics will be available starting in August 2009.
Based on the Open Handset Alliance “Cupcake” release of Android, the initial Mentor Graphics tool kit will include support for the Freescale MPC8536E development system, complemented by customer-tailored support from Mentor Graphics
Mentor now adds the Embedded Alley Development System to the ESD product offering, enabling device OEMs to deploy Android or Linux on devices built with these industry-leading Freescale products.
With this new release for the Embedded Alley Development System, the company broadens its support for Android and also continues to grow the application space for the Google/OHA software stack.
By supporting Android on QorIQ and PowerQUICC III processors, Mentor Graphics opens numerous industries and applications to Android deployment, including networking and network appliances, storage, printing and imaging, multimedia, and industrial control applications.
“Mentor Graphics’ experience and know-how with Power Architecture technology and in-depth knowledge of the Android platform positions us as a strong ecosystem partner to Freescale and an ideal supplier to OEMs,” said Glenn Perry, Mentor Graphics general manager for the Embedded Systems Division.
“Our support for Android on Freescale’s top Power Architecture processors brings a consumer-grade user interface and applications framework to new realms of intelligent devices and industrial equipment.”
“Enabling Android for QorIQ and PowerQUICC III processors offers Freescale’s customers additional choices and flexibility to help enable differentiated end-user experiences,” said Kamal Khouri, senior manager, Platform Product Management for Freescale’s Networking and Multimedia Group.
“Our collaboration with Mentor Graphics allows OEMs to build smart, feature-rich devices based on Freescale processors using either their own value-added applications or shrink-wrapped software from the Android Marketplace.”
Mentor Graphics’ engineering and productization efforts to enable Android for processors built on Power Architecture technology begins with the integration of Android-specific Linux kernel patches (for 2.6.28), and encompasses a range of other investments that include:
* Porting the Dalvik virtual machine underlying Android to Freescale’s PowerQUICC and QorIQ processors, including architecture and build support and comprehensive optimization for Dalvik acceleration.
* Extending Android bionic run-time library and linker support to accommodate Power Architecture technology.
* Utilizes SPE APU, and/or Power Architecture FPU performance enhancement across all software modules.
* Integrating and testing board support and industry-specific device drivers, CODECs and other middleware.
* Supporting Power Architecture technology in the Android Software Development Kit (SDK) and Android targets in the Mentor Graphics customizable Development System
Platform and integration testing of Android stack components and shrink-wrap Android applications.
The Embedded Alley Development System for Android-based devices from Mentor Graphics will be available starting in August 2009.
Based on the Open Handset Alliance “Cupcake” release of Android, the initial Mentor Graphics tool kit will include support for the Freescale MPC8536E development system, complemented by customer-tailored support from Mentor Graphics
Thursday, July 30, 2009
Mentor's Nucleus GUI and Linux platform for ARM Mali GPUs
DAC 2009, SAN FRANCISCO, USA: Mentor Graphics Corp. today announced the integration of its Nucleus graphics user interface (GUI) with the ARM Mali graphics processing unit (GPU) family of acceleration solutions.
The joint platform consists of Embedded Linux running on an ARM1176 processor with an integrated Mali-200 GPU. The tight integration of the Nucleus Graphics GUI solution with ARM’s optimized OpenGL ES device driver enables embedded designers to easily utilize the power of the GPU to deliver products with more compelling user interfaces.
By integrating the Nucleus Graphics GUI solution with the Mali-200 GPU, it is now possible for graphic artists and usability specialists to exploit the potential of this advanced 3D accelerator.
The Nucleus Graphics product abstracts the complexity of the OpenGL ES API to enable anyone to incorporate sophisticated 3D effects such as lighting, spinning, fading, twisting and zooming into their GUI designs without any programming knowledge.
“OpenGL ES is a powerful but complex API and few GUI technologies available today are designed from the outset to accommodate 3D effects and layouts. As a result, getting the best out of a 3D accelerator has generally required a lot of manual embedded programming,” said Ian Smythe, director of marketing, Media Processing Division, ARM.
“With this development, the Nucleus Graphics GUI solution enables anyone designing a GUI to make full use of Mali graphics acceleration capabilities.”
“The ARM Mali family of acceleration solutions is ideal for embedded systems and it is the perfect platform for Nucleus Graphics,” said Glenn Perry, Mentor Graphics Embedded Systems Division general manager.
“With our partnership with ARM, I expect to see a wide range of more dynamic and visually compelling products across the automotive, consumer, medical, and industrial markets over the next couple of years.”
The ARM Mali-200 3D GPU incorporates a fully programmable vertex and fragment shader architecture, making it ideally suited to a range of applications –- from advanced user interfaces and browsing experiences to console-quality gaming.
The joint platform consists of Embedded Linux running on an ARM1176 processor with an integrated Mali-200 GPU. The tight integration of the Nucleus Graphics GUI solution with ARM’s optimized OpenGL ES device driver enables embedded designers to easily utilize the power of the GPU to deliver products with more compelling user interfaces.
By integrating the Nucleus Graphics GUI solution with the Mali-200 GPU, it is now possible for graphic artists and usability specialists to exploit the potential of this advanced 3D accelerator.
The Nucleus Graphics product abstracts the complexity of the OpenGL ES API to enable anyone to incorporate sophisticated 3D effects such as lighting, spinning, fading, twisting and zooming into their GUI designs without any programming knowledge.
“OpenGL ES is a powerful but complex API and few GUI technologies available today are designed from the outset to accommodate 3D effects and layouts. As a result, getting the best out of a 3D accelerator has generally required a lot of manual embedded programming,” said Ian Smythe, director of marketing, Media Processing Division, ARM.
“With this development, the Nucleus Graphics GUI solution enables anyone designing a GUI to make full use of Mali graphics acceleration capabilities.”
“The ARM Mali family of acceleration solutions is ideal for embedded systems and it is the perfect platform for Nucleus Graphics,” said Glenn Perry, Mentor Graphics Embedded Systems Division general manager.
“With our partnership with ARM, I expect to see a wide range of more dynamic and visually compelling products across the automotive, consumer, medical, and industrial markets over the next couple of years.”
The ARM Mali-200 3D GPU incorporates a fully programmable vertex and fragment shader architecture, making it ideally suited to a range of applications –- from advanced user interfaces and browsing experiences to console-quality gaming.
Mentor announces Linux and Nucleus multi-OS support for Marvell Sheeva embedded processors
DAC 2009, SAN FRANCISCO, USA: Mentor Graphics Corp. today announced the availability of a combined open-source Linux and Nucleus operating system (OS) solution for the Marvell Sheeva MV78200 dual-core embedded processor.
“Our collaboration with Mentor Graphics’ embedded systems team has allowed Marvell to address the multi-OS needs of our customers using dual-core processors,” stated Dr. Simon Milner, vice president and general manager of the Enterprise Business Unit, Consumer and Communications Business Group at Marvell Semiconductor.
“The performance and real-time qualities of Mentor’s Nucleus OS complement the power and flexibility of Linux, while their tools and services give our mutual customers a boost in product development.”
This dual operating system support was co-developed by Mentor and Marvell, a leader in storage, communications, and consumer silicon solutions providing processors for devices that require enterprise-class performance with low-power consumption. Applications include network controllers, switches and routers, high-performance storage, enterprise printers, DVRs, NVRs and video surveillance, and high-volume SMB gateways.
“Our collaboration with Marvell delivers innovative system solutions that address the needs and requirements of our mutual customers today,” stated Glenn Perry, Mentor Graphics Embedded Systems Division general manager. “Multiple OSs on multicore SoCs, middleware, and services are critical for today’s low-power, high-performance devices, so we are excited about the breadth and depth of capabilities that can be realized with Marvell.”
The MV78200 is a dual-core, high-performance, low-power, highly integrated processor with the Marvell Sheeva CPU cores. Built on Marvell’s innovative Discovery system controller platform, the MV78200 is a complete SoC solution, optimized for low power operation and ideally suited to a wide range of applications ranging from sophisticated routers, switches and wireless base stations to high-volume laser printer applications.
Developers can use the dual OSs to manage separate functional requirements, yet allow them to easily and reliably communicate with each other. Mentor’s Nucleus OS is a fast, scalable and deterministic OS that can be used for operational tasks such as those required in printing drums and ink coverage for enterprise printers, whereas the Linux OS would be used for user interaction and communication.
“Our collaboration with Mentor Graphics’ embedded systems team has allowed Marvell to address the multi-OS needs of our customers using dual-core processors,” stated Dr. Simon Milner, vice president and general manager of the Enterprise Business Unit, Consumer and Communications Business Group at Marvell Semiconductor.
“The performance and real-time qualities of Mentor’s Nucleus OS complement the power and flexibility of Linux, while their tools and services give our mutual customers a boost in product development.”
This dual operating system support was co-developed by Mentor and Marvell, a leader in storage, communications, and consumer silicon solutions providing processors for devices that require enterprise-class performance with low-power consumption. Applications include network controllers, switches and routers, high-performance storage, enterprise printers, DVRs, NVRs and video surveillance, and high-volume SMB gateways.
“Our collaboration with Marvell delivers innovative system solutions that address the needs and requirements of our mutual customers today,” stated Glenn Perry, Mentor Graphics Embedded Systems Division general manager. “Multiple OSs on multicore SoCs, middleware, and services are critical for today’s low-power, high-performance devices, so we are excited about the breadth and depth of capabilities that can be realized with Marvell.”
The MV78200 is a dual-core, high-performance, low-power, highly integrated processor with the Marvell Sheeva CPU cores. Built on Marvell’s innovative Discovery system controller platform, the MV78200 is a complete SoC solution, optimized for low power operation and ideally suited to a wide range of applications ranging from sophisticated routers, switches and wireless base stations to high-volume laser printer applications.
Developers can use the dual OSs to manage separate functional requirements, yet allow them to easily and reliably communicate with each other. Mentor’s Nucleus OS is a fast, scalable and deterministic OS that can be used for operational tasks such as those required in printing drums and ink coverage for enterprise printers, whereas the Linux OS would be used for user interaction and communication.
Tuesday, July 28, 2009
Synopsys, Mentor, CoWare join ARM Fast Models Enablement Program
CAMBRIDGE, UK: ARM announced at DAC, San Francisco, that CoWare, Mentor Graphics and Synopsys Inc. have joined the ARM Fast Models Enablement Program.
Members of the Program are able to integrate fully validated Fast Models from ARM, for a range of ARM processors, into their virtual platform environments and deliver to their customers.
This ensures that mutual customers can create complete ARM Powered virtual platforms using the design flow of their choice. By using virtual platforms built around ARM processor Fast Models, engineers can develop software well in advance of final hardware implementation, with application and driver software running at near to real-time system performance.
The Fast Models product family from ARM includes programmer's view (PV) models for the ARM9, ARM11 and Cortex families of processors, including the Cortex-A9 MPCore multicore processor. The Fast Model products also include configuration tools that enable the export of ARM processor-based subsystems with OSCI SystemC and TLM-2.0 compliant interfaces.
"We are seeing a growing demand for high-performance models in the industry," said John Cornish, EVP and general manager, System Design Division, ARM. "The TLM-2.0 interface enables our customers to combine our processor Fast Models with models of their other IP to create complete virtual platforms in the design environment of their choice."
"CoWare has successfully delivered Electronic System Virtualization solutions for ARM processor-based designs for many years supporting architecture design, verification, software development, integration and test. With our further engagement in this broader program covering the ARM Cortex Fast Models, we continue to expand this position to serve the growing needs of our joint customers," said Marc Serughetti, vice president of Marketing and Business Development at CoWare Inc.
"This integration and partnership is already proven and in use at several customers resulting in significant time-to-market benefits for those customers."
"Mentor’s Vista technology offers a comprehensive architecture design and prototyping solution that relies on fast processor and peripheral models as an essential part of the solution. The integration of the architecturally accurate ARM Fast Models into our Vista Platform will deliver significant value to our mutual customers," said Simon Bloch, Mentor Graphics vice president and general manager, design and synthesis division.
"In addition, ARM’s Fast Models are compatible with Vista’s TLM scalable modeling methodology that provides the timing and power layers essential for optimizing performance and power at the transaction level of abstraction."
"As a leading IP provider, Synopsys already provides OSCI TLM-2.0 compliant transaction-level models for several processor families including ARM and Synopsys DesignWare Cores and components for SoC infrastructure, AMBA interconnect, CoreConnect and PrimeCell peripherals in the Synopsys DesignWare System-level Library," said Frank Schirrmeister, director product marketing for the Solutions Group at Synopsys.
"The ARM PV Enablement Program allows our users to draw from a larger number of models and enables Synopsys to validate interoperability of Synopsys’ Innovator development environment for virtual platforms with ARM processor-based subsystems using Fast Models from ARM."
Availability
Fast Models Version 5.0 including the SystemC/TLM-2.0 compatible export capability is available for immediate licensing from ARM. 45-day evaluations are available through the Program members in concert with their respective integrated solutions through the PV Enablement Program.
Members of the Program are able to integrate fully validated Fast Models from ARM, for a range of ARM processors, into their virtual platform environments and deliver to their customers.
This ensures that mutual customers can create complete ARM Powered virtual platforms using the design flow of their choice. By using virtual platforms built around ARM processor Fast Models, engineers can develop software well in advance of final hardware implementation, with application and driver software running at near to real-time system performance.
The Fast Models product family from ARM includes programmer's view (PV) models for the ARM9, ARM11 and Cortex families of processors, including the Cortex-A9 MPCore multicore processor. The Fast Model products also include configuration tools that enable the export of ARM processor-based subsystems with OSCI SystemC and TLM-2.0 compliant interfaces.
"We are seeing a growing demand for high-performance models in the industry," said John Cornish, EVP and general manager, System Design Division, ARM. "The TLM-2.0 interface enables our customers to combine our processor Fast Models with models of their other IP to create complete virtual platforms in the design environment of their choice."
"CoWare has successfully delivered Electronic System Virtualization solutions for ARM processor-based designs for many years supporting architecture design, verification, software development, integration and test. With our further engagement in this broader program covering the ARM Cortex Fast Models, we continue to expand this position to serve the growing needs of our joint customers," said Marc Serughetti, vice president of Marketing and Business Development at CoWare Inc.
"This integration and partnership is already proven and in use at several customers resulting in significant time-to-market benefits for those customers."
"Mentor’s Vista technology offers a comprehensive architecture design and prototyping solution that relies on fast processor and peripheral models as an essential part of the solution. The integration of the architecturally accurate ARM Fast Models into our Vista Platform will deliver significant value to our mutual customers," said Simon Bloch, Mentor Graphics vice president and general manager, design and synthesis division.
"In addition, ARM’s Fast Models are compatible with Vista’s TLM scalable modeling methodology that provides the timing and power layers essential for optimizing performance and power at the transaction level of abstraction."
"As a leading IP provider, Synopsys already provides OSCI TLM-2.0 compliant transaction-level models for several processor families including ARM and Synopsys DesignWare Cores and components for SoC infrastructure, AMBA interconnect, CoreConnect and PrimeCell peripherals in the Synopsys DesignWare System-level Library," said Frank Schirrmeister, director product marketing for the Solutions Group at Synopsys.
"The ARM PV Enablement Program allows our users to draw from a larger number of models and enables Synopsys to validate interoperability of Synopsys’ Innovator development environment for virtual platforms with ARM processor-based subsystems using Fast Models from ARM."
Availability
Fast Models Version 5.0 including the SystemC/TLM-2.0 compatible export capability is available for immediate licensing from ARM. 45-day evaluations are available through the Program members in concert with their respective integrated solutions through the PV Enablement Program.
Mentor underscores low-power strategy with Vista architecture-level power solution
SAN FRANCISCO, USA: Mentor Graphics Corp. emphasized its low-power strategy with the announcement of its fifth product platform this year with major new capabilities addressing low-power issues.
The Mentor Graphics Vista platform, for comprehensive architecture design and prototyping, now allows users to model, analyze and optimize power at the transaction level of abstraction.
The Vista product joins other Mentor products, including the Catapult C high-level synthesis tool, the Questa advanced functional verification platform, the Olympus-SoC place and route platform, and the HyperLynx PI power analysis tools, that together provide an end-to-end solution for low-power design, verification and implementation.
"Low power has become a main differentiator for the design of electronic systems," said Walden C. Rhines, chairman and CEO, Mentor Graphics. "Mentor’s low power strategy is to address power minimization on the total system at every stage of the design and verification flow, offering the most comprehensive suite of low power technologies so customers can implement precisely what they need."
Vista Platform
The Vista platform enables engineers to model power at the transaction architecture level using advanced power estimation policies long before an implementation becomes available, or annotate more accurate power behavior based on attributes of the technology process of the target implementation IP blocks.
"Because our storage solutions are complex by nature, it is critical we understand the system requirements and capabilities before we choose a system architecture," said Terry Doherty, engineer at Emulex.
"Using Mentor’s Vista platform, we are able to model the system architecture early in the design process, quantify the system performance and identify architectural limitations. This allows us to get to an optimal system architecture quickly while meeting solution requirements. Without this level of analysis we would not have been able to predict system performance until the system was fielded."
The Mentor Vista platform of low-power electronic system level (ESL) design tools provides a “layered” behavioral, timing and power modeling design methodology coupled with the SystemC Transaction-level Modeling Standard (TLM-2.0) supported by the Open SystemC Initiative (OSCI).
Vista offers an advanced design platform that allows chip designers and system architects to make viable decisions on hardware/software partitioning and architecture structures. With its advanced debug and analysis toolset, users can verify system-wide functionality, analyze and optimize systems under realistic traffic loads, and adjust system resources for optimal performance and power.
Users can also explore various voltage scaling and shutdown techniques and apply the most efficient power management strategies.
As a result, designers can ensure a cost-effective architecture with a suitable bandwidth that can carry the target application. Given the abstraction and fast simulation of the hardware representation, a model of the system can then be used as a virtual platform for early software development, analysis and validation, including the ability to profile power while executing application software.
"Power has become one of the most pressing constraints in current applications," said Guy Moshe, general manager and director of Mentor Graphics ESL/HDL design creation division. "We believe that managing power at the very early design stage, and way ahead of implementation, can offer high-value to our customers in their efforts to better differentiate their products while producing low-power devices."
The Mentor Graphics Vista platform, for comprehensive architecture design and prototyping, now allows users to model, analyze and optimize power at the transaction level of abstraction.
The Vista product joins other Mentor products, including the Catapult C high-level synthesis tool, the Questa advanced functional verification platform, the Olympus-SoC place and route platform, and the HyperLynx PI power analysis tools, that together provide an end-to-end solution for low-power design, verification and implementation.
"Low power has become a main differentiator for the design of electronic systems," said Walden C. Rhines, chairman and CEO, Mentor Graphics. "Mentor’s low power strategy is to address power minimization on the total system at every stage of the design and verification flow, offering the most comprehensive suite of low power technologies so customers can implement precisely what they need."
Vista Platform
The Vista platform enables engineers to model power at the transaction architecture level using advanced power estimation policies long before an implementation becomes available, or annotate more accurate power behavior based on attributes of the technology process of the target implementation IP blocks.
"Because our storage solutions are complex by nature, it is critical we understand the system requirements and capabilities before we choose a system architecture," said Terry Doherty, engineer at Emulex.
"Using Mentor’s Vista platform, we are able to model the system architecture early in the design process, quantify the system performance and identify architectural limitations. This allows us to get to an optimal system architecture quickly while meeting solution requirements. Without this level of analysis we would not have been able to predict system performance until the system was fielded."
The Mentor Vista platform of low-power electronic system level (ESL) design tools provides a “layered” behavioral, timing and power modeling design methodology coupled with the SystemC Transaction-level Modeling Standard (TLM-2.0) supported by the Open SystemC Initiative (OSCI).
Vista offers an advanced design platform that allows chip designers and system architects to make viable decisions on hardware/software partitioning and architecture structures. With its advanced debug and analysis toolset, users can verify system-wide functionality, analyze and optimize systems under realistic traffic loads, and adjust system resources for optimal performance and power.
Users can also explore various voltage scaling and shutdown techniques and apply the most efficient power management strategies.
As a result, designers can ensure a cost-effective architecture with a suitable bandwidth that can carry the target application. Given the abstraction and fast simulation of the hardware representation, a model of the system can then be used as a virtual platform for early software development, analysis and validation, including the ability to profile power while executing application software.
"Power has become one of the most pressing constraints in current applications," said Guy Moshe, general manager and director of Mentor Graphics ESL/HDL design creation division. "We believe that managing power at the very early design stage, and way ahead of implementation, can offer high-value to our customers in their efforts to better differentiate their products while producing low-power devices."
Monday, July 27, 2009
Mentor Graphics provides support for TSMC iPDKs
WILSONVILLE, USA: Mentor Graphics Corp. announced support for the TSMC interoperable process design kit (iPDK) in the Mentor Custom IC design flow products.
This support gives companies using TSMC process technology the freedom to choose best-in-class tools such as the IC Station tool without the encumbrance of proprietary PDK files, and results in shortened design cycle times and more effective design reuse.
“The TSMC unified iPDK is designed to eliminate the need for multiple proprietary PDKs, and opens the door to greater innovations in custom, analog, mixed-signal and RF design,” said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC. “Support from the EDA community has been outstanding, and we feel the collaborative nature of the work will pay huge dividends to our mutual customers.”
The TSMC iPDK is based on an Open Access database and data model, and features open standard languages for scripting and programming. It includes complete views of symbols, parameterized layout cells, callbacks and technology files. This approach ensures rapid availability of PDKs for advanced technology nodes, and allows TSMC customers more choices of design tools.
“The iPDK initiative is a great example of the industry working together in the best interest of its customers,” said Robert Hum, general manager of Mentor Graphics Deep Submicron Division. “Design kits written in proprietary languages that keep the customer captive to one vendor do not serve the industry well. Interoperability gives a customer the choice and flexibility to buy the EDA tools that best serve their business objectives.”
This support gives companies using TSMC process technology the freedom to choose best-in-class tools such as the IC Station tool without the encumbrance of proprietary PDK files, and results in shortened design cycle times and more effective design reuse.
“The TSMC unified iPDK is designed to eliminate the need for multiple proprietary PDKs, and opens the door to greater innovations in custom, analog, mixed-signal and RF design,” said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC. “Support from the EDA community has been outstanding, and we feel the collaborative nature of the work will pay huge dividends to our mutual customers.”
The TSMC iPDK is based on an Open Access database and data model, and features open standard languages for scripting and programming. It includes complete views of symbols, parameterized layout cells, callbacks and technology files. This approach ensures rapid availability of PDKs for advanced technology nodes, and allows TSMC customers more choices of design tools.
“The iPDK initiative is a great example of the industry working together in the best interest of its customers,” said Robert Hum, general manager of Mentor Graphics Deep Submicron Division. “Design kits written in proprietary languages that keep the customer captive to one vendor do not serve the industry well. Interoperability gives a customer the choice and flexibility to buy the EDA tools that best serve their business objectives.”
TSMC intros Mentor's new Calibre versions using interoperable iDRC and iLVS formats
WILSONVILLE, USA: Mentor Graphics Corp. announced that its Calibre nmDRC and nmLVS offerings now support the interoperable iDRC and iLVS formats introduced by TSMC.
TSMC and Mentor Graphics collaborated on these vendor-neutral formats for describing physical verification and layout vs. schematic (LVS) checks. The iDRC and iLVS syntaxes make it possible for TSMC and its customers to create verification decks that will work with Mentor’s Calibre nmDRC and nmLVS offerings or other verification products that support the specification. Mentor will optimize the underlying implementation of iDRC/iLVS to deliver optimum performance to end users.
The iDRC and iLVS specifications are based on the open source TCL language extended with specialized functions for verification. It has been validated on the Calibre platform for 40nm designs manufactured at TSMC, and will be rolled out as part of the TSMC reference flow for 28nm designs.
“The TSMC iDRC ands iLVS formats benefit both TSMC and its customers by making it possible to define and customize complex verification rules for each of our processes that can in turn drive verification tools from any supporting vendor,” said ST Juang, senior director of Design Infrastructure Marketing at TSMC.
“This enables us and our customers to easily adapt design rules to new requirements or special situations without worrying about tuning and testing for different tool flows. We’ve worked closely with Mentor on the architecture and syntax of iDRC and iLVS and have completed first validation on the Calibre tool suite as our lead physical verification platform.”
“Our collaboration with TSMC on the definition of iDRC and iLVS helps our mutual customers realize the best possible performance from Calibre products,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics.
“With this collaboration, TSMC ensures their design guidelines are delivered in a consistent manner to all qualified vendors, and Mentor can use its proprietary technology to continue delivering industry-leading verification platforms with the fastest and most efficient underlying code possible.”
The Calibre implementation of iDRC and iLVS converts iDRC decks into highly tuned native Calibre SVRF calls for optimum runtime performance. It also includes an interactive TCL debugger with breakpoints and variable monitors integrated with a layout debugger, which is part of the Calibre Results Viewing Environment (RVE), and a special in-line SVRF viewer.
The Calibre implementation of iDRC is currently being evaluated at selected TSMC and Mentor customer sites. General availability is expected at the end of 2009.
TSMC and Mentor Graphics collaborated on these vendor-neutral formats for describing physical verification and layout vs. schematic (LVS) checks. The iDRC and iLVS syntaxes make it possible for TSMC and its customers to create verification decks that will work with Mentor’s Calibre nmDRC and nmLVS offerings or other verification products that support the specification. Mentor will optimize the underlying implementation of iDRC/iLVS to deliver optimum performance to end users.
The iDRC and iLVS specifications are based on the open source TCL language extended with specialized functions for verification. It has been validated on the Calibre platform for 40nm designs manufactured at TSMC, and will be rolled out as part of the TSMC reference flow for 28nm designs.
“The TSMC iDRC ands iLVS formats benefit both TSMC and its customers by making it possible to define and customize complex verification rules for each of our processes that can in turn drive verification tools from any supporting vendor,” said ST Juang, senior director of Design Infrastructure Marketing at TSMC.
“This enables us and our customers to easily adapt design rules to new requirements or special situations without worrying about tuning and testing for different tool flows. We’ve worked closely with Mentor on the architecture and syntax of iDRC and iLVS and have completed first validation on the Calibre tool suite as our lead physical verification platform.”
“Our collaboration with TSMC on the definition of iDRC and iLVS helps our mutual customers realize the best possible performance from Calibre products,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics.
“With this collaboration, TSMC ensures their design guidelines are delivered in a consistent manner to all qualified vendors, and Mentor can use its proprietary technology to continue delivering industry-leading verification platforms with the fastest and most efficient underlying code possible.”
The Calibre implementation of iDRC and iLVS converts iDRC decks into highly tuned native Calibre SVRF calls for optimum runtime performance. It also includes an interactive TCL debugger with breakpoints and variable monitors integrated with a layout debugger, which is part of the Calibre Results Viewing Environment (RVE), and a special in-line SVRF viewer.
The Calibre implementation of iDRC is currently being evaluated at selected TSMC and Mentor customer sites. General availability is expected at the end of 2009.
Friday, July 17, 2009
Mentor Graphics signs Trident Techlabs as new India distributor
WILSONVILLE, USA: Mentor Graphics Corp. has signed Trident Techlabs Pvt. Ltd, previously a reseller of Altium’s products, as a distributor in India.
Trident will offer Mentor’s PCB and ASIC/FPGA products for systems design —Expedition Enterprise and PADS PCB design flows, the ModelSim product for ASIC and FPGA simulation, the Questa platform for advanced functional verification, and the HyperLynx family for high-speed PCB interconnect simulations.
This portfolio is tuned to the needs of Indian companies who are developing increasingly complex electronic systems.
“With the growing need for high-speed, advanced design technologies and globalization, companies in India’s electronics industry need to improve their design and analysis capabilities, upgrading from outdated design tools to solutions that meet scalable needs -– from the casual engineer to the most complex solutions,” stated Nilesh Paldhikar, executive director with Trident Techlabs.
“Our company is serving all markets, from casual designers through mission critical systems development as well as the entire academic market. We recognized Mentor Graphics as the only solution provider who can provide an affordable innovative technology to users of individual desktop tool solutions as well as to enterprises with more complex design processes and organizations.
"The PADS and Expedition Enterprise flows give our customers the scalability, power and ease-of-use they need. HyperLynx is the industry leading pre- and post-route signal and power integrity analysis product, combining intuitive ease-of-use with accuracy into the high gigabit segment. ModelSim and Questa for advanced ASIC and FPGA verification give engineers a full solution to complex systems design.”
“We are pleased to expand our reach in India with Trident Techlabs,” said Rick Bosshardt, vice president of Mentor’s Geography and Distribution Channel. “India is a very dynamic and fast-growing market place for electronics design. With Trident Techlabs, we will be able to expand and serve our customers better in five regions: Bangalore, Chennai, Delhi, Hyderabad and Pune.
"Trident has an excellent track record in the public, research and educational sector as well as within the electronics industry. In addition to their experience as a former Altium reseller, Trident will allow us to expand very quickly by offering the industry’s best design products to every electrical and PCB design engineer in India.”
Over the past year, Mentor Graphics has made significant enhancements and added industry-unique and innovative technologies to their PCB design flows:
* The PADS 9.0 release adds new levels of functionality, scalability and integration, enabling designers to leverage many of Mentor’s unique and innovative technologies for design, analysis and manufacturing preparation.
* The HyperLynx 8.0 release expands the industry-leading signal integrity solution with easy-to-use and accurate power integrity analysis as well as new functionality to analyze advanced interconnect methods like DDR2/3.
* To serve mid-sized to large companies, the Expedition Enterprise flow focuses on designer productivity, the use of advanced PCB fabrication and IC technologies, and multi-discipline collaboration of globally-dispersed design teams to improve the complete product development process.
For the functional verification of complex SoCs and ASICs, the Questa verification platform delivers the full value of advanced verification and debug technologies within a comprehensive verification solution based on a metrics-driven verification management system.
The Questa platform spans the levels of abstraction required for complex SoC and FPGA design and verification.
In addition, Mentor was the first to combine single kernel simulator technology with a unified debug environment for Verilog, VHDL, and SystemC.
The combination of industry-leading, native single kernel simulator performance with the best integrated debug and analysis environment makes ModelSim the simulator of choice for both ASIC and FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.
Trident will offer Mentor’s PCB and ASIC/FPGA products for systems design —Expedition Enterprise and PADS PCB design flows, the ModelSim product for ASIC and FPGA simulation, the Questa platform for advanced functional verification, and the HyperLynx family for high-speed PCB interconnect simulations.
This portfolio is tuned to the needs of Indian companies who are developing increasingly complex electronic systems.
“With the growing need for high-speed, advanced design technologies and globalization, companies in India’s electronics industry need to improve their design and analysis capabilities, upgrading from outdated design tools to solutions that meet scalable needs -– from the casual engineer to the most complex solutions,” stated Nilesh Paldhikar, executive director with Trident Techlabs.
“Our company is serving all markets, from casual designers through mission critical systems development as well as the entire academic market. We recognized Mentor Graphics as the only solution provider who can provide an affordable innovative technology to users of individual desktop tool solutions as well as to enterprises with more complex design processes and organizations.
"The PADS and Expedition Enterprise flows give our customers the scalability, power and ease-of-use they need. HyperLynx is the industry leading pre- and post-route signal and power integrity analysis product, combining intuitive ease-of-use with accuracy into the high gigabit segment. ModelSim and Questa for advanced ASIC and FPGA verification give engineers a full solution to complex systems design.”
“We are pleased to expand our reach in India with Trident Techlabs,” said Rick Bosshardt, vice president of Mentor’s Geography and Distribution Channel. “India is a very dynamic and fast-growing market place for electronics design. With Trident Techlabs, we will be able to expand and serve our customers better in five regions: Bangalore, Chennai, Delhi, Hyderabad and Pune.
"Trident has an excellent track record in the public, research and educational sector as well as within the electronics industry. In addition to their experience as a former Altium reseller, Trident will allow us to expand very quickly by offering the industry’s best design products to every electrical and PCB design engineer in India.”
Over the past year, Mentor Graphics has made significant enhancements and added industry-unique and innovative technologies to their PCB design flows:
* The PADS 9.0 release adds new levels of functionality, scalability and integration, enabling designers to leverage many of Mentor’s unique and innovative technologies for design, analysis and manufacturing preparation.
* The HyperLynx 8.0 release expands the industry-leading signal integrity solution with easy-to-use and accurate power integrity analysis as well as new functionality to analyze advanced interconnect methods like DDR2/3.
* To serve mid-sized to large companies, the Expedition Enterprise flow focuses on designer productivity, the use of advanced PCB fabrication and IC technologies, and multi-discipline collaboration of globally-dispersed design teams to improve the complete product development process.
For the functional verification of complex SoCs and ASICs, the Questa verification platform delivers the full value of advanced verification and debug technologies within a comprehensive verification solution based on a metrics-driven verification management system.
The Questa platform spans the levels of abstraction required for complex SoC and FPGA design and verification.
In addition, Mentor was the first to combine single kernel simulator technology with a unified debug environment for Verilog, VHDL, and SystemC.
The combination of industry-leading, native single kernel simulator performance with the best integrated debug and analysis environment makes ModelSim the simulator of choice for both ASIC and FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.
Wednesday, July 15, 2009
Atrenta, Mentor Graphics ally on power optimization for high-level synthesis
Design Automation Conference 2009, SAN JOSE, USA: Atrenta Inc. a leading provider of Early Design Closure solutions to radically improve design efficiency throughout the IC design flow, announced a collaboration with Mentor Graphics Corp. on an high-level synthesis power optimization flow.
The collaboration between the two companies has resulted in an interface between Mentor’s Catapult C Synthesis high-level synthesis tool and Atrenta’s SpyGlass-Power RTL power estimation and reduction tool to automate multi-level clock gating, an important technique used by designers in low-power designs.
According to Mentor Graphics, Catapult is the industry’s leading high-level synthesis tool and offers the fastest path to verified RTL from pure C++. With its new low-power optimizations, Catapult will thoroughly analyze the design to determine gateable clocks and build the appropriate logic -- an often error-prone and tedious task when done manually at the backend of the design flow. This new technology delivers near 100 percent perfect clock gating.
The resulting RTL output from Catapult is then seamlessly handed off to SpyGlass-Power, which examines every clock gating candidate identified by Catapult, measures the potential power savings, and determines which particular candidates should be included or excluded from the clock gating insertion process.
The static and dynamic power estimates from SpyGlass-Power are fed back into Catapult C for performance, area and power tradeoff analysis, and the resulting RTL netlist is then available to downstream RTL synthesis tools, resulting in a very efficient low-power design implementation.
According to Mentor Graphics, dynamic power savings for clock gating is design and test vector dependent, however measurements on more than 300 customer designs showed improvements ranging from 10 to 90 percent with an average improvement of 40 percent.
“By using a power-aware high-level synthesis flow starting from C++, designers have at their disposal a design methodology that makes power consumption a key design metric right at the start of the design process, where it can have the maximum impact,” said Shawn McCloud, product line director for High-Level Products at Mentor Graphics.
“The collaboration with Atrenta and their SpyGlass product significantly enhances the flow by quantifying power savings and ensuring that the generated RTL is power optimized.”
“The collaboration with Mentor and Catapult C provides users of high-level synthesis with the benefits of RTL analysis and optimization from our SpyGlass platform, especially for power estimation and reduction,” said Kiran Vittal, product marketing director of power and test products at Atrenta. “Power optimization is an important focus area for Atrenta. Several new capabilities to support better power optimization will be announced in the coming months.”
Atrenta and Mentor Graphics will showcase the results of this collaboration in a joint demonstration of an ESL-to-RTL power optimization flow in Atrenta’s booth at the 46th Design Automation Conference (DAC) in San Francisco.
The Catapult/SpyGlass flow is available now. The respective tools can be purchased from Mentor Graphics and Atrenta.
The collaboration between the two companies has resulted in an interface between Mentor’s Catapult C Synthesis high-level synthesis tool and Atrenta’s SpyGlass-Power RTL power estimation and reduction tool to automate multi-level clock gating, an important technique used by designers in low-power designs.
According to Mentor Graphics, Catapult is the industry’s leading high-level synthesis tool and offers the fastest path to verified RTL from pure C++. With its new low-power optimizations, Catapult will thoroughly analyze the design to determine gateable clocks and build the appropriate logic -- an often error-prone and tedious task when done manually at the backend of the design flow. This new technology delivers near 100 percent perfect clock gating.
The resulting RTL output from Catapult is then seamlessly handed off to SpyGlass-Power, which examines every clock gating candidate identified by Catapult, measures the potential power savings, and determines which particular candidates should be included or excluded from the clock gating insertion process.
The static and dynamic power estimates from SpyGlass-Power are fed back into Catapult C for performance, area and power tradeoff analysis, and the resulting RTL netlist is then available to downstream RTL synthesis tools, resulting in a very efficient low-power design implementation.
According to Mentor Graphics, dynamic power savings for clock gating is design and test vector dependent, however measurements on more than 300 customer designs showed improvements ranging from 10 to 90 percent with an average improvement of 40 percent.
“By using a power-aware high-level synthesis flow starting from C++, designers have at their disposal a design methodology that makes power consumption a key design metric right at the start of the design process, where it can have the maximum impact,” said Shawn McCloud, product line director for High-Level Products at Mentor Graphics.
“The collaboration with Atrenta and their SpyGlass product significantly enhances the flow by quantifying power savings and ensuring that the generated RTL is power optimized.”
“The collaboration with Mentor and Catapult C provides users of high-level synthesis with the benefits of RTL analysis and optimization from our SpyGlass platform, especially for power estimation and reduction,” said Kiran Vittal, product marketing director of power and test products at Atrenta. “Power optimization is an important focus area for Atrenta. Several new capabilities to support better power optimization will be announced in the coming months.”
Atrenta and Mentor Graphics will showcase the results of this collaboration in a joint demonstration of an ESL-to-RTL power optimization flow in Atrenta’s booth at the 46th Design Automation Conference (DAC) in San Francisco.
The Catapult/SpyGlass flow is available now. The respective tools can be purchased from Mentor Graphics and Atrenta.
Monday, July 13, 2009
Mentor's Walden Rhines keynoter at Semicon West
SEMICON West 2009, WILSONVILLE, USA: Mentor Graphics Corp. today announced that Dr. Walden C. Rhines, Chairman and CEO, will present the following keynote at Semicon West 2009 in San Francisco, CA.
Who: Dr. Walden C. Rhines, Chairman and CEO, Mentor Graphics
What: Presenting “World Semiconductor Dynamics: Myth vs. Reality”
When: Tuesday, July 14, 9:00 AM – 9:45 AM
Where: Novellus Theatre at the Yerba Buena Center for the Arts (across from Moscone Center)
In his keynote address, Dr. Rhines explores some of the issues confronting the EDA industry in today’s tough economic environment and presents historical data and trends of the semiconductor industry with conclusions that may surprise you.
Who: Dr. Walden C. Rhines, Chairman and CEO, Mentor Graphics
What: Presenting “World Semiconductor Dynamics: Myth vs. Reality”
When: Tuesday, July 14, 9:00 AM – 9:45 AM
Where: Novellus Theatre at the Yerba Buena Center for the Arts (across from Moscone Center)
In his keynote address, Dr. Rhines explores some of the issues confronting the EDA industry in today’s tough economic environment and presents historical data and trends of the semiconductor industry with conclusions that may surprise you.
Friday, July 10, 2009
Mentor Graphics signs Ruihesoft as new distributor in China
WILSONVILLE, USA: Mentor Graphics Corp. announced signing Beijing Ruihesoft Co., Ltd., previously a reseller of Altium’s products, as a distributor of Mentor’s Printed Circuit Board (PCB) systems design products in China.
The product portfolio will include the PADS PCB design flow as well as the HyperLynx® family for high-speed signal interconnect simulation. This portfolio is tuned to the predominant needs of China’s electronics companies, developing leading-edge systems with powerful desktop design solutions.
“Electronic systems and semiconductor components are getting more and more complex,” stated Feng Quanyu, general manager of Beijing Ruihesoft. “Mentor Graphics provides the industry’s best, affordable, innovative technology for users of individual desktop tool solutions as well as for enterprises with more complex design processes and organizations.
"Ruihesoft and Mentor Graphics will work together to provide total solutions and service for electronic system design companies in China. At a June 9th PCB seminar in Beijing held together with Mentor Graphics, hundreds of users highlighted the growing need for more powerful design and analysis solutions that deliver fast, accurate and repetitive results.”
“We are pleased to have Ruihesoft as our partner in China,” says Rick Bosshardt, vice president of Mentor’s Geography and Distribution Channel. “Ruihesoft is providing us with a broader coverage, adding five additional major cities in northern and eastern China.
"Their experience as a former Altium reseller, the excellent training facilities, and the reputation for their outstanding support and serving their customers’ needs will allow us to expand very quickly into new market segments by offering the best available products to every PCB design engineer in China.”
Over the past year, Mentor Graphics has made significant enhancements and added industry-unique and innovative technologies to its PCB design flows:
* The PADS 9.0 release adds new levels of functionality, scalability and integration, enabling designers to leverage many of Mentor’s unique and innovative technologies for design, analysis, manufacturing and multi-disciplined collaboration.
* The HyperLynx 8.0 product expands the industry-leading signal integrity solution with easy-to-use and accurate power integrity analysis, as well as new functionality to analyze advanced interconnect methods like DDR2/3.
The product portfolio will include the PADS PCB design flow as well as the HyperLynx® family for high-speed signal interconnect simulation. This portfolio is tuned to the predominant needs of China’s electronics companies, developing leading-edge systems with powerful desktop design solutions.
“Electronic systems and semiconductor components are getting more and more complex,” stated Feng Quanyu, general manager of Beijing Ruihesoft. “Mentor Graphics provides the industry’s best, affordable, innovative technology for users of individual desktop tool solutions as well as for enterprises with more complex design processes and organizations.
"Ruihesoft and Mentor Graphics will work together to provide total solutions and service for electronic system design companies in China. At a June 9th PCB seminar in Beijing held together with Mentor Graphics, hundreds of users highlighted the growing need for more powerful design and analysis solutions that deliver fast, accurate and repetitive results.”
“We are pleased to have Ruihesoft as our partner in China,” says Rick Bosshardt, vice president of Mentor’s Geography and Distribution Channel. “Ruihesoft is providing us with a broader coverage, adding five additional major cities in northern and eastern China.
"Their experience as a former Altium reseller, the excellent training facilities, and the reputation for their outstanding support and serving their customers’ needs will allow us to expand very quickly into new market segments by offering the best available products to every PCB design engineer in China.”
Over the past year, Mentor Graphics has made significant enhancements and added industry-unique and innovative technologies to its PCB design flows:
* The PADS 9.0 release adds new levels of functionality, scalability and integration, enabling designers to leverage many of Mentor’s unique and innovative technologies for design, analysis, manufacturing and multi-disciplined collaboration.
* The HyperLynx 8.0 product expands the industry-leading signal integrity solution with easy-to-use and accurate power integrity analysis, as well as new functionality to analyze advanced interconnect methods like DDR2/3.
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