Atrenta, Mentor Graphics ally on power optimization for high-level synthesis

Design Automation Conference 2009, SAN JOSE, USA: Atrenta Inc. a leading provider of Early Design Closure solutions to radically improve design efficiency throughout the IC design flow, announced a collaboration with Mentor Graphics Corp. on an high-level synthesis power optimization flow.

The collaboration between the two companies has resulted in an interface between Mentor’s Catapult C Synthesis high-level synthesis tool and Atrenta’s SpyGlass-Power RTL power estimation and reduction tool to automate multi-level clock gating, an important technique used by designers in low-power designs.

According to Mentor Graphics, Catapult is the industry’s leading high-level synthesis tool and offers the fastest path to verified RTL from pure C++. With its new low-power optimizations, Catapult will thoroughly analyze the design to determine gateable clocks and build the appropriate logic -- an often error-prone and tedious task when done manually at the backend of the design flow. This new technology delivers near 100 percent perfect clock gating.

The resulting RTL output from Catapult is then seamlessly handed off to SpyGlass-Power, which examines every clock gating candidate identified by Catapult, measures the potential power savings, and determines which particular candidates should be included or excluded from the clock gating insertion process.

The static and dynamic power estimates from SpyGlass-Power are fed back into Catapult C for performance, area and power tradeoff analysis, and the resulting RTL netlist is then available to downstream RTL synthesis tools, resulting in a very efficient low-power design implementation.

According to Mentor Graphics, dynamic power savings for clock gating is design and test vector dependent, however measurements on more than 300 customer designs showed improvements ranging from 10 to 90 percent with an average improvement of 40 percent.

“By using a power-aware high-level synthesis flow starting from C++, designers have at their disposal a design methodology that makes power consumption a key design metric right at the start of the design process, where it can have the maximum impact,” said Shawn McCloud, product line director for High-Level Products at Mentor Graphics.

“The collaboration with Atrenta and their SpyGlass product significantly enhances the flow by quantifying power savings and ensuring that the generated RTL is power optimized.”

“The collaboration with Mentor and Catapult C provides users of high-level synthesis with the benefits of RTL analysis and optimization from our SpyGlass platform, especially for power estimation and reduction,” said Kiran Vittal, product marketing director of power and test products at Atrenta. “Power optimization is an important focus area for Atrenta. Several new capabilities to support better power optimization will be announced in the coming months.”

Atrenta and Mentor Graphics will showcase the results of this collaboration in a joint demonstration of an ESL-to-RTL power optimization flow in Atrenta’s booth at the 46th Design Automation Conference (DAC) in San Francisco.

The Catapult/SpyGlass flow is available now. The respective tools can be purchased from Mentor Graphics and Atrenta.

Mentor extends Catapult C with support for control logic

WILSONVILLE, USA: Mentor Graphics Corp. announced that the Catapult C Synthesis tool has been extended to support control logic and manage low power design requirements, thus enabling full-chip high-level synthesis (HLS).

This breakthrough technology allows designers to use pure ANSI C++ for both algorithmic blocks and control logic blocks. Extending the Catapult C tool’s capabilities to full-chip high-level synthesis is critical due to the rapid growth in design size and complexity, which requires engineers to design hardware functionality at higher levels of abstraction.

Control logic synthesis and algorithmic synthesis have traditionally been addressed using different languages, formalisms and abstractions. The latest advances in the Catapult C Synthesis tool unifies these two domains, allowing users to describe control logic along with algorithmic behavior in a single and coherent model leveraging standard ANSI C++.

At the heart of this innovation is a new synthesizable C++ construct, which allows designers to easily specify asynchronous data communication, allowing full control over concurrent hardware creation. This pivotal mechanism allows interfacing algorithmic representations driven by the dataflow with control-dominated blocks synchronized by clocks.

The result is a coding style familiar to hardware designers, letting users easily express communication, priority and task coordination within an abstract representation of concurrency. The new approach formalizes a modeling style, which provides the necessary accuracy for control oriented tasks, while preserving the abstraction beneficial for algorithmic subsystems.

The synthesis process is complemented by a patent-pending and fully automated verification flow which for the first time lets users validate the detailed RTL-level block interactions at the C level.

Tight integration between verification and synthesis has proved a necessity to realizing the full potential of HLS. A common pitfall found with other HLS tools is developing high-level synthesis in isolation, which results in overly complex verification of the RTL output.

"Our digital broadcasting ICs typically consist of a complex mix of compute intensive algorithmic units and control dominated blocks," said Professor Schlicht, Head of Department, Fraunhofer Institute for Integrated Circuits.

"The new Catapult extensions for control-logic synthesis provide us with the capability to develop an increasing portion of the overall system using high-level synthesis from C++. This allows us to extend our C++ based implementation flow beyond the pure signal processing blocks."

In addition to support for control logic, the Catapult C Synthesis tool has added innovative technology for low power design by automating two prevailing design techniques: multi-level clock gating and interfacing to dynamic power and clock management units.

The Catapult C tool will analyze deep cones of logic to find gateable clocks, an otherwise error-prone and manual task typically done by backend low power experts.
This new and unique optimization delivers near 100% perfect clock gating by operating at the flop level, maximizing power savings by locally inferring the gating logic surrounding the targeted registers.

To help further reduce power, the Catapult C Synthesis tool also exports real-time information on the state of all system blocks. This information is relayed to power management units leveraging dynamic frequency and voltage scaling heuristics to achieve system-wide power savings.

As expected, dynamic power savings is design and test vector dependent; measurements on more than 300 customer designs showed improvements ranging from 10 percent to 90 percent, with an average improvement of 40 percent.

"The control logic extensions of Catapult C now let us develop a larger part of our systems with HLS," said Emmanuel Liegeon, Deputy Manager of Digital ASIC & FPGA Design Group, Thales Alenia Space. "As we develop more and more of the system in HLS, it becomes paramount to get power right. The latest enhancements in Catapult C for low power are delivering the optimizations we need."

Catapult C
The Catapult C Synthesis tool is the first product to automatically generate control and algorithmic RTL multi-block designs from a pure ANSI C++ source where both the core algorithm and interface are untimed.

This productivity improvement gives designers time and freedom to automatically perform detailed design exploration of different micro-architectural options and interface scenarios to quickly achieve fully optimized hardware designs.

The Catapult C Synthesis 2009a release is available to customers in July. The Catapult C product family ranges from $140,000 to $390,000.

Cadence C-to-Silicon Compiler eliminates barriers to HLS adoption

Cadence Design Systems Inc. recently announced its C-to-Silicon Compiler, said to be the next-generation of HLS (high-level synthesis) technology.

The C-to-Silicon Compiler is said to eliminate historical barriers to HLS adoption to deliver the quality of results and net productivity gains engineers need. It also produces RTL (register transfer level) with quality at or above the 90th percentile of manual RTL design, while increasing the engineering productivity up to 10X. HLS incidentally, reduces the manual effort required to produce RTL, thereby enabling designers to avoid syntax errors common in traditional methodologies.

I was very fortunate enough to be able to speak directly with Steve Svoboda, marketing director for system level design products, Cadence, in the US, last evening, on the C-to-Silicon Compiler.

According to Svoboda, this tool can accurately predict timing estimates. Logic synthesis ability is embedded into the tool. Cadence logic sysnthesis has been embedded inside HLS. HLS transforms C and C++ into RTL.

What can this product actually do for the EDA industry? He says it can actually take EDA up to a new level in terms of delivering additional productivity to designers.

"When design compiler and logic synthesis came, it was during the golden era of the semiconductor industry. Productivity was increasing rapidly. But the problem is, since the early 1990s, there has been no real change in the RTL design methodology. The only productivity increase has come out in form of design re-use," he says.

"This (C-to-Silicon Compiler) could re-energize semiconductor and EDA industries by at least 10X times. About 20 years ago, there was 10X productivity increase. By having HLS, we can now close the gap and tackle the chips more effectively now."

So, first up, will C-to-Silicon Compiler compete with custom design projects? Svoboda it won't! Custom design projects typically utilize transistor-level design. C-to-Silicon is made to work within a standard ASIC design-flow.

Accelerate and improve verification
The C-to-Silicon Compiler will both accelerate and improve verification as well. The timing-approximate fast hardware models (FHMs) run 80-90 percent the speed of untimed C-models (or two-three orders of magnitude faster than RTL). This enables the hardware-software co-verification with greater timing accuracy.

The next question is: can people use third-party synthesis tools, along with the proprietary Cadence systhesis tool? Svoboda says that the C-to-Silicon Compiler outputs IEEE-standard Verilog RTL. Therefore, the output can go to any third-party synthesis tool. However, as the RTL output is generated using timing estimates from Cadence RTL Compiler, designers will get the best quality of results when using RTL Compiler for logic synthesis.

Will C-to-Silicon Compiler better predict performance and power? And if yes, has this cracked the low-power design issue? Svoboda adds that because of embedded logic synthesis, the C-to-Silicon Compiler can predict performance and (in principle) power better than other high-level synthesis tools.

He says: "Power estimation/optimization are key feature sets planned for upcoming releases of C-to-Silicon Compiler. We believe that those capabilities will enable the designers to create designs that are much better optimized for power, since design decisions with greatest power impact are made at the system-level."

Finally, how does C-to-Silicon compiler handle hardware allocation and scheduling operations? The answer is, C-to-Silicon Compiler handles hardware allocation and scheduling using various proprietary algorithms and heuristics. Many of these are based on previous research at Cadence Berkeley Labs.

Svoboda notes: "One should note that the better quality of results/performance of C-to-Silicon is due primarily to its inherent ability to generate more accurate timing-estimates than other HLS tools. The higher accuracy timing estimates result from the embedding of logic synthesis within the HLS tool/process, which enables gathering of full-context gate-level information to derive the timing estimates.

"Other HLS approaches rely on pre-characterization of technology libraries, which is not accurate enough, because those gate level estimates are only nominal values, and do not take into account the full-context of the design (fan-in, fan-out, buffers, etc.)"

Lastly, what happens to ESL (electronic system-level) tools? He believes that this tool will help the ESL market.

Svoboda says: "We now have a methodology to do design creation in C++ and SystemC. For example, they do virtual prototyping, hardware-software co-design, etc. In the past, when engineers created designs, they had to re-design in C++, etc. Our tool creates the RTL automatically for them. So, this could re-energize the ESL market very well."

It will be interesting to see what the other EDA firms such as Synopsys and Magma have in store!