Design Automation Conference 2009, SAN FRANCISCO, USA: Mentor Graphics Corp.unveiled its Android and Linux strategy, including the acquisition of Embedded Alley Solutions Inc., an innovative leader in Android and Linux development systems.
By combining Embedded Alley’s Android and Linux products and services with the Mentor Graphics Nucleus real-time operating system (RTOS), tools and middleware, Mentor can now provide device manufacturers with all the software they need to build their products, and work closely with them throughout their product lifecycle to supply tools and services at every stage.
“Mentor’s strategy acknowledges two strong trends we see in embedded device development today,” stated Glenn Perry, Mentor Graphics Embedded Systems Division General Manager.
“One is a huge demand for Google’s Android platform in new, complex devices beyond the mobile phones for which Android was originally developed. The other is the growing use on multi-core processors of multiple operating systems, usually Linux and an RTOS like Nucleus. Our investment in Embedded Alley, and its products, open source expertise, and services, will allow our customers to innovate and build better products with power savings, performance optimization, and reduced system cost and risk.”
Mentor’s Android, Linux, and Nucleus products and services provide all the tools, runtime components and expertise required for customers to get to production with innovative products.
This ecosystem for Android- and Linux-based devices is supported by leading semiconductor partners, including ARM, Freescale, Marvell, MIPS, RMI, and Texas Instruments (TI). In separate announcements today, Mentor Graphics revealed support for the ARM Mali graphics processing unit family, Freescale Power Architecture processors and Marvell Sheeva MV78200 Dual-core Embedded Processors.
Embedded Alley was the first to market commercial Android tools and services in May 2009, for the RMI Au1250 SoC and the MIPS architecture.
“The Embedded Alley team is excited to bring our vast experience in open source development to Mentor Graphics,” said Pete Popov, CEO of Embedded Alley. “This is a huge win for our customers, who can now benefit from the combination of Embedded Alley's services and development systems with Mentor's products, services and outstanding support.”
“TI is pleased to learn that Mentor Graphics has acquired Embedded Alley, allowing Mentor to provide additional value to our customers developing with Android and/or Linux on our various TI solutions, including our OMAP35x platform,” said Gerard Andrews, OMAP35x product line manager, TI.
“With the combined expertise from Mentor Graphics and Embedded Alley, we’re confident that they will be able to deliver innovative and even stronger multi-OS/multi-core products that inspire new Linux- and Android-based designs. We’re excited and look forward to seeing the synergy between these two companies and their solutions that ultimately addresses our customers’ key careabouts on an open software platform, community participation and support.”
Perry continued: “As early developers in embedded Linux, Embedded Alley is well-known in the open source community, both as active participants in major projects such as OpenEmbedded, Advanced Linux Sound Architecture, and Linux kernel development, and as leaders in commercial development based on open source software. Their strong reputation follows them into the Android commercial tool market, now placing Mentor Graphics at the forefront of open source software in embedded devices.”
Embedded Alley gained a tremendous lead in Android solutions by investing early and building on their deep Linux/open source experience and technologies. As pioneers in the embedded Linux community, the Embedded Alley team has been instrumental in defining product offerings, shaping business models and building market strategies for embedded systems.
Its unique approach to commercial open source products avoided “boxed” Linux distributions, and gave developers more flexibility and immediate access to the latest open source innovations.
Showing posts with label DAC 2009. Show all posts
Showing posts with label DAC 2009. Show all posts
Friday, July 31, 2009
Mentor enables Android on Freescale products
Design Automation Conference 2009, SAN FRANCISCO, USA: Mentor Graphics Corp., through its acquisition of Embedded Alley, a leading provider of embedded Linux and Android solutions, announced that the company is extending the popular Android mobile applications platform to support Freescale’s QorIQ and PowerQUICC III processors, which are built on Power Architecture technology.
Mentor now adds the Embedded Alley Development System to the ESD product offering, enabling device OEMs to deploy Android or Linux on devices built with these industry-leading Freescale products.
With this new release for the Embedded Alley Development System, the company broadens its support for Android and also continues to grow the application space for the Google/OHA software stack.
By supporting Android on QorIQ and PowerQUICC III processors, Mentor Graphics opens numerous industries and applications to Android deployment, including networking and network appliances, storage, printing and imaging, multimedia, and industrial control applications.
“Mentor Graphics’ experience and know-how with Power Architecture technology and in-depth knowledge of the Android platform positions us as a strong ecosystem partner to Freescale and an ideal supplier to OEMs,” said Glenn Perry, Mentor Graphics general manager for the Embedded Systems Division.
“Our support for Android on Freescale’s top Power Architecture processors brings a consumer-grade user interface and applications framework to new realms of intelligent devices and industrial equipment.”
“Enabling Android for QorIQ and PowerQUICC III processors offers Freescale’s customers additional choices and flexibility to help enable differentiated end-user experiences,” said Kamal Khouri, senior manager, Platform Product Management for Freescale’s Networking and Multimedia Group.
“Our collaboration with Mentor Graphics allows OEMs to build smart, feature-rich devices based on Freescale processors using either their own value-added applications or shrink-wrapped software from the Android Marketplace.”
Mentor Graphics’ engineering and productization efforts to enable Android for processors built on Power Architecture technology begins with the integration of Android-specific Linux kernel patches (for 2.6.28), and encompasses a range of other investments that include:
* Porting the Dalvik virtual machine underlying Android to Freescale’s PowerQUICC and QorIQ processors, including architecture and build support and comprehensive optimization for Dalvik acceleration.
* Extending Android bionic run-time library and linker support to accommodate Power Architecture technology.
* Utilizes SPE APU, and/or Power Architecture FPU performance enhancement across all software modules.
* Integrating and testing board support and industry-specific device drivers, CODECs and other middleware.
* Supporting Power Architecture technology in the Android Software Development Kit (SDK) and Android targets in the Mentor Graphics customizable Development System
Platform and integration testing of Android stack components and shrink-wrap Android applications.
The Embedded Alley Development System for Android-based devices from Mentor Graphics will be available starting in August 2009.
Based on the Open Handset Alliance “Cupcake” release of Android, the initial Mentor Graphics tool kit will include support for the Freescale MPC8536E development system, complemented by customer-tailored support from Mentor Graphics
Mentor now adds the Embedded Alley Development System to the ESD product offering, enabling device OEMs to deploy Android or Linux on devices built with these industry-leading Freescale products.
With this new release for the Embedded Alley Development System, the company broadens its support for Android and also continues to grow the application space for the Google/OHA software stack.
By supporting Android on QorIQ and PowerQUICC III processors, Mentor Graphics opens numerous industries and applications to Android deployment, including networking and network appliances, storage, printing and imaging, multimedia, and industrial control applications.
“Mentor Graphics’ experience and know-how with Power Architecture technology and in-depth knowledge of the Android platform positions us as a strong ecosystem partner to Freescale and an ideal supplier to OEMs,” said Glenn Perry, Mentor Graphics general manager for the Embedded Systems Division.
“Our support for Android on Freescale’s top Power Architecture processors brings a consumer-grade user interface and applications framework to new realms of intelligent devices and industrial equipment.”
“Enabling Android for QorIQ and PowerQUICC III processors offers Freescale’s customers additional choices and flexibility to help enable differentiated end-user experiences,” said Kamal Khouri, senior manager, Platform Product Management for Freescale’s Networking and Multimedia Group.
“Our collaboration with Mentor Graphics allows OEMs to build smart, feature-rich devices based on Freescale processors using either their own value-added applications or shrink-wrapped software from the Android Marketplace.”
Mentor Graphics’ engineering and productization efforts to enable Android for processors built on Power Architecture technology begins with the integration of Android-specific Linux kernel patches (for 2.6.28), and encompasses a range of other investments that include:
* Porting the Dalvik virtual machine underlying Android to Freescale’s PowerQUICC and QorIQ processors, including architecture and build support and comprehensive optimization for Dalvik acceleration.
* Extending Android bionic run-time library and linker support to accommodate Power Architecture technology.
* Utilizes SPE APU, and/or Power Architecture FPU performance enhancement across all software modules.
* Integrating and testing board support and industry-specific device drivers, CODECs and other middleware.
* Supporting Power Architecture technology in the Android Software Development Kit (SDK) and Android targets in the Mentor Graphics customizable Development System
Platform and integration testing of Android stack components and shrink-wrap Android applications.
The Embedded Alley Development System for Android-based devices from Mentor Graphics will be available starting in August 2009.
Based on the Open Handset Alliance “Cupcake” release of Android, the initial Mentor Graphics tool kit will include support for the Freescale MPC8536E development system, complemented by customer-tailored support from Mentor Graphics
Thursday, July 30, 2009
Mentor's Nucleus GUI and Linux platform for ARM Mali GPUs
DAC 2009, SAN FRANCISCO, USA: Mentor Graphics Corp. today announced the integration of its Nucleus graphics user interface (GUI) with the ARM Mali graphics processing unit (GPU) family of acceleration solutions.
The joint platform consists of Embedded Linux running on an ARM1176 processor with an integrated Mali-200 GPU. The tight integration of the Nucleus Graphics GUI solution with ARM’s optimized OpenGL ES device driver enables embedded designers to easily utilize the power of the GPU to deliver products with more compelling user interfaces.
By integrating the Nucleus Graphics GUI solution with the Mali-200 GPU, it is now possible for graphic artists and usability specialists to exploit the potential of this advanced 3D accelerator.
The Nucleus Graphics product abstracts the complexity of the OpenGL ES API to enable anyone to incorporate sophisticated 3D effects such as lighting, spinning, fading, twisting and zooming into their GUI designs without any programming knowledge.
“OpenGL ES is a powerful but complex API and few GUI technologies available today are designed from the outset to accommodate 3D effects and layouts. As a result, getting the best out of a 3D accelerator has generally required a lot of manual embedded programming,” said Ian Smythe, director of marketing, Media Processing Division, ARM.
“With this development, the Nucleus Graphics GUI solution enables anyone designing a GUI to make full use of Mali graphics acceleration capabilities.”
“The ARM Mali family of acceleration solutions is ideal for embedded systems and it is the perfect platform for Nucleus Graphics,” said Glenn Perry, Mentor Graphics Embedded Systems Division general manager.
“With our partnership with ARM, I expect to see a wide range of more dynamic and visually compelling products across the automotive, consumer, medical, and industrial markets over the next couple of years.”
The ARM Mali-200 3D GPU incorporates a fully programmable vertex and fragment shader architecture, making it ideally suited to a range of applications –- from advanced user interfaces and browsing experiences to console-quality gaming.
The joint platform consists of Embedded Linux running on an ARM1176 processor with an integrated Mali-200 GPU. The tight integration of the Nucleus Graphics GUI solution with ARM’s optimized OpenGL ES device driver enables embedded designers to easily utilize the power of the GPU to deliver products with more compelling user interfaces.
By integrating the Nucleus Graphics GUI solution with the Mali-200 GPU, it is now possible for graphic artists and usability specialists to exploit the potential of this advanced 3D accelerator.
The Nucleus Graphics product abstracts the complexity of the OpenGL ES API to enable anyone to incorporate sophisticated 3D effects such as lighting, spinning, fading, twisting and zooming into their GUI designs without any programming knowledge.
“OpenGL ES is a powerful but complex API and few GUI technologies available today are designed from the outset to accommodate 3D effects and layouts. As a result, getting the best out of a 3D accelerator has generally required a lot of manual embedded programming,” said Ian Smythe, director of marketing, Media Processing Division, ARM.
“With this development, the Nucleus Graphics GUI solution enables anyone designing a GUI to make full use of Mali graphics acceleration capabilities.”
“The ARM Mali family of acceleration solutions is ideal for embedded systems and it is the perfect platform for Nucleus Graphics,” said Glenn Perry, Mentor Graphics Embedded Systems Division general manager.
“With our partnership with ARM, I expect to see a wide range of more dynamic and visually compelling products across the automotive, consumer, medical, and industrial markets over the next couple of years.”
The ARM Mali-200 3D GPU incorporates a fully programmable vertex and fragment shader architecture, making it ideally suited to a range of applications –- from advanced user interfaces and browsing experiences to console-quality gaming.
Wednesday, July 29, 2009
Azuro's low-power CTS for complex SoC designs
Design Automation Conference 2009, SANTA CLARA, USA: Azuro Inc., a provider of advanced implementation tools for nanometer chip design, has announced version 5 of its PowerCentric low-power clock tree synthesis (CTS) solution with extended support for complex system-on-chip (SoC) designs.
“Azuro’s proprietary global approaches to clock tree balancing and patented clock gate optimization algorithms are ideally suited to complex SoC designs,” said Paul Cunningham, CEO and co-founder of Azuro.
“PowerCentric is being actively used to tape out many of the world’s most complex chips with hundreds of intertwined clocks and dozens of voltage islands. This latest software release strengthens our proven leadership position in CTS and reinforces Azuro’s continued commitment to deliver lowest clock power, best clock gate timing, and fastest CTS turnaround time.”
Key features in PowerCentric version 5 include:
* 30 percent reduction in CTS runtimes on designs with multiple modes and corners.
* Enhanced clock gate optimization and clock tree buffering algorithms delivering up to 10 percent additional clock power savings.
* Comprehensive support for UPF 2.0 (IEEE 1801) power domain configuration format.
* Ground breaking new “Trial CTS” capability delivering accurate post-CTS design timing with runtimes of less than one hour per one million placeable instances.
* Top level clock balancing through hardened sub-chips with back-annotated parasitics.
* Full database save with rapid restore.
PowerCentric version 5 is available now with UPF 2.0 support in limited availability.
“Azuro’s proprietary global approaches to clock tree balancing and patented clock gate optimization algorithms are ideally suited to complex SoC designs,” said Paul Cunningham, CEO and co-founder of Azuro.
“PowerCentric is being actively used to tape out many of the world’s most complex chips with hundreds of intertwined clocks and dozens of voltage islands. This latest software release strengthens our proven leadership position in CTS and reinforces Azuro’s continued commitment to deliver lowest clock power, best clock gate timing, and fastest CTS turnaround time.”
Key features in PowerCentric version 5 include:
* 30 percent reduction in CTS runtimes on designs with multiple modes and corners.
* Enhanced clock gate optimization and clock tree buffering algorithms delivering up to 10 percent additional clock power savings.
* Comprehensive support for UPF 2.0 (IEEE 1801) power domain configuration format.
* Ground breaking new “Trial CTS” capability delivering accurate post-CTS design timing with runtimes of less than one hour per one million placeable instances.
* Top level clock balancing through hardened sub-chips with back-annotated parasitics.
* Full database save with rapid restore.
PowerCentric version 5 is available now with UPF 2.0 support in limited availability.
austriamicrosystems to produce Triad's via-configurable SoC solution
Design Automation Conference 2009, UNTERPREMSTAETTEN, AUSTRIA & WINSTON SALEM, USA: austriamicrosystems business unit Full Service Foundry announced that Triad Semiconductor has selected austriamicrosystems for the production of its Via-Configurable Array (VCA) technology.
The VCA technology has been developed using austriamicrosystems advanced analog specialty 0.35um CMOS embedded EEPROM process technology and is manufactured in austriamicrosystems state-of-the-art 8-inch SMIF fab. Triad is extending its already successful line of VCAs fabricated at austriamicrosystems with the introduction of the Mocha product line.
Mocha is a complete system-on-chip (SoC) solution combining a high performance, low power 32-bit processor with Triad’s via configurable analog, digital, and memory resources. Unique to Triad’s patented VCA approach is the ability to configure and interconnect this rich set of resources using only a single via mask layer.
This approach enables the re-use of silicon-proven IP, reduces engineering and tooling costs, and improves development time.
“The austriamicrosystems C35 specialty process contains the superior analog/mixed-signal features that our applications demand” states James Kemerling, CTO and Co-Founder of Triad Semiconductor. “Highest manufacturing quality standards and the C35 process’ mixed signal capabilities combined with the ability to embed EEPROM and high voltage options makes this an ideal process to support our new Mocha-family of configurable SoCs.”
“Triad’s via-configurable array technology enables ASIC customers to rapidly develop prototypes of their products.” states Thomas Riener, General Manager Full Service Foundry at austriamicrosystems. “It helps shorten the development phase and supports fast product ramp-ups which ultimately results in a reduced time-to-profits. Once requiring high volume production, customers can either further optimize the VCA or easily change to pure ASIC manufacturing.”
The VCA technology has been developed using austriamicrosystems advanced analog specialty 0.35um CMOS embedded EEPROM process technology and is manufactured in austriamicrosystems state-of-the-art 8-inch SMIF fab. Triad is extending its already successful line of VCAs fabricated at austriamicrosystems with the introduction of the Mocha product line.
Mocha is a complete system-on-chip (SoC) solution combining a high performance, low power 32-bit processor with Triad’s via configurable analog, digital, and memory resources. Unique to Triad’s patented VCA approach is the ability to configure and interconnect this rich set of resources using only a single via mask layer.
This approach enables the re-use of silicon-proven IP, reduces engineering and tooling costs, and improves development time.
“The austriamicrosystems C35 specialty process contains the superior analog/mixed-signal features that our applications demand” states James Kemerling, CTO and Co-Founder of Triad Semiconductor. “Highest manufacturing quality standards and the C35 process’ mixed signal capabilities combined with the ability to embed EEPROM and high voltage options makes this an ideal process to support our new Mocha-family of configurable SoCs.”
“Triad’s via-configurable array technology enables ASIC customers to rapidly develop prototypes of their products.” states Thomas Riener, General Manager Full Service Foundry at austriamicrosystems. “It helps shorten the development phase and supports fast product ramp-ups which ultimately results in a reduced time-to-profits. Once requiring high volume production, customers can either further optimize the VCA or easily change to pure ASIC manufacturing.”
Tuesday, July 28, 2009
Virage Logic extends IP technology leadership to 32/28nm process
Design Automation Conference 2009, SAN FRANCISCO, USA: Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP partner, today announced it has extended its advanced IP technology leadership to the 32/28-nanometer process node with the tape out of a product test chip with multiple IPs optimized for a high performance application for an early adopter customer.
The product test chip has advanced power management and at-speed test capabilities to address the power and yield challenges of 32/28nm and smaller geometries. In addition to the product test chip, Virage Logic has also taped out multiple 32nm test chips at leading foundries.
Because of Virage Logic’s proven track record of success at the 40nm process technology that includes multiple customers in production, the early adopter customer selected Virage Logic to leverage the power management capabilities of the SiWare memory compilers and advanced embedded memory test and repair capabilities of the STAR memory system for its first 32/28nm chip.
“Every new process node brings new manufacturing challenges that can impact overall design schedules and time to yield. At the advanced process nodes such as 32/28nm, the industry’s leaders will carefully select partners that enable them to proceed with confidence,” said Brani Buric, executive vice president of marketing and sales at Virage Logic.
“With more than ten 40nm customers, Virage Logic has once again proven that it has the technology leadership and know-how to provide its customers with early access to IP that meets their SoC design performance, cost and yield/ramp to volume goals.”
The product test chip has advanced power management and at-speed test capabilities to address the power and yield challenges of 32/28nm and smaller geometries. In addition to the product test chip, Virage Logic has also taped out multiple 32nm test chips at leading foundries.
Because of Virage Logic’s proven track record of success at the 40nm process technology that includes multiple customers in production, the early adopter customer selected Virage Logic to leverage the power management capabilities of the SiWare memory compilers and advanced embedded memory test and repair capabilities of the STAR memory system for its first 32/28nm chip.
“Every new process node brings new manufacturing challenges that can impact overall design schedules and time to yield. At the advanced process nodes such as 32/28nm, the industry’s leaders will carefully select partners that enable them to proceed with confidence,” said Brani Buric, executive vice president of marketing and sales at Virage Logic.
“With more than ten 40nm customers, Virage Logic has once again proven that it has the technology leadership and know-how to provide its customers with early access to IP that meets their SoC design performance, cost and yield/ramp to volume goals.”
ARM, Chartered, IBM, Samsung and Synopsys to deliver vertically optimized solution for 32/28nm mobile SoC designs
SAN FRANCISCO, USA: In a move that addresses fundamental challenges in creating advanced systems-on-chips (SoCs), ARM, Chartered Semiconductor Manufacturing Ltd, IBM, Samsung Electronics Co. Ltd and Synopsys Inc. announced at the Design Automation Conference (DAC) an agreement to develop a comprehensive technology enablement solution for the design and manufacture of mobile Internet-optimized devices.
The objective of this collaboration is to leverage innovations in material science, mobile multimedia implementation and SoC design to lower risk and improve time-to-market for advanced mobile products. This complete design chain collaboration of technology leaders intends to integrate the following components:
ARM high-performance, low-power processor architecture for mobile applications, and optimized suite of physical intellectual property (physical IP) 32/28nm low-power/low-leakage, high-k metal-gate (HKMG) synchronized foundry services through the Common Platform manufacturing alliance of IBM, Chartered and Samsung.
Synopsys Lynx Design System, including Galaxy Implementation Platform for SoC implementation, as well as DesignWare connectivity IP. As semiconductor technology approaches fundamental physical limits and design complexity reaches unprecedented levels, a deeper type of technical alignment is essential.
Going beyond an existing track record of successful cooperation at previous nodes, this agreement among ARM, the Common Platform companies, and Synopsys represents a new level of collaboration necessary to address the cost and technical challenges associated with advanced SoC design and manufacturing. This initiative aligns strategy, technology roadmaps and customer deliveries.
"The Common Platform alliance's expanded engagement approach with ARM, and now Synopsys, means working more closely together with earlier access to each other's technology innovations, integrating and optimizing our capabilities for clients," said Michael J. Cadigan, general manager, IBM Microelectronics Division, on behalf of the Common Platform alliance companies. "The benefits are clear and differentiated: lower risk, lower cost and faster time-to-market."
Combination of strengths
Each company brings unique technology and expertise that, when combined through joint collaboration, creates an optimized solution not available from other sources.
ARM brings a robust portfolio of logic, memory and interface IP, as well as its widely adopted Cortex processor family that is used in a broad array of mobile applications. ARM Physical IP optimized for the Common Platform 32/28nm process delivers valuable low-power and system cost benefits. The intention of this agreement is to ensure the IP is fully optimized with the Synopsys design flow.
"The complexity of advanced manufacturing process technology requires a tight connection between the Physical IP, processor cores and EDA methodology," said Warren East, CEO, ARM. "Early collaboration between these leading companies will significantly improve the performance, power and area achievable by our partners and deliver increased value to the end products."
Synopsys brings a suite of tool components from its Galaxy Implementation Platform, Lynx Design System and DesignWare connectivity IP providing the foundation of the solutions design flow. By tuning the automated front-to-back flow to run on Common Platform technology with ARM processor and physical IP, the flow is aimed at delivering a streamlined implementation path that can reduce the total cost of developing an optimized SoC, while helping speed time-to-market and reduce risk.
"This unique ARM-Synopsys-Common Platform collaboration can alleviate costs and risks by harnessing the leading players in silicon technology, IP, tools and flow enablement to integrate and optimize the path from software to silicon," said Aart de Geus, chairman and CEO of Synopsys.
"Through this alignment, we plan to deliver early 32/28 nanometer tool and IP enablement, plus a complete, vertically optimized design solution based on the Synopsys Lynx Design System to provide customers the lowest cost of design and fastest time-to-market for next-generation mobile SoC designs."
The Common Platform 32/28nm process uses an innovative high-k metal-gate (HKMG) approach to address the limitations of polysilicon technology. It leverages the research and development efforts of the IBM joint technology development alliance to offer a high-performance, low-power manufacturing platform. The process offering is available with synchronized foundry services from all three Common Platform companies, ensuring customer freedom of choice and maximum sourcing flexibility.
The collaborative effort began a year ago. Initial 32nm low-power tool and IP enablement has been released and a steady stream of early customer deliverables is targeted in the coming months. Supporting physical and processor IP, connectivity IP, process design kits and tools will be available from their respective suppliers.
Demonstrations of the technology based on initial test chips will be shown at the 2009 DAC in the ARM-Common Platform-Synopsys "Innovation Optimized" exhibit (booth #1114).
The objective of this collaboration is to leverage innovations in material science, mobile multimedia implementation and SoC design to lower risk and improve time-to-market for advanced mobile products. This complete design chain collaboration of technology leaders intends to integrate the following components:
ARM high-performance, low-power processor architecture for mobile applications, and optimized suite of physical intellectual property (physical IP) 32/28nm low-power/low-leakage, high-k metal-gate (HKMG) synchronized foundry services through the Common Platform manufacturing alliance of IBM, Chartered and Samsung.
Synopsys Lynx Design System, including Galaxy Implementation Platform for SoC implementation, as well as DesignWare connectivity IP. As semiconductor technology approaches fundamental physical limits and design complexity reaches unprecedented levels, a deeper type of technical alignment is essential.
Going beyond an existing track record of successful cooperation at previous nodes, this agreement among ARM, the Common Platform companies, and Synopsys represents a new level of collaboration necessary to address the cost and technical challenges associated with advanced SoC design and manufacturing. This initiative aligns strategy, technology roadmaps and customer deliveries.
"The Common Platform alliance's expanded engagement approach with ARM, and now Synopsys, means working more closely together with earlier access to each other's technology innovations, integrating and optimizing our capabilities for clients," said Michael J. Cadigan, general manager, IBM Microelectronics Division, on behalf of the Common Platform alliance companies. "The benefits are clear and differentiated: lower risk, lower cost and faster time-to-market."
Combination of strengths
Each company brings unique technology and expertise that, when combined through joint collaboration, creates an optimized solution not available from other sources.
ARM brings a robust portfolio of logic, memory and interface IP, as well as its widely adopted Cortex processor family that is used in a broad array of mobile applications. ARM Physical IP optimized for the Common Platform 32/28nm process delivers valuable low-power and system cost benefits. The intention of this agreement is to ensure the IP is fully optimized with the Synopsys design flow.
"The complexity of advanced manufacturing process technology requires a tight connection between the Physical IP, processor cores and EDA methodology," said Warren East, CEO, ARM. "Early collaboration between these leading companies will significantly improve the performance, power and area achievable by our partners and deliver increased value to the end products."
Synopsys brings a suite of tool components from its Galaxy Implementation Platform, Lynx Design System and DesignWare connectivity IP providing the foundation of the solutions design flow. By tuning the automated front-to-back flow to run on Common Platform technology with ARM processor and physical IP, the flow is aimed at delivering a streamlined implementation path that can reduce the total cost of developing an optimized SoC, while helping speed time-to-market and reduce risk.
"This unique ARM-Synopsys-Common Platform collaboration can alleviate costs and risks by harnessing the leading players in silicon technology, IP, tools and flow enablement to integrate and optimize the path from software to silicon," said Aart de Geus, chairman and CEO of Synopsys.
"Through this alignment, we plan to deliver early 32/28 nanometer tool and IP enablement, plus a complete, vertically optimized design solution based on the Synopsys Lynx Design System to provide customers the lowest cost of design and fastest time-to-market for next-generation mobile SoC designs."
The Common Platform 32/28nm process uses an innovative high-k metal-gate (HKMG) approach to address the limitations of polysilicon technology. It leverages the research and development efforts of the IBM joint technology development alliance to offer a high-performance, low-power manufacturing platform. The process offering is available with synchronized foundry services from all three Common Platform companies, ensuring customer freedom of choice and maximum sourcing flexibility.
The collaborative effort began a year ago. Initial 32nm low-power tool and IP enablement has been released and a steady stream of early customer deliverables is targeted in the coming months. Supporting physical and processor IP, connectivity IP, process design kits and tools will be available from their respective suppliers.
Demonstrations of the technology based on initial test chips will be shown at the 2009 DAC in the ARM-Common Platform-Synopsys "Innovation Optimized" exhibit (booth #1114).
Calypto's fully automated sequential optimization flow for high-performance IP blocks
SAN FRANCISCO, USA: Calypto Design Systems Inc. has announced a fully automated design flow aimed at advancing the delivery of optimized, high-performance IP blocks found in today’s leading SoC designs.
Enabled by Calypto’s SLEC RTL tool and new analysis capabilities in its proven PowerPro CG (clock gating) tool, Calypto’s Sequential Optimization Flow allows designers, for the first time, to use a fully automated flow to optimize power, area, and timing for high-performance IP blocks, such as microprocessors and digital signal processors (DSPs). Using the flow, designers are also assured that functionality is maintained throughout the process.
Calypto will demonstrate its Sequential Optimization Flow this week at its booth during the 2009 Design Automation Conference (DAC) held in San Francisco.
"With each new generation of electronics products, SoC designers are challenged to deliver higher performance functions that dissipate less power and occupy less silicon area than the previous generation," said Tom Sandoval, CEO of Calypto.
"We have developed an automated flow that dramatically reduces the design time and resources required to deliver low-power, high-performance, differentiated functionality. As a result, even small SoC design teams are enabled to efficiently meet their strict power, performance and area goals using an automated method that includes proven tools for both optimization and comprehensive verification."
Without an automated approach, design teams have been forced to engage in manual optimizations that can be costly, time consuming and error prone. This process frequently results in timing issues which, in turn, lead to increased circuit area and power consumption.
Moreover, manual optimizations require extensive resources and unique skill sets, making the process off-limits to smaller design teams. Calypto’s new Sequential Optimization Flow addresses these challenges.
Calypto's new Sequential Optimization Flow includes PowerPro CG, which takes an RTL design and automatically generates a power-optimized RTL design. Both the original and power-optimized RTL designs are run through a third-party synthesis tool, such as the Encounter RTL Compiler from Cadence Design Systems, Inc., to create two gate-level netlists.
With the new automated analysis capabilities of PowerPro CG, the timing and power consumption of both netlists are automatically analyzed so that targeted retiming synthesis can be run on the power-optimized, gate-level netlist. Using Calypto’s SLEC RTL, functional equivalence between the original RTL and the new timing- and power-optimized gate level netlist is verified.
By combining gate-level retiming with automated RTL power optimization and sequential logic equivalence checking, Calypto’s Sequential Optimization Flow enables SoC design teams to optimize power, area and timing for IP blocks and complex functions that were previously considered off-limits to such optimizations.
New sequential optimization flow @ DAC 2009
Calypto is showcasing the results of running the Sequential Optimization Flow on the Sun Microsystems OpenSPARC T1 processor core at the 2009 DAC. Sun has made this 64-bit, high-throughput, low-power core available to the public under the GNU v2.0 license.
Calypto will demonstrate how running the core through the flow results in a 24 percent power advantage and almost five percent area advantage over the original core, with no performance impact. DAC attendees will see, firsthand, the effectiveness of the flow. Details of the Sequential Optimization Flow and the results of using the flow on the OpenSPARC core will be provided.
Calypto will also demonstrate its full suite of PowerPro and SLEC products at this year's DAC in booth #1610, being held July 26-31 in San Francisco at the Moscone Center.
Available now, Calypto’s PowerPro CG runs on PC platforms running Linux and is priced at $295,000 (US) for a one-year, time-based license. Existing PowerPro CG customers will be upgraded to the new version at no charge. SLEC RTL is available now and is priced at $175,000 (US) for a one-year, time-based license. Synthesis solutions are available directly from their manufacturers.
Enabled by Calypto’s SLEC RTL tool and new analysis capabilities in its proven PowerPro CG (clock gating) tool, Calypto’s Sequential Optimization Flow allows designers, for the first time, to use a fully automated flow to optimize power, area, and timing for high-performance IP blocks, such as microprocessors and digital signal processors (DSPs). Using the flow, designers are also assured that functionality is maintained throughout the process.
Calypto will demonstrate its Sequential Optimization Flow this week at its booth during the 2009 Design Automation Conference (DAC) held in San Francisco.
"With each new generation of electronics products, SoC designers are challenged to deliver higher performance functions that dissipate less power and occupy less silicon area than the previous generation," said Tom Sandoval, CEO of Calypto.
"We have developed an automated flow that dramatically reduces the design time and resources required to deliver low-power, high-performance, differentiated functionality. As a result, even small SoC design teams are enabled to efficiently meet their strict power, performance and area goals using an automated method that includes proven tools for both optimization and comprehensive verification."
Without an automated approach, design teams have been forced to engage in manual optimizations that can be costly, time consuming and error prone. This process frequently results in timing issues which, in turn, lead to increased circuit area and power consumption.
Moreover, manual optimizations require extensive resources and unique skill sets, making the process off-limits to smaller design teams. Calypto’s new Sequential Optimization Flow addresses these challenges.
Calypto's new Sequential Optimization Flow includes PowerPro CG, which takes an RTL design and automatically generates a power-optimized RTL design. Both the original and power-optimized RTL designs are run through a third-party synthesis tool, such as the Encounter RTL Compiler from Cadence Design Systems, Inc., to create two gate-level netlists.
With the new automated analysis capabilities of PowerPro CG, the timing and power consumption of both netlists are automatically analyzed so that targeted retiming synthesis can be run on the power-optimized, gate-level netlist. Using Calypto’s SLEC RTL, functional equivalence between the original RTL and the new timing- and power-optimized gate level netlist is verified.
By combining gate-level retiming with automated RTL power optimization and sequential logic equivalence checking, Calypto’s Sequential Optimization Flow enables SoC design teams to optimize power, area and timing for IP blocks and complex functions that were previously considered off-limits to such optimizations.
New sequential optimization flow @ DAC 2009
Calypto is showcasing the results of running the Sequential Optimization Flow on the Sun Microsystems OpenSPARC T1 processor core at the 2009 DAC. Sun has made this 64-bit, high-throughput, low-power core available to the public under the GNU v2.0 license.
Calypto will demonstrate how running the core through the flow results in a 24 percent power advantage and almost five percent area advantage over the original core, with no performance impact. DAC attendees will see, firsthand, the effectiveness of the flow. Details of the Sequential Optimization Flow and the results of using the flow on the OpenSPARC core will be provided.
Calypto will also demonstrate its full suite of PowerPro and SLEC products at this year's DAC in booth #1610, being held July 26-31 in San Francisco at the Moscone Center.
Available now, Calypto’s PowerPro CG runs on PC platforms running Linux and is priced at $295,000 (US) for a one-year, time-based license. Existing PowerPro CG customers will be upgraded to the new version at no charge. SLEC RTL is available now and is priced at $175,000 (US) for a one-year, time-based license. Synthesis solutions are available directly from their manufacturers.
Synopsys, Mentor, CoWare join ARM Fast Models Enablement Program
CAMBRIDGE, UK: ARM announced at DAC, San Francisco, that CoWare, Mentor Graphics and Synopsys Inc. have joined the ARM Fast Models Enablement Program.
Members of the Program are able to integrate fully validated Fast Models from ARM, for a range of ARM processors, into their virtual platform environments and deliver to their customers.
This ensures that mutual customers can create complete ARM Powered virtual platforms using the design flow of their choice. By using virtual platforms built around ARM processor Fast Models, engineers can develop software well in advance of final hardware implementation, with application and driver software running at near to real-time system performance.
The Fast Models product family from ARM includes programmer's view (PV) models for the ARM9, ARM11 and Cortex families of processors, including the Cortex-A9 MPCore multicore processor. The Fast Model products also include configuration tools that enable the export of ARM processor-based subsystems with OSCI SystemC and TLM-2.0 compliant interfaces.
"We are seeing a growing demand for high-performance models in the industry," said John Cornish, EVP and general manager, System Design Division, ARM. "The TLM-2.0 interface enables our customers to combine our processor Fast Models with models of their other IP to create complete virtual platforms in the design environment of their choice."
"CoWare has successfully delivered Electronic System Virtualization solutions for ARM processor-based designs for many years supporting architecture design, verification, software development, integration and test. With our further engagement in this broader program covering the ARM Cortex Fast Models, we continue to expand this position to serve the growing needs of our joint customers," said Marc Serughetti, vice president of Marketing and Business Development at CoWare Inc.
"This integration and partnership is already proven and in use at several customers resulting in significant time-to-market benefits for those customers."
"Mentor’s Vista technology offers a comprehensive architecture design and prototyping solution that relies on fast processor and peripheral models as an essential part of the solution. The integration of the architecturally accurate ARM Fast Models into our Vista Platform will deliver significant value to our mutual customers," said Simon Bloch, Mentor Graphics vice president and general manager, design and synthesis division.
"In addition, ARM’s Fast Models are compatible with Vista’s TLM scalable modeling methodology that provides the timing and power layers essential for optimizing performance and power at the transaction level of abstraction."
"As a leading IP provider, Synopsys already provides OSCI TLM-2.0 compliant transaction-level models for several processor families including ARM and Synopsys DesignWare Cores and components for SoC infrastructure, AMBA interconnect, CoreConnect and PrimeCell peripherals in the Synopsys DesignWare System-level Library," said Frank Schirrmeister, director product marketing for the Solutions Group at Synopsys.
"The ARM PV Enablement Program allows our users to draw from a larger number of models and enables Synopsys to validate interoperability of Synopsys’ Innovator development environment for virtual platforms with ARM processor-based subsystems using Fast Models from ARM."
Availability
Fast Models Version 5.0 including the SystemC/TLM-2.0 compatible export capability is available for immediate licensing from ARM. 45-day evaluations are available through the Program members in concert with their respective integrated solutions through the PV Enablement Program.
Members of the Program are able to integrate fully validated Fast Models from ARM, for a range of ARM processors, into their virtual platform environments and deliver to their customers.
This ensures that mutual customers can create complete ARM Powered virtual platforms using the design flow of their choice. By using virtual platforms built around ARM processor Fast Models, engineers can develop software well in advance of final hardware implementation, with application and driver software running at near to real-time system performance.
The Fast Models product family from ARM includes programmer's view (PV) models for the ARM9, ARM11 and Cortex families of processors, including the Cortex-A9 MPCore multicore processor. The Fast Model products also include configuration tools that enable the export of ARM processor-based subsystems with OSCI SystemC and TLM-2.0 compliant interfaces.
"We are seeing a growing demand for high-performance models in the industry," said John Cornish, EVP and general manager, System Design Division, ARM. "The TLM-2.0 interface enables our customers to combine our processor Fast Models with models of their other IP to create complete virtual platforms in the design environment of their choice."
"CoWare has successfully delivered Electronic System Virtualization solutions for ARM processor-based designs for many years supporting architecture design, verification, software development, integration and test. With our further engagement in this broader program covering the ARM Cortex Fast Models, we continue to expand this position to serve the growing needs of our joint customers," said Marc Serughetti, vice president of Marketing and Business Development at CoWare Inc.
"This integration and partnership is already proven and in use at several customers resulting in significant time-to-market benefits for those customers."
"Mentor’s Vista technology offers a comprehensive architecture design and prototyping solution that relies on fast processor and peripheral models as an essential part of the solution. The integration of the architecturally accurate ARM Fast Models into our Vista Platform will deliver significant value to our mutual customers," said Simon Bloch, Mentor Graphics vice president and general manager, design and synthesis division.
"In addition, ARM’s Fast Models are compatible with Vista’s TLM scalable modeling methodology that provides the timing and power layers essential for optimizing performance and power at the transaction level of abstraction."
"As a leading IP provider, Synopsys already provides OSCI TLM-2.0 compliant transaction-level models for several processor families including ARM and Synopsys DesignWare Cores and components for SoC infrastructure, AMBA interconnect, CoreConnect and PrimeCell peripherals in the Synopsys DesignWare System-level Library," said Frank Schirrmeister, director product marketing for the Solutions Group at Synopsys.
"The ARM PV Enablement Program allows our users to draw from a larger number of models and enables Synopsys to validate interoperability of Synopsys’ Innovator development environment for virtual platforms with ARM processor-based subsystems using Fast Models from ARM."
Availability
Fast Models Version 5.0 including the SystemC/TLM-2.0 compatible export capability is available for immediate licensing from ARM. 45-day evaluations are available through the Program members in concert with their respective integrated solutions through the PV Enablement Program.
Monday, July 27, 2009
ST unveils latest advances in design methodologies at DAC 2009
SINGAPORE: STMicroelectronics will participate as presenter or co-author of several papers at the DAC 2009 (Design Automation Conference), which takes place from July 26-31, 2009, in San Francisco, California.
ST’s contributions to the conference cover advances in design methodologies and automation in the areas of 3-D stacking for complex SoC (System-on-Chip) ICs, physical- and system-level chip design, and IC reliability.
In the DAC 2009 ‘Management Day’ session, Philippe Magarshack, STMicroelectronics’ General Manager of Central CAD & Design Solutions will present: ‘3-D Stacking: Opportunities and Trends for Consumer SOCs’, which will discuss 3-D integration as a promising technology to extend the momentum of Moore’s Law into the next decade, offering higher transistor density, faster interconnects, heterogeneous technology integration, with potentially lower power, cost and faster time-to-market.
However, 3-D integration isn’t without challenges: the presentation discusses the need for a range of new capabilities including process technology, architectures, design methods and tools, and manufacturing-worthy test solutions to be developed before 3-D chips can be mass produced for consumer applications.
Also, as part of the Management Day, Magarshack will participate on the panel ‘Making Critical Decisions for Emerging SoC Development,’ which will discuss emerging solutions for complex nanometer SoCs and their economic impact.
ST is also presenting several papers in physical and system-level design, including the examination of architectural-level design and power-estimation techniques, and the design-automation of IP re-use.
The need to design differentiated SoC product derivatives in extremely narrow time windows is tackled by a paper from ST engineers. The paper describes the moving of design creation to higher levels of abstraction, presenting an ESL (Electronic System Level) design methodology as a solution to deal with the increasing design challenges in the industry. In addition, the paper explores solutions for optimal designs in terms of power performance and silicon die area.
Another paper describes how ST engineers have used the SPIRIT (Structure for Packaging, Integrating and Re-using IP within Tool flows) Consortium’s IP-XACT standards to enable IP reuse through design automation, to provide an SoC integration solution for ST’s program (with Freescale) for the fast development of new 32-bit automotive microcontroller families.
An approach to improving design productivity for digital consumer ICs is the subject of another paper. ST’s engineers propose allowing front-end designers to prototype the SoC at the architecture level, gaining early insight into potential implementation issues during the design capture stage.
Power management, also, is an increasingly important concern for both wireless and wired applications. ST engineers will present an architectural-level power planning and estimation system to manage the challenges to preserve power and extend battery life in portable products.
Testing and reliability are also addressed by ST’s engineers, in two papers. The first paper is a presentation on a low-power DFT (Design-For-Test) flow for multi-voltage designs and ATPG (Automatic Test Pattern Generation).
The second paper examines an approach for the reduction of EMI (Electromagnetic Interference) to produce very robust automotive IC designs.
ST’s contributions to the conference cover advances in design methodologies and automation in the areas of 3-D stacking for complex SoC (System-on-Chip) ICs, physical- and system-level chip design, and IC reliability.
In the DAC 2009 ‘Management Day’ session, Philippe Magarshack, STMicroelectronics’ General Manager of Central CAD & Design Solutions will present: ‘3-D Stacking: Opportunities and Trends for Consumer SOCs’, which will discuss 3-D integration as a promising technology to extend the momentum of Moore’s Law into the next decade, offering higher transistor density, faster interconnects, heterogeneous technology integration, with potentially lower power, cost and faster time-to-market.
However, 3-D integration isn’t without challenges: the presentation discusses the need for a range of new capabilities including process technology, architectures, design methods and tools, and manufacturing-worthy test solutions to be developed before 3-D chips can be mass produced for consumer applications.
Also, as part of the Management Day, Magarshack will participate on the panel ‘Making Critical Decisions for Emerging SoC Development,’ which will discuss emerging solutions for complex nanometer SoCs and their economic impact.
ST is also presenting several papers in physical and system-level design, including the examination of architectural-level design and power-estimation techniques, and the design-automation of IP re-use.
The need to design differentiated SoC product derivatives in extremely narrow time windows is tackled by a paper from ST engineers. The paper describes the moving of design creation to higher levels of abstraction, presenting an ESL (Electronic System Level) design methodology as a solution to deal with the increasing design challenges in the industry. In addition, the paper explores solutions for optimal designs in terms of power performance and silicon die area.
Another paper describes how ST engineers have used the SPIRIT (Structure for Packaging, Integrating and Re-using IP within Tool flows) Consortium’s IP-XACT standards to enable IP reuse through design automation, to provide an SoC integration solution for ST’s program (with Freescale) for the fast development of new 32-bit automotive microcontroller families.
An approach to improving design productivity for digital consumer ICs is the subject of another paper. ST’s engineers propose allowing front-end designers to prototype the SoC at the architecture level, gaining early insight into potential implementation issues during the design capture stage.
Power management, also, is an increasingly important concern for both wireless and wired applications. ST engineers will present an architectural-level power planning and estimation system to manage the challenges to preserve power and extend battery life in portable products.
Testing and reliability are also addressed by ST’s engineers, in two papers. The first paper is a presentation on a low-power DFT (Design-For-Test) flow for multi-voltage designs and ATPG (Automatic Test Pattern Generation).
The second paper examines an approach for the reduction of EMI (Electromagnetic Interference) to produce very robust automotive IC designs.
E-System unveils integrated signal and power integrity co-simulator
Design Automation Conference 2009, ATLANTA, USA: E-System Design Inc. unveiled a breakthrough solution that provides design engineers with superior visibility and predictability when simulating IC packaging and printed circuit board performance by allowing designers to accurately simulate critical paths up to complete designs for signoff before they are released to manufacturing.
By using a unique methodology (M-FDM) and IP exclusively licensed from the Georgia Institute of Technology, Sphinx is able to more accurately predict the coupling effects and return path discontinuities commonly seen in new IC packaging and PCB designs today.
This is especially critical for designers who would like for their new designs to consistently achieve first pass success and quick ramp-up to production.
Traditionally, IC package and printed circuit board designers have relied on full wave simulators to perform signal and power integrity simulations of their designs. However, full wave simulators only allow the designers to see small portions of their design and not all of the coupling effects in a complete design.
Existing Fast EM solvers on the other hand estimate performance and suffer from reduced accuracy versus full wave simulators.
By utilizing the Multi-layered Finite Difference Method (M-FDM), and accurately modeling return path discontinuities, interlayer coupling effects, including through gaps and apertures commonly found in most simple to full 3D SiP and PCB designs today, Sphinx is able to provide excellent accuracy, and can very quickly and efficiently simulate critical paths up to complete designs before they go to manufacturing.
“Most new IC package and printed circuit board designs today contain gaps such as package cavities, voltage islands, split planes, apertures between layers, and multiple reference planes leading to return path discontinuities,” said Madhavan Swaminathan, CTO, founder of E-System Design, and principal author of the book “Power Integrity Modeling and Design for Semiconductors and Systems (Prentice Hall)”.
“The interlayer coupling effects through these apertures can be very significant and if not considered, can lead to having to re-spin your design. Sphinx was designed to accurately simulate these effects, including gap fields, wrap around currents, and return path discontinuities (RPD’s). Sphinx was also designed to be very efficient and to allow the designer to simulate their complete design for sign-off before manufacturing.”
“We have evaluated 'Sphinx' as a signal and power integrity design tool and have found it to be superior to industry available tools in the market, providing increased productivity with its easy to use features for performing pre- and post-layout analysis,” said Moises Cases, Retired Distinguished Engineer, IBM Corp., President and CEO, The Cases Group, LLC.
“Sphinx’s modeling and simulation capabilities provide at least 10X faster simulation time in specific design applications with results correlating well with hardware measurements. This tool will be an asset to our existing design tool suite.”
“Considering how rapidly geometries are shrinking, frequencies are increasing, and diverse technologies are being combined onto SoC’s, SiP’s and PCB systems today, designers are faced with very significant challenges. At the same time, product design cycles are shrinking and time to market is critical for new product success and profitability. Designers need a tool which they can use to accurately simulate their designs and confidently release those designs to manufacturing,” said Gene Jakubowski, CEO and co-founder of E-System Design.
“Sphinx is that tool, because of its accuracy and ability to simulate complete designs, it is the only viable sign off tool for IC packaging and printed circuit boards in the industry today.”
By using a unique methodology (M-FDM) and IP exclusively licensed from the Georgia Institute of Technology, Sphinx is able to more accurately predict the coupling effects and return path discontinuities commonly seen in new IC packaging and PCB designs today.
This is especially critical for designers who would like for their new designs to consistently achieve first pass success and quick ramp-up to production.
Traditionally, IC package and printed circuit board designers have relied on full wave simulators to perform signal and power integrity simulations of their designs. However, full wave simulators only allow the designers to see small portions of their design and not all of the coupling effects in a complete design.
Existing Fast EM solvers on the other hand estimate performance and suffer from reduced accuracy versus full wave simulators.
By utilizing the Multi-layered Finite Difference Method (M-FDM), and accurately modeling return path discontinuities, interlayer coupling effects, including through gaps and apertures commonly found in most simple to full 3D SiP and PCB designs today, Sphinx is able to provide excellent accuracy, and can very quickly and efficiently simulate critical paths up to complete designs before they go to manufacturing.
“Most new IC package and printed circuit board designs today contain gaps such as package cavities, voltage islands, split planes, apertures between layers, and multiple reference planes leading to return path discontinuities,” said Madhavan Swaminathan, CTO, founder of E-System Design, and principal author of the book “Power Integrity Modeling and Design for Semiconductors and Systems (Prentice Hall)”.
“The interlayer coupling effects through these apertures can be very significant and if not considered, can lead to having to re-spin your design. Sphinx was designed to accurately simulate these effects, including gap fields, wrap around currents, and return path discontinuities (RPD’s). Sphinx was also designed to be very efficient and to allow the designer to simulate their complete design for sign-off before manufacturing.”
“We have evaluated 'Sphinx' as a signal and power integrity design tool and have found it to be superior to industry available tools in the market, providing increased productivity with its easy to use features for performing pre- and post-layout analysis,” said Moises Cases, Retired Distinguished Engineer, IBM Corp., President and CEO, The Cases Group, LLC.
“Sphinx’s modeling and simulation capabilities provide at least 10X faster simulation time in specific design applications with results correlating well with hardware measurements. This tool will be an asset to our existing design tool suite.”
“Considering how rapidly geometries are shrinking, frequencies are increasing, and diverse technologies are being combined onto SoC’s, SiP’s and PCB systems today, designers are faced with very significant challenges. At the same time, product design cycles are shrinking and time to market is critical for new product success and profitability. Designers need a tool which they can use to accurately simulate their designs and confidently release those designs to manufacturing,” said Gene Jakubowski, CEO and co-founder of E-System Design.
“Sphinx is that tool, because of its accuracy and ability to simulate complete designs, it is the only viable sign off tool for IC packaging and printed circuit boards in the industry today.”
Wednesday, July 22, 2009
See EVE break billion-gate barrier at DAC
Design Automation Conference 2009, SAN JOSE, USA: Stop by the EVE booth (#908, South Hall) at the 46th Design Automation Conference (DAC) July 27-30 at the Moscone Center in San Francisco to see firsthand how it broke the billion-gate barrier.
As the leader in hardware/software co-verification, EVE last week launched ZeBu-Server, a scalable and affordable emulation system capable of handling up to one-billion application specific integrated circuit (ASIC) gates that will be continuously demonstrated during DAC.
Additionally, EVE will host three educational sessions at its booth. The first is on emulation for billion gate-designs. Another covers emulation with electronic system level (ESL) virtual platforms. The third will introduce an emulation smart debug methodology.
As the leader in hardware/software co-verification, EVE last week launched ZeBu-Server, a scalable and affordable emulation system capable of handling up to one-billion application specific integrated circuit (ASIC) gates that will be continuously demonstrated during DAC.
Additionally, EVE will host three educational sessions at its booth. The first is on emulation for billion gate-designs. Another covers emulation with electronic system level (ESL) virtual platforms. The third will introduce an emulation smart debug methodology.
Tuesday, July 21, 2009
46th DAC welcomes 29 new exhibitors
LOUISVILLE, USA: The Design Automation Conference (DAC) announced that it will feature 29 companies exhibiting at this year’s conference for the first time.
The new exhibitors include companies ranging from providers of design tools and data management solutions to product development experts and placement firms. The 46th DAC will be held July 26–31 at the Moscone Center in San Francisco and DAC exhibit hours will be 9 a.m. to 6 p.m. Monday, July 27 through Wednesday, July 29 and 9 a.m. to 1 p.m. on Thursday, July 30.
This year, the DAC exhibit floor features almost 200 companies. Access to exhibits is available through full-conference, exhibit-only, or Free Monday registration.
Exhibit-only registration offers access to all four days of the Exhibition, the keynote sessions, including the plenary CEO keynote panel, all DAC Pavilion and Exhibitor Forum sessions, plus the new IC Design Central Partner pavilion.
Free Monday registration permits access to the exhibition and the plenary CEO keynote panel on Monday, July 27.
“This robust list of first-time DAC exhibitors reflects the diversity of the innovation taking place in the industry, and reflects the role DAC plays as the premier venue for introducing new solutions and connecting with customers and partners,” said Andrew B. Kahng, general chair, 46th DAC Executive Committee.
“We are very pleased to welcome this year’s new exhibitors, and we look forward to the excitement they will bring to the exhibit floor.”
The following companies and organizations will be exhibiting at DAC for the first time this year:
Achilles Test Systems Inc.; Agnisys Inc.; Altair Engineering Inc.; AnSyn; APAC IC Layout Consultant Inc.; ATEEDA Ltd; BEEcube; Cambridge Analog Technologies Inc.; Chipworks; CST of America Inc.; Desaut Inc.; DOCEA Power; E-System Design Inc.;
Enterpoint; Epoch Microelectronics Inc.; Fidus Systems Inc.; Innovative Logic Inc.;
Logic Perspective Technology Inc.; Mephisto Design Automation; MethodICs LLC;
NextOp Software Inc.; Optiwave Systems Inc.; OVM World; R³ Logic Inc.; SKILLCAD Inc., Tiempo; Warthman Associates; XJTAG; and Z2 Innovation.
The new exhibitors include companies ranging from providers of design tools and data management solutions to product development experts and placement firms. The 46th DAC will be held July 26–31 at the Moscone Center in San Francisco and DAC exhibit hours will be 9 a.m. to 6 p.m. Monday, July 27 through Wednesday, July 29 and 9 a.m. to 1 p.m. on Thursday, July 30.
This year, the DAC exhibit floor features almost 200 companies. Access to exhibits is available through full-conference, exhibit-only, or Free Monday registration.
Exhibit-only registration offers access to all four days of the Exhibition, the keynote sessions, including the plenary CEO keynote panel, all DAC Pavilion and Exhibitor Forum sessions, plus the new IC Design Central Partner pavilion.
Free Monday registration permits access to the exhibition and the plenary CEO keynote panel on Monday, July 27.
“This robust list of first-time DAC exhibitors reflects the diversity of the innovation taking place in the industry, and reflects the role DAC plays as the premier venue for introducing new solutions and connecting with customers and partners,” said Andrew B. Kahng, general chair, 46th DAC Executive Committee.
“We are very pleased to welcome this year’s new exhibitors, and we look forward to the excitement they will bring to the exhibit floor.”
The following companies and organizations will be exhibiting at DAC for the first time this year:
Achilles Test Systems Inc.; Agnisys Inc.; Altair Engineering Inc.; AnSyn; APAC IC Layout Consultant Inc.; ATEEDA Ltd; BEEcube; Cambridge Analog Technologies Inc.; Chipworks; CST of America Inc.; Desaut Inc.; DOCEA Power; E-System Design Inc.;
Enterpoint; Epoch Microelectronics Inc.; Fidus Systems Inc.; Innovative Logic Inc.;
Logic Perspective Technology Inc.; Mephisto Design Automation; MethodICs LLC;
NextOp Software Inc.; Optiwave Systems Inc.; OVM World; R³ Logic Inc.; SKILLCAD Inc., Tiempo; Warthman Associates; XJTAG; and Z2 Innovation.
Monday, July 20, 2009
Calypto enables ESL design, verification of complex designs
Design Automation Conference 2009, SANTA CLARA, USA: Enabling electronic system level (ESL) design flows for increasingly complex system on a chip (SOC) devices, Calypto Design Systems Inc. announced the release of SLEC 4.0, the latest version of its popular sequential logic equivalence checking (SLEC) product family.
SLEC is the semiconductor industry’s only comprehensive functional verification solution that formally verifies equivalence between ESL models and RTL implementations. The new version has up to five times the capacity of the previous version and provides tighter integration with the leading high-level synthesis (HLS) tools from Cadence Design Systems, Mentor Graphics, and Forte.
“HLS tools are becoming more efficient at handling larger functions. As a result, customers are applying HLS tools to design blocks with significant complexity, especially from a sequential perspective,” said Tom Sandoval, CEO of Calypto Design Systems.
“SLEC 4.0 keeps pace with the most sophisticated designs and provides an automated path to comprehensive verification with the industry’s only proven sequential equivalence checker. With SLEC, designers can avoid running time-consuming simulations and can uncover bugs that might otherwise go undetected and cause catastrophic delays to product development timelines.”
Calypto pioneered sequential logic equivalence checking when it announced its first version of SLEC nearly five years ago. Since that time, SLEC’s capacity has grown from thousand-gate blocks and tens of cycles of sequential complexity to hundreds of thousands of gates and thousands of cycles of sequential complexity.
The verification challenges have increased exponentially with these more sophisticated functions, making traditional simulation-based verification even less effective.
Optimized database and improved integration with HLS tools
Featuring algorithmic enhancements to Calypto’s patented word level solvers, the latest version of SLEC also includes dramatic improvement to SLEC’s proprietary database that results in a reduced memory footprint while SLEC is running. Together, these advancements enable the tool to handle larger, more complex designs.
As a result, designers can more freely use high level synthesis for the generation of highly complex functions, knowing that SLEC can provide comprehensive verification. The interface between SLEC and the leading HLS tools — Mentor Catapult, Cadence C-to-Silicon compiler, and Forte Cynthesizer — has also been improved in SLEC 4.0 to ensure an automated, efficient path to formal verification, requiring little or no user intervention.
Multiple clock support added
The ability to handle multiple clock designs has traditionally been a limitation with sequential logic equivalence checking. As SLEC capacity has increased, allowing the tool to support larger and more complex graphics, networking, multimedia, and wireless functions, the need to comprehensively verify designs with multiple clocks has become more and more prevalent.
With version 4.0, SLEC customers can now fully verify designs with multiple, independent clocks. For example, SLEC RTL can verify that the relationship between two clocks -- e.g., one clock is a multiple of another) is not disrupted by the manual introduction of sequential optimizations for power or performance by a designer. SLEC RTL can also now detect the illegal mixing of signals from different clock domains introduced by sequential transformations.
The SLEC family of products includes:
* SLEC System: Formally verifies equivalence of system-level models and RTL designs.
* SLEC System-HLS: Formally verifies that an RTL design generated using high-level synthesis is functionally equivalent to its corresponding system level model.
* SLEC RTL: Formally ensures functional equivalence between a golden RTL model and a corresponding RTL model has been sequentially modified to reduce power or improve performance.
* SLEC Pro: Comprehensively verifies that an RTL design generated by Calypto’s PowerPro product is functionally equivalent to its corresponding golden RTL model.
* SLEC 4.0 Showcased at 2009 DAC, Calypto to Present and Co-host Luncheon.
SLEC is the semiconductor industry’s only comprehensive functional verification solution that formally verifies equivalence between ESL models and RTL implementations. The new version has up to five times the capacity of the previous version and provides tighter integration with the leading high-level synthesis (HLS) tools from Cadence Design Systems, Mentor Graphics, and Forte.
“HLS tools are becoming more efficient at handling larger functions. As a result, customers are applying HLS tools to design blocks with significant complexity, especially from a sequential perspective,” said Tom Sandoval, CEO of Calypto Design Systems.
“SLEC 4.0 keeps pace with the most sophisticated designs and provides an automated path to comprehensive verification with the industry’s only proven sequential equivalence checker. With SLEC, designers can avoid running time-consuming simulations and can uncover bugs that might otherwise go undetected and cause catastrophic delays to product development timelines.”
Calypto pioneered sequential logic equivalence checking when it announced its first version of SLEC nearly five years ago. Since that time, SLEC’s capacity has grown from thousand-gate blocks and tens of cycles of sequential complexity to hundreds of thousands of gates and thousands of cycles of sequential complexity.
The verification challenges have increased exponentially with these more sophisticated functions, making traditional simulation-based verification even less effective.
Optimized database and improved integration with HLS tools
Featuring algorithmic enhancements to Calypto’s patented word level solvers, the latest version of SLEC also includes dramatic improvement to SLEC’s proprietary database that results in a reduced memory footprint while SLEC is running. Together, these advancements enable the tool to handle larger, more complex designs.
As a result, designers can more freely use high level synthesis for the generation of highly complex functions, knowing that SLEC can provide comprehensive verification. The interface between SLEC and the leading HLS tools — Mentor Catapult, Cadence C-to-Silicon compiler, and Forte Cynthesizer — has also been improved in SLEC 4.0 to ensure an automated, efficient path to formal verification, requiring little or no user intervention.
Multiple clock support added
The ability to handle multiple clock designs has traditionally been a limitation with sequential logic equivalence checking. As SLEC capacity has increased, allowing the tool to support larger and more complex graphics, networking, multimedia, and wireless functions, the need to comprehensively verify designs with multiple clocks has become more and more prevalent.
With version 4.0, SLEC customers can now fully verify designs with multiple, independent clocks. For example, SLEC RTL can verify that the relationship between two clocks -- e.g., one clock is a multiple of another) is not disrupted by the manual introduction of sequential optimizations for power or performance by a designer. SLEC RTL can also now detect the illegal mixing of signals from different clock domains introduced by sequential transformations.
The SLEC family of products includes:
* SLEC System: Formally verifies equivalence of system-level models and RTL designs.
* SLEC System-HLS: Formally verifies that an RTL design generated using high-level synthesis is functionally equivalent to its corresponding system level model.
* SLEC RTL: Formally ensures functional equivalence between a golden RTL model and a corresponding RTL model has been sequentially modified to reduce power or improve performance.
* SLEC Pro: Comprehensively verifies that an RTL design generated by Calypto’s PowerPro product is functionally equivalent to its corresponding golden RTL model.
* SLEC 4.0 Showcased at 2009 DAC, Calypto to Present and Co-host Luncheon.
Saturday, July 18, 2009
Si2 announces board of directors for 2009-2010
Design Automation Conference 2009, AUSTIN, USA: The Silicon Integration Initiative (Si2) announced the election of its Board of Directors for the 2009-2010 term, as well as the place and time for the Annual Member/Guest Meeting.
The newest elected Board member is Charlie Huang, senior vice president and chief strategy officer at Cadence Design Systems, Inc., who replaces the previous Board representative from Cadence.
The re-elected Board Members and their representatives are:
AMD – Ward Vercruysse, director and fellow;
ARM Inc. - John Goodenough, world wide director Design Technology;
IBM Microelectronics – Leon Stock, director, EDA;
Intel Corp. - Rahul Goyal, director, EDA Business;
LSI - Ameesh Desai, senior director, Design Tools & Methodology;
National Semiconductor - James Lin, vice president of Technology Infrastructure;
NXP – Barry Dennington, sr. vice president;
Sequence Design - Vic Kulkarni, president & CEO; and
Synopsys - John Chilton, sr. vice president, Marketing & Strategic Development.
“I offer a warm welcome to Charlie as our newest elected Board member, and congratulate all returning Board members. We are extremely pleased to have their insight and expertise on the strategic and business affairs of Si2,” said Steve Schulz, president & CEO.
“I am delighted to join the Si2 Board and look forward to taking an active role in this vital organization,” said Huang. “Si2’s ongoing commitment to developing open and inclusive standards in critical areas such as OpenAccess, library modeling and characterization, DFM, and low-power design flows, drives innovation in EDA and benefits the IC industry and the broader electronics ecosystem.”
The newest elected Board member is Charlie Huang, senior vice president and chief strategy officer at Cadence Design Systems, Inc., who replaces the previous Board representative from Cadence.
The re-elected Board Members and their representatives are:
AMD – Ward Vercruysse, director and fellow;
ARM Inc. - John Goodenough, world wide director Design Technology;
IBM Microelectronics – Leon Stock, director, EDA;
Intel Corp. - Rahul Goyal, director, EDA Business;
LSI - Ameesh Desai, senior director, Design Tools & Methodology;
National Semiconductor - James Lin, vice president of Technology Infrastructure;
NXP – Barry Dennington, sr. vice president;
Sequence Design - Vic Kulkarni, president & CEO; and
Synopsys - John Chilton, sr. vice president, Marketing & Strategic Development.
“I offer a warm welcome to Charlie as our newest elected Board member, and congratulate all returning Board members. We are extremely pleased to have their insight and expertise on the strategic and business affairs of Si2,” said Steve Schulz, president & CEO.
“I am delighted to join the Si2 Board and look forward to taking an active role in this vital organization,” said Huang. “Si2’s ongoing commitment to developing open and inclusive standards in critical areas such as OpenAccess, library modeling and characterization, DFM, and low-power design flows, drives innovation in EDA and benefits the IC industry and the broader electronics ecosystem.”
Wednesday, July 15, 2009
Atrenta, Mentor Graphics ally on power optimization for high-level synthesis
Design Automation Conference 2009, SAN JOSE, USA: Atrenta Inc. a leading provider of Early Design Closure solutions to radically improve design efficiency throughout the IC design flow, announced a collaboration with Mentor Graphics Corp. on an high-level synthesis power optimization flow.
The collaboration between the two companies has resulted in an interface between Mentor’s Catapult C Synthesis high-level synthesis tool and Atrenta’s SpyGlass-Power RTL power estimation and reduction tool to automate multi-level clock gating, an important technique used by designers in low-power designs.
According to Mentor Graphics, Catapult is the industry’s leading high-level synthesis tool and offers the fastest path to verified RTL from pure C++. With its new low-power optimizations, Catapult will thoroughly analyze the design to determine gateable clocks and build the appropriate logic -- an often error-prone and tedious task when done manually at the backend of the design flow. This new technology delivers near 100 percent perfect clock gating.
The resulting RTL output from Catapult is then seamlessly handed off to SpyGlass-Power, which examines every clock gating candidate identified by Catapult, measures the potential power savings, and determines which particular candidates should be included or excluded from the clock gating insertion process.
The static and dynamic power estimates from SpyGlass-Power are fed back into Catapult C for performance, area and power tradeoff analysis, and the resulting RTL netlist is then available to downstream RTL synthesis tools, resulting in a very efficient low-power design implementation.
According to Mentor Graphics, dynamic power savings for clock gating is design and test vector dependent, however measurements on more than 300 customer designs showed improvements ranging from 10 to 90 percent with an average improvement of 40 percent.
“By using a power-aware high-level synthesis flow starting from C++, designers have at their disposal a design methodology that makes power consumption a key design metric right at the start of the design process, where it can have the maximum impact,” said Shawn McCloud, product line director for High-Level Products at Mentor Graphics.
“The collaboration with Atrenta and their SpyGlass product significantly enhances the flow by quantifying power savings and ensuring that the generated RTL is power optimized.”
“The collaboration with Mentor and Catapult C provides users of high-level synthesis with the benefits of RTL analysis and optimization from our SpyGlass platform, especially for power estimation and reduction,” said Kiran Vittal, product marketing director of power and test products at Atrenta. “Power optimization is an important focus area for Atrenta. Several new capabilities to support better power optimization will be announced in the coming months.”
Atrenta and Mentor Graphics will showcase the results of this collaboration in a joint demonstration of an ESL-to-RTL power optimization flow in Atrenta’s booth at the 46th Design Automation Conference (DAC) in San Francisco.
The Catapult/SpyGlass flow is available now. The respective tools can be purchased from Mentor Graphics and Atrenta.
The collaboration between the two companies has resulted in an interface between Mentor’s Catapult C Synthesis high-level synthesis tool and Atrenta’s SpyGlass-Power RTL power estimation and reduction tool to automate multi-level clock gating, an important technique used by designers in low-power designs.
According to Mentor Graphics, Catapult is the industry’s leading high-level synthesis tool and offers the fastest path to verified RTL from pure C++. With its new low-power optimizations, Catapult will thoroughly analyze the design to determine gateable clocks and build the appropriate logic -- an often error-prone and tedious task when done manually at the backend of the design flow. This new technology delivers near 100 percent perfect clock gating.
The resulting RTL output from Catapult is then seamlessly handed off to SpyGlass-Power, which examines every clock gating candidate identified by Catapult, measures the potential power savings, and determines which particular candidates should be included or excluded from the clock gating insertion process.
The static and dynamic power estimates from SpyGlass-Power are fed back into Catapult C for performance, area and power tradeoff analysis, and the resulting RTL netlist is then available to downstream RTL synthesis tools, resulting in a very efficient low-power design implementation.
According to Mentor Graphics, dynamic power savings for clock gating is design and test vector dependent, however measurements on more than 300 customer designs showed improvements ranging from 10 to 90 percent with an average improvement of 40 percent.
“By using a power-aware high-level synthesis flow starting from C++, designers have at their disposal a design methodology that makes power consumption a key design metric right at the start of the design process, where it can have the maximum impact,” said Shawn McCloud, product line director for High-Level Products at Mentor Graphics.
“The collaboration with Atrenta and their SpyGlass product significantly enhances the flow by quantifying power savings and ensuring that the generated RTL is power optimized.”
“The collaboration with Mentor and Catapult C provides users of high-level synthesis with the benefits of RTL analysis and optimization from our SpyGlass platform, especially for power estimation and reduction,” said Kiran Vittal, product marketing director of power and test products at Atrenta. “Power optimization is an important focus area for Atrenta. Several new capabilities to support better power optimization will be announced in the coming months.”
Atrenta and Mentor Graphics will showcase the results of this collaboration in a joint demonstration of an ESL-to-RTL power optimization flow in Atrenta’s booth at the 46th Design Automation Conference (DAC) in San Francisco.
The Catapult/SpyGlass flow is available now. The respective tools can be purchased from Mentor Graphics and Atrenta.
Magwel's breakthrough EDA products for power management ICs
Design Automation Conference 2009, SAN JOSE, USA: Magwel NV, the leader in 3D co-simulation and extraction solutions, is announcing the release and immediate availability of two breakthrough EDA products for design and verification of power management ICs.
Power Transistor Modeler (PTM) extracts the series-on-resistance (Rdson) of very large power transistor arrays with 3D simulation accuracy in record time. Current hot-spots and electro-migration problems are highlighted directly on the GDS layout. Automatic GDS input and geometric processing make this tool easy to use by designers.
Substrate Noise Modeler (SNM) analyzes substrate noise injection (both minority and majority carrier injections) and noise coupling to sensitive circuits, which is typically found in power management devices. SNM takes GDS layout and technology information as input and provides 3D device simulation accuracy with very fast simulation speed.
“2D and 2.5D extractors are not adequate to deal with the complex, non-uniform current flows in power devices. Due to this lack of accurate tools, designers often over-design to avoid reliability problems,” said Dündar Dumlugöl, Chairman and CEO of Magwel. He added, “PTM simulates some of the largest power transistors in the industry in a matter of hours on standard workstations pinpointing potential electro-migration problems.”
SNM was developed to address substrate noise problems typically found in switching power regulators. SNM models drift-diffusion equations in the substrate with advanced carrier mobility and recombination models to provide excellent match with silicon.
Dumlugöl said: “SNM is unique in the sense that it combines the accuracy of a true 3D device simulator with the speed and capacity necessary to handle large scale problems. This has been achieved through a combination of intelligent meshing and advanced numerical techniques.”
PTM and SNM have been extensively validated at leading power management IC vendors.
Magwel will demonstrate these products at DAC'09 conference in San Francisco, CA in booth #3357.
Power Transistor Modeler (PTM) extracts the series-on-resistance (Rdson) of very large power transistor arrays with 3D simulation accuracy in record time. Current hot-spots and electro-migration problems are highlighted directly on the GDS layout. Automatic GDS input and geometric processing make this tool easy to use by designers.
Substrate Noise Modeler (SNM) analyzes substrate noise injection (both minority and majority carrier injections) and noise coupling to sensitive circuits, which is typically found in power management devices. SNM takes GDS layout and technology information as input and provides 3D device simulation accuracy with very fast simulation speed.
“2D and 2.5D extractors are not adequate to deal with the complex, non-uniform current flows in power devices. Due to this lack of accurate tools, designers often over-design to avoid reliability problems,” said Dündar Dumlugöl, Chairman and CEO of Magwel. He added, “PTM simulates some of the largest power transistors in the industry in a matter of hours on standard workstations pinpointing potential electro-migration problems.”
SNM was developed to address substrate noise problems typically found in switching power regulators. SNM models drift-diffusion equations in the substrate with advanced carrier mobility and recombination models to provide excellent match with silicon.
Dumlugöl said: “SNM is unique in the sense that it combines the accuracy of a true 3D device simulator with the speed and capacity necessary to handle large scale problems. This has been achieved through a combination of intelligent meshing and advanced numerical techniques.”
PTM and SNM have been extensively validated at leading power management IC vendors.
Magwel will demonstrate these products at DAC'09 conference in San Francisco, CA in booth #3357.
Tuesday, July 14, 2009
46th DAC offers six workshops
Design Automation Conference 2009, LOUISVILLE, USA: Six workshops created to appeal to the interests of the entire DAC community will be offered at the 46th Design Automation Conference (DAC) July 26-31 at the Moscone Center in San Francisco. Attendees of the 46th DAC can learn about front- or back-end design issues, or participate in several special-interest workshops.
“This year’s workshop lineup will give attendees new insights and unforeseen knowledge,” said Diana Marculescu, 46th DAC Coordinator for Workshops and Colocated Events and ACM/SIGDA Representative. “Perhaps even more important, workshop participants will benefit from the opportunity for networking with their industry peers, which is one of the special benefits of DAC.”
Workshops on Front-End Tools and Methodologies
For designers working with multiprocessor designs, the workshop “MPSoC: Current Trends and the Future” on Sunday, July 26, will allow them to hear from an impressive list of speakers covering topics of interest in the design tools, methodologies, and programming of Multiprocessor Systems-on-Chip (MPSoCs).
The full-day “Virtual Platform Workshop” on Wednesday, July 29, strongly complements the new DAC User Track in addressing the latest SoC design challenges. This workshop is designed to bring together people interested in the use of Virtual Platforms (VPs) in SoC design validation and embedded software development.
Developing a Go-to-Market Strategy
The half-day workshop on “Marketing of Technology - the Last Critical Step” scheduled on Sunday, July 26, should appeal to the technically-trained professional charged with launching the company’s next big product. The workshop will cover product marketing from a semiconductor perspective and with an emphasis on new Web 2.0 tools. Participants will learn about hands-on tools they can use in their own work.
Emerging Applications for EDA
The International Workshop on Bio-Design Automation (IWBDA) on Monday, July 27, will be of interest for any DAC attendee who is following the emerging use of EDA in new areas.
It will feature invited talks by experts in the field of synthetic biology, contributed presentations, and an interactive poster session all focused on concepts, methodologies and software tools for the automated synthesis of novel biological functions.
Career Advice
Two workshops will focus on the unique challenges and opportunities of two very different stages of a career. The new full-day “Young Faculty Workshop” scheduled on Monday, July 27, will bring senior graduate students interested in academia, as well as EDA professionals ready for a career move, together with senior faculty, funding agency program managers, and senior industry professionals who will share their views and experiences on succeeding as a faculty member in EDA.
Also on Monday, July 27, the 10th annual “Workshop for Women in Design Automation” (WWINDA) will focus on issues surrounding the choice between a technical career path and the management track. Dr. Telle Whitney, president and CEO of the Anita Borg Institute, will give the workshop’s opening keynote address which will be followed by an interactive panel discussion on this year’s WWINDA theme, “Career Crossroads - Who Has the Map?”
“This year’s workshop lineup will give attendees new insights and unforeseen knowledge,” said Diana Marculescu, 46th DAC Coordinator for Workshops and Colocated Events and ACM/SIGDA Representative. “Perhaps even more important, workshop participants will benefit from the opportunity for networking with their industry peers, which is one of the special benefits of DAC.”
Workshops on Front-End Tools and Methodologies
For designers working with multiprocessor designs, the workshop “MPSoC: Current Trends and the Future” on Sunday, July 26, will allow them to hear from an impressive list of speakers covering topics of interest in the design tools, methodologies, and programming of Multiprocessor Systems-on-Chip (MPSoCs).
The full-day “Virtual Platform Workshop” on Wednesday, July 29, strongly complements the new DAC User Track in addressing the latest SoC design challenges. This workshop is designed to bring together people interested in the use of Virtual Platforms (VPs) in SoC design validation and embedded software development.
Developing a Go-to-Market Strategy
The half-day workshop on “Marketing of Technology - the Last Critical Step” scheduled on Sunday, July 26, should appeal to the technically-trained professional charged with launching the company’s next big product. The workshop will cover product marketing from a semiconductor perspective and with an emphasis on new Web 2.0 tools. Participants will learn about hands-on tools they can use in their own work.
Emerging Applications for EDA
The International Workshop on Bio-Design Automation (IWBDA) on Monday, July 27, will be of interest for any DAC attendee who is following the emerging use of EDA in new areas.
It will feature invited talks by experts in the field of synthetic biology, contributed presentations, and an interactive poster session all focused on concepts, methodologies and software tools for the automated synthesis of novel biological functions.
Career Advice
Two workshops will focus on the unique challenges and opportunities of two very different stages of a career. The new full-day “Young Faculty Workshop” scheduled on Monday, July 27, will bring senior graduate students interested in academia, as well as EDA professionals ready for a career move, together with senior faculty, funding agency program managers, and senior industry professionals who will share their views and experiences on succeeding as a faculty member in EDA.
Also on Monday, July 27, the 10th annual “Workshop for Women in Design Automation” (WWINDA) will focus on issues surrounding the choice between a technical career path and the management track. Dr. Telle Whitney, president and CEO of the Anita Borg Institute, will give the workshop’s opening keynote address which will be followed by an interactive panel discussion on this year’s WWINDA theme, “Career Crossroads - Who Has the Map?”
Monday, July 13, 2009
Sequence enabling design for power (DFP)
Design Automation Conference 2009, SUNNYVALE, USA: Sequence Design, the EDA leader Enabling Design For Power (DFP), will introduce a new version of its award-winning PowerArtist at this year’s DAC, Booth 3455, combining RTL power analysis and automatic power reduction all within an integrated environment.
For information on demos, products, and all other news and events mentioned in this announcement, visit: http://www.sequencedesign.com/newsevents/events.php.
The latest PowerArtist power-reduction breakthrough is but a part of the company’s DAC lineup this year, which includes:
Enabling Design For Power
A range of solutions with a legacy of proven results speed design closure while ensuring accuracy:
● PowerArtist, automatic analysis and reduction
● PowerTheater, unmatched precision at RTL
● CoolProducts, advanced features for power-grid integrity
● Columbus, sets the standard for extraction technology
Sequence will participate in multiple industry events during the show, including:
●Sunday, 1pm, Room 130
CTO Jerry Frenkil at Si2 Workshop Presents “LPC Models for Low Power”
●Tuesday, 3pm, Booth 4359
CTO Jerry Frenkil Presents “Designing for Power”
“DAC is the glue that binds us,” said Vic Kulkarni, Sequence President and CEO. “It’s the only time we’re all together in one big room with the most brilliant minds in high tech, and I’m really looking forward to seeing all of our dear friends and customers in San Francisco.”
For information on demos, products, and all other news and events mentioned in this announcement, visit: http://www.sequencedesign.com/newsevents/events.php.
The latest PowerArtist power-reduction breakthrough is but a part of the company’s DAC lineup this year, which includes:
Enabling Design For Power
A range of solutions with a legacy of proven results speed design closure while ensuring accuracy:
● PowerArtist, automatic analysis and reduction
● PowerTheater, unmatched precision at RTL
● CoolProducts, advanced features for power-grid integrity
● Columbus, sets the standard for extraction technology
Sequence will participate in multiple industry events during the show, including:
●Sunday, 1pm, Room 130
CTO Jerry Frenkil at Si2 Workshop Presents “LPC Models for Low Power”
●Tuesday, 3pm, Booth 4359
CTO Jerry Frenkil Presents “Designing for Power”
“DAC is the glue that binds us,” said Vic Kulkarni, Sequence President and CEO. “It’s the only time we’re all together in one big room with the most brilliant minds in high tech, and I’m really looking forward to seeing all of our dear friends and customers in San Francisco.”
EDA, cloud computing experts' free workshop on cluster migration
Design Automation Conference 2009, LISLE, USA: A team of industry leaders in EDA and high performance computing (HPC) in the cloud will be hosting a free workshop in San Francisco, CA coincident with the Design Automation Conference to provide expert training and best practices for users of HPC clusters.
Experts from Sun Microsystems, eXludus and Univa UD will lead the lunchtime session, which takes place on July 27 from 12-2pm.
The July 27th Migration Workshop is a free session that provides participants with access to valuable tools and knowledge about upgrading from commercial cluster schedulers such as Platform LSF to a more cost-effective and complete environment.
This workshop includes a detailed discussion of the differences between schedulers, a look at the benefits of core optimization, how to efficiently manage the migration, and how migrating puts organizations in a better position to leverage both private and public cloud computing.
This workshop is the fourth in a series of similar events which have taken place in Tokyo, Japan, Austin, Texas and Santa Clara, CA.
Geared towards Design Engineers, HPC Infrastructure Owners and IT Decision Makers, the topics covered in the workshop include:
Sun Grid Engine Overview and DRM Comparison
* Anatomy of a Migration Project
* Migration Planning
* Key Evaluation Criteria
* Installation, Configuration & Management
* Migrating Users and Applications
Multi-Core Optimization and Demo
Multi-Cluster Management
Building a Private Cloud
Best Practices for Getting Started
“Now more than ever, companies are looking for ways to achieve cost efficiencies while maintaining productivity and performance. In just a few hours, we provide the tools and expertise users need to confidently plan a migration project to a more comprehensive, affordable computing environmentl,” explains Gary Tyreman, vice president and general manager of Infrastructure at Univa UD.
The workshop, which includes lunch, is being held at the W Hotel/San Francisco, 181 3rd Street, directly across the street from the Moscone Center. Participants can register for the workshops at: http://lsf-to-sge-migration-workshop-.eventbrite.com/
Experts from Sun Microsystems, eXludus and Univa UD will lead the lunchtime session, which takes place on July 27 from 12-2pm.
The July 27th Migration Workshop is a free session that provides participants with access to valuable tools and knowledge about upgrading from commercial cluster schedulers such as Platform LSF to a more cost-effective and complete environment.
This workshop includes a detailed discussion of the differences between schedulers, a look at the benefits of core optimization, how to efficiently manage the migration, and how migrating puts organizations in a better position to leverage both private and public cloud computing.
This workshop is the fourth in a series of similar events which have taken place in Tokyo, Japan, Austin, Texas and Santa Clara, CA.
Geared towards Design Engineers, HPC Infrastructure Owners and IT Decision Makers, the topics covered in the workshop include:
Sun Grid Engine Overview and DRM Comparison
* Anatomy of a Migration Project
* Migration Planning
* Key Evaluation Criteria
* Installation, Configuration & Management
* Migrating Users and Applications
Multi-Core Optimization and Demo
Multi-Cluster Management
Building a Private Cloud
Best Practices for Getting Started
“Now more than ever, companies are looking for ways to achieve cost efficiencies while maintaining productivity and performance. In just a few hours, we provide the tools and expertise users need to confidently plan a migration project to a more comprehensive, affordable computing environmentl,” explains Gary Tyreman, vice president and general manager of Infrastructure at Univa UD.
The workshop, which includes lunch, is being held at the W Hotel/San Francisco, 181 3rd Street, directly across the street from the Moscone Center. Participants can register for the workshops at: http://lsf-to-sge-migration-workshop-.eventbrite.com/
Subscribe to:
Posts (Atom)
