ChipStart offers subsystem alternative for SoC system management

PALO ALTO, USA: ChipStart LLC, a semiconductor intellectual property solution company, announced today the availability of a new SoC intellectual property hardware and software combination, called SSM, which consolidates power, security, error recovery, and boot management by using an SoC subsystem approach.

SSM allows developers to add virtualization to their SoC architectures by replacing tightly coupled solutions typically engineered in house with a decoupling alternative.

Semico Research estimates that over 50 IP cores are present on average in SoCs being developed today. As a result, more SoCs contain distributed computing, multicore architectures. These topologies are making it increasingly difficult to manage power, security, error recovery and even boot sequencing.

No one IP core can easily be given enough accessibility and control to manage the other cores without complicating the architecture. And with many software operating systems and applications on the single SoC, synchronizing their states with their support hardware is also becoming complex.

Solutions designed in-house often result in adding some combination of extra logic and additional software development to manage the system tasks. These solutions are often designed and tested specifically for the SoC configuration.

As complexities grow, significant cost and verification risks are now escalating from the need to redesign and re-verify these solutions for each new chip development project.

SSM represents a unique “subsystem” alternative which decouples the system management from the specific design, promoting high reuse and faster hardware-software integration. SSM creates virtualization in the SoC architecture.

Hardware level virtualization comes from SSM’s ability to operate as a self contained unit independent from the other SoC components. SSM connects to the other IP cores using a simple hardware bus scheme. SSM utilizes commands sent to it by any source to execute the necessary signal level transitions that change an IP cores’ operation state.

Software virtualization comes from SSM's ability to synchronize software and hardware states as it is performing the hardware level tasks. SSM provides API’s and a kernel which is hosted on SSM's hardware core. Drivers are connected to other software on the SoC, which communicates the status of the hardware state changes. SSM can also take command directives directly from the software through the drivers.

Rich Wawryzniak, Senior Analyst, Semico Research, says: “Virtualizing system management using a subsystem approach creates real economies when measuring the development costs for complex SoCs. Since these costs are multiplying from both hardware and software complexity growth, the need for modular SoC architectures that effects both hardware and software development dictates the need for these subsystems.”

SSM uses a unique policy maker-enforcement approach to system management. SSM assumes any other resource on the SoC is a policy maker. SSM takes its commands in the form of a list, which are also called scripts. Scripts are placed into SSM’s local RAM. SSM executes these scripts and communicates its status through a message passing scheme via the hardware bus and through its drivers. By changing the scripts, SSM can manage and change hardware and software states at any time during operation.

SSM scripting eases software and hardware integration, and provides architecture consistency across chips. Says Phil Casini, managing partner for Advance Tech Marketing, and co-developer of SSM, “Scripts make it possible to create pre-designed and pre-verified command sequences that can be mixed and matched for specific SoC instantiations.

This eliminates much of the fixed design and verification costs typically associated with coordinating and managing the system resources. Scripts also marginalize the variable costs because they are reusable from instantiation to instantiation, which eases software integration.”

NEC intros SoC for STBs with extensive multi-format video support

IBC 2009, KAWASAKI, JAPAN, DUESSELDORF, GERMANY & SANTA CLARA, USA: NEC Electronics (TSE: 6723) today announced the availability of a new image-processing solution, the EMMA3SL/P system-on-chip (SoC) based on NEC Electronics’ enhanced multimedia architecture (EMMA) platform.

The EMMA3SL/P SoC is a set-top box (STB) device compliant with H.264 high definition (HD), the next-generation image-compression standard, as well as the multi-format video support used for the increasing number of worldwide internet-protocol television (IP TV) STBs, such as DivX, VC-1, and WMV. The new SoC is also the first among the company’s EMMA products to support China’s audio/video standard (AVS).

The EMMA3SL/P device is an image-processing SoC that integrates key functions needed to receive and decode digital broadcasts, including MPEG-2 HD audio/video decoders, transport-stream demultiplexers, as well as display controllers for enhanced display and graphics features.

The new SoC includes these features:
(1) multi-format video support for IP TV STBs, in addition to support for the H.264 HD standard and China’s AVS,
(2) integrated enhanced security features, and
(3) 20 percent reduction in the number of on-board pins compared to the company’s existing products, due to the high level of function integration.

Digital audio/visual (AV) applications are a strategic business focus for NEC Electronics, and the company is actively promoting chips for this market segment.

Having released the world's first digital broadcasting STB SoC in 1998 under the brand name "EMMA," the company has built a formidable range of digital AV SoC devices since then covering three main areas — STBs, digital TVs and DVD recorders.

With these devices, NEC Electronics reached a cumulative total shipment of 100 million as of April 2009. NEC Electronics introduced two EMMA devices in January 2009, the EMMA3SL/LP and EMMA3SL/L SoCs, to the wider H.264 STB market.

Due to specific emerging demand for increased multi-format video especially in Europe, Asia, and Latin America, NEC Electronics announced an expansion of its STB device roadmap with advanced security features and cost efficiency, building on technology gained from previous products.

HKSTP to provide partner companies with PowerPC core IP

HONG KONG: Hong Kong Science and Technology Parks Corp. (HKSTP) recently signed an agreement with IBM to make IBM’s PowerPC system-on-chip (SoC) intellectual property (IP) available through HKSTP’s new Secure Virtual IP Chamber.

The IP agreement will enable HKSTP’s partner companies and clients all over the world to use IBM’s advanced technology to design prototype products with PowerPC cores in a secure environment that can significantly reduce risk and improve time-to-market at competitive cost.

“We are very delighted to expand our relationship with IBM, which first started in 2007, to create value for our partner companies and clients,” says Allen Yeung, Vice President of Business Development and Technology Support of HKSTP. “The milestone agreement reflects the endorsement and confidence of IBM in the strengths of HKSTP’s Secure Virtual IP Chamber enabling IP protection and technology collaboration.”

SoC technology enables smaller, thinner and longer battery life for consumer electronics such as mobile phones and digital cameras. SoC refers to the placing of multiple-function systems on a single silicon chip and has been key to advancements in the semiconductor industry. But integrating SoC involves time consuming development of in-house IP as well as acquiring IP license from external developers.

The process of integration thus requires substantial IP collaborations. Such collaboration in the past was not that forthcoming due to trust issues between IP suppliers and IC design companies.

With the launch of the Secure Virtual IP Chamber by HKSTP today, the previous issues become irrelevant with HKSTP servicing both companies as the neutral third party in a trusted environment certified by ISO27001:2005 Information Security Management System.

The Chamber provides HKSTP’s partner companies and global clients with secure online access to a wide array of powerful resources including software, IP, information and materials in circuit and systems design and product manufacturing.

It also provides IP by leading international suppliers, including ARM, Cadence and Synopsys, in addition to IBM, at as little as a quarter of the original costs in some areas. Electronics companies and industries using IT solutions will be the first to benefit from the agreement.

E. Anthony Tan, Chief Executive of HKSTP, says, “The PowerPC core agreement and the establishment of the Secure Virtual IP Chamber show HKSTP’s commitment not only to IP protection for technology development, but also our dedication to driving Hong Kong forward as a regional hub for technology and innovation.”

“HKSTP will continue to form strong alliances with key technology vendors like IBM and provide services such as the Secure Virtual IP Chamber to help companies innovate and create value,” he added.

“IBM is expanding its Power Architecture, the most scalable architecture in the world, in collaboration with a number of companies that can add unique value to that architecture," said Bernard Meyerson, IBM, Vice President of Strategic Alliances.

“Working with HKSTP as a trusted IP partner, we are providing our customers with greater value by giving them the option to evaluate, design, and use IP in a well-protected environment while enabling them to achieve cost and time-to-market goals.”

Power Architecture is one of the world’s key embedded CPU architectures and a dominant player in routers, networking equipment, 3G base stations, storage, automotive, multimedia gaming and Digital/Interactive TV.

In a further expansion of IBM’s efforts to provide this technology to universities, the company is now providing HKSTP-designated users with commercial cores (IBM 405 and 460 cores) with SoC. The Secure Virtual IP Chamber service facilitates access to services that help keep the cost for designing prototypes low.

The new agreement builds on the partnership HKSTP and IBM put in place in 2007 to promote semiconductor foundry services in the Asia Pacific region by leveraging IBM’s leading semiconductor technology.

Arteris P-NoC to address SoC peripheral interconnect requirements

SAN JOSE, USA: Arteris Inc., a leading network-on-chip (NoC) SoC interconnect solutions provider, announced the availability of the P-NoC™ peripheral interconnect solution. This provides an efficient way to integrate peripheral components into a SoC.

The P-NoC interconnect product is optimized for connectivity of peripheral IP cores such as timers, USB, infrared interfaces, control communications, audio, touch screen, and other functions. It can also be used to communicate to the programming interfaces of all IP cores in an SoC.

The Arteris P-NoC solution is optimized specifically to address the challenge of integrating peripherals in high-traffic SoCs while using minimal number of wires and gates.

Typically, in a design with multiple peripheral functions, designers must deal with the problem of having only a few data traffic initiators communicating with many data traffic targets. The Arteris P-NoC is scalable from a few to several hundred peripherals while conserving power, reducing gates needed for peripheral communications and minimizing the number of global wires.

The Arteris P-NoC is supported by a full suite of Arteris NoC generation and verification tools for accelerated design turnaround. Arteris NoCcompiler, allows rapid configuration of the peripheral interconnect and generation of Verilog, VHDL and SystemC representations. Arteris NoCverifier supports automated verification of the peripheral interconnect.

“Today'’s complex SoCs require a wide variety and breadth of functionality, and even the simplest of functions must be seamlessly integrated with the on-chip network. Arteris P-NoC saves SoC engineering time by offering a high performance, yet low cost, peripheral interconnect solution.

“It is supported by a silicon-proven NoC Element IP library and a full suite of design and verification tools that is fully compatible with industry standard IP interfaces,” said K. Charles Janac, President and CEO of Arteris.

“Together with the Arteris NoC Solution, the Arteris P-NoC allows our suite of capabilities to address all requirements for SoC interconnect including, top level interconnect, block level interconnect, peripheral interconnect and interchip links.”

The Arteris P-NoC is available for immediate delivery.

Azuro's low-power CTS for complex SoC designs

Design Automation Conference 2009, SANTA CLARA, USA: Azuro Inc., a provider of advanced implementation tools for nanometer chip design, has announced version 5 of its PowerCentric low-power clock tree synthesis (CTS) solution with extended support for complex system-on-chip (SoC) designs.

“Azuro’s proprietary global approaches to clock tree balancing and patented clock gate optimization algorithms are ideally suited to complex SoC designs,” said Paul Cunningham, CEO and co-founder of Azuro.

“PowerCentric is being actively used to tape out many of the world’s most complex chips with hundreds of intertwined clocks and dozens of voltage islands. This latest software release strengthens our proven leadership position in CTS and reinforces Azuro’s continued commitment to deliver lowest clock power, best clock gate timing, and fastest CTS turnaround time.”

Key features in PowerCentric version 5 include:

* 30 percent reduction in CTS runtimes on designs with multiple modes and corners.
* Enhanced clock gate optimization and clock tree buffering algorithms delivering up to 10 percent additional clock power savings.
* Comprehensive support for UPF 2.0 (IEEE 1801) power domain configuration format.
* Ground breaking new “Trial CTS” capability delivering accurate post-CTS design timing with runtimes of less than one hour per one million placeable instances.
* Top level clock balancing through hardened sub-chips with back-annotated parasitics.
* Full database save with rapid restore.

PowerCentric version 5 is available now with UPF 2.0 support in limited availability.

Semico releases two reports on ASIC design starts

PHOENIX, USA: Semico Research Corp. has just released two reports that provide both an historical analysis and forecasts the future of ASIC design starts.

The current global economic slowdown is having an adverse impact on design starts for ASICs. The slowing of design start activity began at the end of 2008 and is continuing through 2009. Semico believes design activity will recover back to more historical norms in 2010.

The “ASIC Design Starts: Changes in Industry Dynamics” report provides an in-depth perspective by showing a comparison between design starts for SoCs and all other types of ASICs.

This report also examines the continuing increase in SoC design costs. ASIC design starts data show changes in design for each device type including analog, mixed signal, gate array, PLD, FPGA, performance SoC, value SoC and structured ASIC.

The design starts data is further segmented by: product type, process geometry, gate count and geographic region. This report contains a wealth of data in 55 tables and 58 figures/graphs.

The “ASIC Design Starts: By Key Applications Revisited II” report segments the data by 66 of the key end applications that drive the design starts market within the computing, communications, consumer, transportation and industrial segments. Within each end application, the data is further segmented by: Analog, Mixed Signal, Performance and Value SoC, PLD, FPGA, Gate Array and Structured ASIC. This report contains an enormous amount of data in 134 tables and 69 figures/graphs.



Both reports complement each other. For each segment, they include design starts and the ASIC unit volumes associated with those design starts. While they use the same worldwide design starts information, each report analyzes the data from a different perspective.

Verigy celebrates 10th anniversary of V93000 SoC test platform

SEMICON West 2009, SAN FRANCISCO, USA: Verigy, a premier semiconductor test company, marked the 10th anniversary of its breakthrough V93000 system-on-chip (SOC) test platform.

Since its introduction, nearly 2,000 V93000 platforms have been installed at the world’s leading foundries, outsource assembly and test (OSAT) providers, fabless semiconductor companies and integrated device manufacturers (IDMs).

“Ten years ago, the V93000 was unveiled at SEMICON/West so it’s very fitting to celebrate here with the industry that has come to rely on this platform,” said Hans-Juergen Wagner, Vice President of SOC Test, Verigy.

“With its unique architecture and evolving set of performance capabilities, the V93000 platform has stood the test of time and continues to deliver best-in-class quality of results and lowest overall cost-of-test for our customers.”

The first V93000 platform, purchased in 1999 by STMicroelectronics, one of the world’s leading semiconductor manufacturers, is still in use on the company’s test floor. “Verigy shares our commitment to delivering the highest quality solutions to our customers,” said Riccardo Ferrari, General Manager of the Communications Infrastructure Division, STMicroelectronics. “The V93000 continues to play a pivotal role in our overall production process as we deliver the leading-edge products our customers count on.”

Virage Logic expands India presence with broad IP portfolio, CorelEL as sales rep

FREMONT, USA: Virage Logic Corp. has expanded its presence in India with the appointment of CoreEL as its sales representative. CoreEL joins a growing global network of sales representatives that complement and expand the reach of Virage Logic’s direct sales channel.

CoreEL’s more than 15 years experience working with India’s networking, telecom, computing, consumer, industrial, defense and automotive customers make them ideally suited to represent Virage Logic’s broad portfolio of silicon proven IP.

“As the semiconductor industry continues to globalize and more semiconductor companies rely on their India-based teams to make SoC design project decisions, the time was right to bring CoreEL on board to service our growing India customer base,” noted Jai Iyer, Virage Logic’s vice president of Asia sales.

“We are confident that the combination of CoreEL’s strong technology and design services experience will enable them to provide the superior sales and support services Virage Logic’s customers worldwide have come to expect.”

“India is rich in engineering talent and a target for companies worldwide to tap into the engineering resources,” said Vishwanath Padur, vice president of Sales and Marketing for CoreEL.

“With Virage Logic’s highly differentiated IP offering -– including embedded SRAMs, embedded NVMs, embedded memory test and repair, logic libraries, memory development software, and interface IP solutions -– we look forward to being able to provide even greater value to our extensive customer base as we help them address their SoC design challenges.”

Conexant's semiconductor solution for connected photo frame segment

NEWPORT BEACH, USA: Conexant Systems Inc., a leading supplier of innovative semiconductor solutions for imaging, audio, video and Internet connectivity applications, announced the first in a planned series of new system-on-chip (SoC) solutions targeted at the growing market for “connected” digital photo frames and interactive display appliances (IDAs).

These products integrate Internet connectivity and touch-screen technology. The high-performance CX92735 supports advanced features including streaming media content, MP3 audio playback with slideshow functionality, and Wi-Fi, Bluetooth, and Ethernet connectivity.

“Conexant is a leading provider of solutions for multifunction printers and facsimile applications, and we have applied our proficiency in imaging technologies to deliver a new system-on-chip that allows us to expand into the growing, adjacent connected photo frame segment,” said Christian Scherp, president of Conexant.

“We have extensive expertise in analog and mixed-signal design, firmware and software development, and in-depth applications knowledge. We will continue to leverage these strengths to capitalize on growth opportunities in the areas we address, and provide our customers with innovative solutions that contribute to their success.”

Connected frames and IDAs are offered in a wide variety of form-factors including speakerphones, VoIP phones, and digital photo frames. They can be used in a broad range of video, audio, telephony, and digital signage applications.

For example, connected frames can be used within the home to send or receive text messages, make hands-free VoIP phone calls, and access and view information such as news, recipes, weather, and traffic reports from the Internet.

Additional applications include interactive kiosks, point-of-sale terminals, baby monitors, and home automation, security, and monitoring systems. In addition, wireless operators are beginning to allow subscribers to use connected frames to receive data over the cellular network.

X-FAB releases first 0.18 micrometer foundry solution for integrated hall sensors

ERFURT, GERMANY: X-FAB Silicon Foundries, a leading analog/mixed-signal foundry and expert in “More than Moore” technologies, announced the industry’s first foundry process for the production of integrated Hall sensor ICs in 0.18 micrometer technology.

Its 0.18 micrometer low-power CMOS process, known as XH018, allows the combination of Hall sensor elements with high-voltage devices and non-volatile memory (NVM) options. This capability augments the industry-leading analog/mixed-signal capabilities inherent in the XH018 process, enabling cost-effective and energy-efficient System-on-Chip (SoC) solutions.

X-FAB’s customers gain the many advantages that Hall effect sensors have over traditional mechanical and reed discrete devices. Silicon-based contactless implementation of Hall sensors improves reliability and durability by virtually eliminating mechanical wear. These sensors enable high-precision measurement and analysis of magnetic fields.

X-FAB’s 0.18 micrometer foundry technology for Hall sensors enables the sensing element to be integrated on the same chip as its control logic and interface circuitry. Due to its small geometry resulting in high integration density, high magnetic sensitivity can be achieved with minimal parasitic effects. On a test chip with a sensor size of 50 by 50 square micrometers, X-FAB has proven a magnetic sensitivity of up to 360 V/(A*T) with high linearity.

Hall sensor technology has been replacing conventional sensing techniques in many applications. X-FAB’s Hall sensor foundry offering is ideal for a variety of applications including magnetic field measurements, position control, speed detection, contactless switches as well as position and angle sensors.

System costs for such applications can be substantially lowered with X-FAB’s integrated approach due to lower part count, simpler assembly, and higher reliability.

X-FAB’s XH018 technology for integrated Hall sensor solutions is available today. It comes with comprehensive design support including characterization data and layout examples.

Xilinx, BEEcube next-gen FPGA-based multi-core SoC development platform for Sun OpenSPARC

SAN JOSE, USA & BEIJING, CHINA: Xilinx Inc. and BEEcube Inc. will jointly unveil a high-performance development environment for multi-core UltraSPARC CMT (chip multi-threaded) processors that reduces the time and effort required to design systems using the SPARC architecture.

The companies demonstrated the development system for the first time at the grand opening of an Advanced Research & Teaching Facility for Embedded System Design in Beijing, a joint venture between Beijing University of Technology (BJUT), the Chinese Ministry of Education (MOE) and Xilinx University Program (XUP).

The BEEcube SoC development platform is built upon BEEcube's third-generation, large-scale multi-core processor BEE3(TM) emulator and takes full advantage of the performance and flexibility of Xilinx' flagship Virtex-5 FPGAs.

The platform enables researchers and hardware architects to quickly experiment with large scale, multi-core, multi-threaded FPGA implementations of UltraSPARC CMT processors for a broad set of end-markets including computing, industrial, scientific, medical, aerospace and defense, storage and networking.

Sun Microsystems' UltraSPARC T1 and UltraSPARC T2 microprocessors are the first 64-bit microprocessors available as an open source design and are freely available from the OpenSPARC website, http://www.beecube.com/opensparc.

"The newest emulation technology from BEEcube, powered by high performance Virtex-5 FPGAs, delivers a development platform that will be a great asset to designers who wish to evaluate the capabilities of the SPARC CMT architecture in a programmable device," said Patrick Lysaght, senior director for the Xilinx University Program and Xilinx Research Labs. "We're pleased that Xilinx technology is playing an important role in expanding the ecosystem for this important and popular open source processor core."

"This exciting collaboration between Xilinx, Sun, and BEEcube leverages our history of proven ASIC prototyping methodology from UC Berkeley and BEEcube, and brings it to the new world of multicore SoCs," said Robert Brodersen, professor emeritus at the University of California, Berkeley and chairman of BEEcube. "This new advance enables system architects using the SPARC CMT architecture to rapidly explore design trade-offs for cost/power/performance optimizations."

"The BEE3 hardware platform, based on Xilinx Virtex-5 FPGA technology, significantly expands the reach of Sun's Chip Multithreading SPARC architecture for the OpenSPARC community, which includes academics, researchers, and developers throughout the world," said Shrenik Mehta, senior director for front-end tools and OpenSPARC at Sun Microsystems. "The BEE3 platform provides users the ability to prototype and build significantly larger multi-core designs based on Sun's industry-leading CMT technology."

A single BEE3 module is capable of emulating either a quad-core 16-thread or two dual-core 8-thread UltraSPARC T1 processors, running on a binary-compatible OpenSolaris or Ubuntu Linux operating system.

Each BEE3 module is designed using the latest Virtex-5 FPGAs. Existing users have a migration path from the Virtex-5 OpenSPARC single-FPGA Evaluation Platform to the new BEE3 quad-FPGA scalable computing platform. Altogether, the new BEEcube development system offers researchers and hardware architects six times more FPGA logic capacity, 64 times larger DRAM capacity, and support for PCI Express x8 and 10-Gigabit Ethernet interfaces.

The BEE3-based OpenSPARC FPGA development platform is immediately available through BEEcube.

SafeNet unveils highest security SoCs, next generation of security co-processors

BALTIMORE, USA: SafeNet Inc., a leader in information security now affiliated with Aladdin Knowledge, announced the availability of the SafeXcel-1742 and SafeXcel-1746, the next generation of the company’s proven security co-processors, and the SafeXcel-3120 and SafeXcel-3141 high-performance system on a chip (SoC) processors.

Each family of chips provides customers with flexible price and performance options when selecting a security solution for accelerating IPsec, SSL/TLS/DTLS, SRTP, MACsec, and Public Key operations.

“SafeNet provides the industry’s broadest portfolio of embedded security solutions to address the needs of various customers across the spectrum of chip and system designs,” said Bob Wheeler, senior analyst, The Linley Group. “This latest addition of security co-processors and SoCs to SafeNet’s solutions portfolio provides customers with flexible options for building the highest level of security into a wide range of feature-rich networking and communications products.”

The SafeXcel family of security co-processors is competitively priced and is intended to offer customers a cost-effective, high-performance solution for building security into gateway appliances, firewalls, modems, office automation equipment, and telecommunications equipment. The SafeXcel-1742 and SafeXcel-1746 co-processors save networking and telecom device and equipment manufacturers design and engineering costs, and reduce overall time to market.

The SafeXcel-1742 and SafeXcel-1746 security co-processors allow host processors to offload packet processing and crypto computations, providing acceleration of IPsec, TLS/SSL/DTLS, SRTP, and MACsec security protocol functions, as well as acceleration of the latest cipher and hash cryptographic algorithms, including Suite B. SafeXcel-1746 contains the highest performance PKA in its class and meets requirements for very high session setup rates.

“At SafeNet, we recognize that the needs of every customer are unique, and the design of every chip, every handset, and every piece of equipment has unique requirements. This is why we are committed to the design, development, and delivery of the industry’s most diverse portfolio of embedded security solutions aimed to provide customers with the best price/performance ratio possible,” said Simon Blake-Wilson, managing director, embedded security solutions, SafeNet. “With the expansion of our chip portfolio to include the cost-sensitive SafeXcel-17xx designs, and the high-performance SafeXcel-31xx SoC designs, we continue to lead the industry in terms of performance and security.”

The SafeNet SafeXcel-3141 and SafeXcel-3120 are highly integrated, high-speed network security SoCs, designed to optimize overall system performance, while reducing cost and shortening time to market for networking, storage, telecom, and defense manufacturers. The security certification capabilities for SafeXcel-3120 and SafeXcel-3141 are FIPS 140-2 Level 3 compliant.

The SafeNet SafeXcel-3141 is a highly integrated, multi-gigabit network security SoC designed to accelerate applications such as IPsec and SSL/TLS. Platform security is ensured through the utilization of trusted code running on the device’s dedicated ARM core. This feature along with a comprehensive tamper detection-and-response system makes the device well-suited for applications that require a high level of intrinsic security.

SafeNet SafeXcel-3120 is a highly integrated device designed for modest performance and high security, where power and cost-sensitivity are a priority at the network edge. The SafeXcel-3120 contains all the same trusted platform features as the 3141, with the addition of red and black data separation.

The embedded ARM processor, via a digital signature, will allow customer-specific application code to execute, enabling the device to be the central processor in the system for security and general applications. Data path is driven by classification engines within the SoC for true in-line and look-aside security processing for both protocol transforms and key management.

SafeNet SafeXcel customers can also significantly reduce time to market by licensing SafeNet’s proven QuickSec IPsec and MACsec software. The QuickSec software seamlessly interfaces with any SafeXcel security co-processor, and can be used on many types of host processors and operating systems. The QuickSec software toolkit can also leverage SafeXcel co-processors for accelerating IPsec packet processing and IKE authentication.

Embedded Security Solutions for OEMs

SafeNet SafeXcel processors are the most cost-effective line of high-speed security processors and co-processors on the market today. Fully integrated with SafeNet’s QuickSec VPN security software, SafeXcel processors provide the market's only complete hardware/software security solution for networking and communications OEMs—delivering superior protection while reducing cost and time to market. SafeNet’s award-winning embedded security solutions are deployed by leading global telecommunications, networking, and semiconductor vendors who trust SafeNet’s best-in-class security solutions for their next-generation networking products. SafeNet OEM customers include Nokia, Ericsson, NEC, AMCC, AMD, Azaire Networks, Cisco, Hitachi, HP, Juniper Networks, PMC-Sierra, Alcatel-Lucent, Nortel, Siemens, Samsung, and Texas Instruments.

OCP-IP releases OCP 3.0 specification

BEAVERTON, USA: Open Core Protocol International Partnership (OCP-IP) has released the OCP 3.0 specification for member review. This latest version contains extensions to support cache coherence and more aggressive power management, as well as an additional high-speed consensus profile and other new elements.

Embedded processors commonly used in SoCs often use local caches to improve performance and reduce power by storing frequently referenced storage locations in high bandwidth low latency local memories. Keeping such caches coherent with the external memories that they shadow requires either careful software engineering or costly hardware resources that have been considered too expensive for most SoCs.

However, maintaining coherence in embedded software is becoming very complex so the OCP 3.0 coherence extensions are included to enable hardware-based coherence among the wide variety of heterogeneous CPUs, DSPs, accelerators and streaming input/output devices that characterize advanced SoCs.

The OCP extensions differ from traditional coherence approaches by cleanly separating the primitive operations associated with maintaining coherence from the specific system-level approach for implementing the communication and storage aspects of a coherent system. This extends a key advantage of OCP -– the ability to develop IP cores independently from the system in which they will be used –- into the domain of cache coherent systems.

In particular, the OCP coherence extensions have been validated against both invalidate-based snoopy and directory-based coherence schemes.

As power minimization is important in most electronic systems, designers are increasingly implementing power management protocols on chip. OCP 3.0 defines a new connection protocol that allows the power management hardware to disconnect the OCP interface without losing any transaction so the manager may then independently shut off power.

Consensus profiles provide company engineers with standardized configurations of OCP options for specific system use cases, ensuring interoperability. A third profile (Profile 3) has been added in OCP 3.0. Profile 1 is a simple slave profile. Profile 2 is a high-speed profile, and Profile 3 is an advanced high-speed profile needed for high speed CPUs, high-performance video graphics accelerators and DRAMS. A detailed technical article on consensus profiles is available here.

“OCP-IP believes a standard is only proven through real-world implementations and products,” said Ian Mackintosh president and chairman of OCP-IP. “OCP-IP members, companies with world-class SoC design expertise in their own right, have used OCP in numerous SoC designs and have already shipped many hundreds of million of units. OCP 3.0 utilizes the collective experience of these SoC designers and EDA providers and directly addresses their enhancement recommendations with the new specification.”

Work on OCP 3.0 was executed by members of the OCP-IP Specification Working Group including: MIPS Technologies, Nokia, Sonics Inc, Texas Instruments, Toshiba and other industry leading companies.

Frontier Silicon selects mixed-signal IP from S3

Silicon & Software Systems Ltd. (S3), a world leading provider of mixed-signal semiconductor IP solutions, announced that Frontier Silicon has licensed its mixed-signal IP for its Chorus 3 SoC. S3 delivered a high performance PLL from its portfolio as part of the deal.

Frontier Silicon is a leading supplier of innovative semiconductor, module and software solutions for digital radio and connected audio systems and this advanced digital radio and audio baseband network processor SoC is now widely available to the market.

"S3 achieved first-time-right silicon and helped us to rapidly enter the market with our Chorus 3 SoC. The low jitter performance of this PLL means that we can offer a superior product that will help drive the successful migration to DAB digital radio across Europe and Australia. The key advantages of working with S3 are first-time-right silicon, best-in-class performance, on-time delivery and excellent integration support. Our partnership with S3 has enabled us to develop the most optimum SoC solution for DAB," said Bob Heads, VP Engineering, at Frontier Silicon.

Commenting on S3's success at Frontier Silicon, Mike Murray, General Manager for Mixed Signal IP at S3, said: "Frontier Silicon is developing innovative solutions on advanced process nodes and we are very pleased to have enabled them to get to market quickly with their DAB product, through the rapid and successful deployment of our leading edge mixed-signal IP. We look forward to extending our working relationship further for their next SoC developments."

What can the global semicon industry do to get back its money-making touch!

It is very well known that the global semiconductor industry has had a year full of turmoil. The ongoing global financial has been not been of any help either.

The key question: Has the semiconductor industry really lost its money making touch?

According to iSuppli, facing dwindling profits, fewer opportunities to expand by taking market share from competitors and a shrinking roster of star performers, the semiconductor industry has entered a period of lowered expectations and diminishing options, forcing chip suppliers to rethink their basic strategies for success.

Thanks to Jon Cassell at iSuppli, I caught up with Derek Lidow, president and CEO, of iSuppli, to find out more about why the global semiconductor industry has become less forgiving. He has offered a range of suggestions for the global semiconductor industry to adopt and follow. The beauty of the advice lies in its simplicity, and I hope the industry is reading!

Facing dwindling profits and fewer opportunities to expand by taking market share from competitors and a shrinking roster of star performer, how difficult is the market today?

According to Derek Lidow, at the moment, the makers of electronics have started slamming on the brakes as they have decided that the financial turmoil will effect Christmas spending.

In this scenario, what strategies should the players: a) fabs; b) NAND; c) DRAM; d) materials devise, to ensure some turnaround?

Lidow says that the fab players should consolidate fabs to make them more efficient.

Both the NAND players and DRAM players should push out capacity expansion plans. Makers of devices should make variations of the existing products that customer would like to have, and don't turn down opportunities to lock in orders for specials.

If semiconductors have actually lost their money-making touch, it is really an alarming sign. However, Lidow advises that the semiconductor business is maturing and every industry, as it matures, must undergo transitions.

Leaders can't ignore looming changes
"Often, these transitions come as a surprise and many companies go through hard times," he says. "Semiconductor companies don't have to go through the turmoil of the steel or automotive industries if it doesn't want to. The leaders of the industry just can't ignore the looming changes."

Is there a way that semiconductor companies break out of the current market dynamics to outperform the industry?

Lidow suggests the semiconductor companies should STOP doing things that they are not good at! He adds: "Each company will have to follow a recipe that eliminates where they are mediocre and focuses on where they add real value. Next, they should change their business models so that semiconductor technology is the tool, not the objective."

According to him, designing more total systems with system-level chips built around proprietary Intellectual Property (IP) should be enough.

He says: "The electronics industry is $1.5 trillion dollars in size, and the semiconductor industry is $270 billion in size. There is a lot more value to capture. However, the value is more complex to unlock and requires as much or more software expertise as it does semiconductor expertise. They have to get married together to succeed in developing proprietary IP."

Areas to outspend rivals
As for the areas where companies can massively outspending rivals in areas of products and manufacturing, these would be leading edge wafer foundries, memory chips, and the most complex system-on-chips (SoCs).

Why won't this massive outspend simply to maintain technical and scale dominances in competitive market segments be risky?

Lidow says you can only use this strategy if you know you can outspend your rival! "We see the problems of a spending race in the memory market where many companies are trying to keep up with Samsung's massive investments and it is hurting everyone," he points out.

iSuppli has also advised adopting a scalable acquisition process that would allow a semiconductor company to grow by buying other companies or selected parts of companies.

Lidow says: "I think the point of my article was that there haven't been any success stories to date. So, this strategy is unproven, but very tantalizing, considering the state of the maturing industry."

EVE betting strong on Indian semicon industry

I have known Montu Makadia, Director and Country Sales Manager, EVE Design Automation Pvt. Ltd, since his days at eInfochips. It was interesting to learn more about the company and its strategy for India over the coming years.

For those who came in late, EVE offers a broad range of hardware-assisted verification solutions on the market, from acceleration to fast emulation and prototyping, with the most cycles per dollar. EVE products lead to a significant shortening of the overall verification cycle of complex integrated circuits and electronic systems design.

EVE products also work in conjunction with popular Verilog and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics. Its sales headquarters in the United States is in San Jose, California. EVE's manufacturing, R&D and corporate headquarters is located in Palaiseau, France.

Estimating the Indian semiconductor industry, Makadia said the global semiconductor market continues to grow, driven by the demand for consumer-oriented electronic devices. The Indian semiconductor industry, in particular, appears quite strong and is an attractive market opportunity for EVE.

"That's because of its push into digital media, telecom and mobile communications markets that presents tremendous growth opportunities for companies such as EVE," he said.

According to him, industry watchers should see strong growth in semiconductors in India in the coming years, propelled by smaller process technologies, multi-core architectures and the ever-increasing software content in system-on-chips (SoCs). With more SoC designs, the demand increases for hardware/software co-verification solutions.

EVE's belief in the Indian market has been so strong that EVE Design Automation Pvt. Ltd., a wholly owned subsidiary based in Bangalore, was formed in 2007. EVE DA markets and supports the Zebu (for 'zero bugs') hardware-assisted verification platforms of accelerators, emulators and FPGA prototypes.

ZeBu enhances SoC performance
So, how exactly does ZeBu help analyze, benchmark and measure performance of the system-on-chip (SoC) over realistic scenarios?

Makadia said: "We have been really successful last year promoting the Zebu based emulation platform. Our existing customers, as well as new prospects in India, have shown great interest and recognized real value in adopting Zebu, not only for hardware verification but also for hardware and software co-verification.

"The Zebu platforms enable software validation and co-verification in a range of several megahertz, thus replacing the deployment of ASIC or prototype boards. For instance, we booted operating systems, e.g., Linux and WinCE, on processors designs mapped into ZeBu emulation platforms at 10-20 megahertz using a transactor-based verification methodology."

How can EVE's ZeBu be the choice of startups who need first-pass silicon success? Makadia added that startups in need of first-pass silicon success and designers worldwide have found that emulation tools such as Zebu are the only option for debugging hardware and testing the integration of hardware and software within complex SoCs.

He noted: "This is especially true when the task calls for executing billions of cycles in less than one hour and there's a need for full visibility into the hardware. The ability to track hardware and software interaction offered by Zebu is considered a plus."

ZeBu helps to analyze benchmark and measure SoC performance with realistic scenarios by running at speeds well above one megahertz. It is capable of executing complete test scenarios within an acceptable timeframe and just shy of running in real time.

This is interesting, and further examination needs to be done to evaluate how the emulation segment is performing and where it is evolving, especially, in India?

Makadia said: "After several years of stagnation, the overall market for emulation has been growing due to escalating complexity in hardware and in embedded software. Other factors have made emulators attractive once again. They run faster, are easier to use, have smaller footprints and are cheaper than older generations."

The growth trend for emulation and hardware/software co-verification solutions will continue in the foreseeable future, especially in India.

Speaking on EVE's overall strategy, he added that the company will continue to introduce even better performing emulation platforms through innovative architectures and enhanced supporting software to increase adoption by all market segments of the electronics industry.

Further, EVE is evaluating strategic partnerships and possible mergers with various synergistic companies to expand the attraction of its offerings.