SUNNYVALE, USA: MIPS Technologies Inc., a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, and Sigma Designs Inc., a leader in digital media processing system-on-chip (SoC) solutions for consumer electronics, announced that they are bringing a full high-definition (HD) experience to the revolutionary Android platform.
At the DIGITIMES Tech Forum Multimedia Day in Taipei on August 27th, the companies will demonstrate an Android-based system displaying 1080p video on a full HD flat screen display.
This HD video demonstration is a major milestone toward the creation of a reference platform for an Android-based set-top box (STB) -- a goal that Sigma and MIPS have been jointly working toward with other members of the STB working group of the Open Embedded Software Foundation (OESF). The goal of the OESF consortium is to drive Android into new consumer electronics segments beyond the mobile handset, where Android is already finding success.
"After showing a Blu-ray reference design for Android in June, we are pleased to now show full HD video on a MIPS-Based platform from Sigma -- a platform that was selected as an official Android reference port for the OESF STB working group," said Ken Lowe, vice president of strategic marketing, Sigma Designs.
"Support for Android is a priority on Sigma's roadmap as we enable our customers to quickly, easily and cost-effectively bring exciting new functionality to their next-generation of connected devices including DTVs, STBs and Blu-ray players."
"We are excited to join with Sigma to announce this latest Android on MIPS milestone and another industry-first," said Art Swift, vice president of marketing at MIPS Technologies.
"Since we announced public availability of the Android on MIPS source code earlier this month, over 600 people have registered to access the code, and we actually had to add server and network capacity in order to meet demand! Together with our ecosystem partners, silicon partners and Early Access Customers, we are making incredible progress in driving Android into devices beyond the mobile handset."
To enable Android to run on an HD screen rather than the small screen of a mobile handset, Sigma and MIPS undertook enhancements to Android libraries and the MIPS architecture.
Sigma Designs extended libraries within Android to support hardware graphics acceleration and hardware decoding to take advantage of their SoC capabilities for HD. MIPS Technologies is also making performance optimizations specifically for the MIPS32 architecture. This optimized code will be available in the future as part of the publicly-available Android on MIPS code.
Showing posts with label MIPS Technologies. Show all posts
Showing posts with label MIPS Technologies. Show all posts
Thursday, August 27, 2009
Tuesday, August 4, 2009
MIPS drives Android into the digital home
SUNNYVALE, USA: MIPS Technologies Inc., a leading provider of industry-standard processor architectures and cores for home entertainment, communications, networking and portable multimedia markets, has met a key milestone in driving the Android platform beyond mobile handsets.
Just two months after announcing its port of the Android platform to the MIPS(r) architecture, the company is making the source code publicly available.
MIPS Technologies also initiated an Early Access Program for a small group of key customers who will have access to specific hardware and code optimizations before they are publicly available. These customers will work closely with MIPS' engineering team, providing critical feedback and market expertise. MIPS Technologies plans to announce initial Early Access customers shortly.
"We are seeing an enormous amount of customer interest in Android on the MIPS architecture," said Art Swift, vice president of marketing, MIPS Technologies.
"Android presents a compelling value proposition in bringing internet connectivity and a broad range of applications to MIPS-based digital home devices. We are working closely with customers and partners to ensure that critical technologies are available for developers to take advantage of Android for consumer electronics."
Together with ecosystem partners, silicon partners and working groups of the Open Embedded Software Foundation (OESF), an organization focused on driving Android beyond mobile handsets, MIPS Technologies is working to define standardized Android-based platforms for consumer devices such as set-top boxes, digital TVs, mobile internet devices (MIDs), home media players and VoIP systems.
Having already demonstrated Android running on a home media player and on a DTV reference design, MIPS and its partners plan to demonstrate more solutions in the coming months.
MIPS Technologies and its partners last week outlined their progress in taking Android beyond mobile handsets during forums in Taiwan and Japan. At the Japan forum -- sponsored by the OESF -- MIPS Technologies' long-time partner D2 Technologies demonstrated its mCUE converged communications client for Android-based devices.
The demonstration showed how embedded software products such as mCUE can enable VoIP, video chat and other IP communications in Android-based embedded equipment and consumer electronics devices.
Just two months after announcing its port of the Android platform to the MIPS(r) architecture, the company is making the source code publicly available.
MIPS Technologies also initiated an Early Access Program for a small group of key customers who will have access to specific hardware and code optimizations before they are publicly available. These customers will work closely with MIPS' engineering team, providing critical feedback and market expertise. MIPS Technologies plans to announce initial Early Access customers shortly.
"We are seeing an enormous amount of customer interest in Android on the MIPS architecture," said Art Swift, vice president of marketing, MIPS Technologies.
"Android presents a compelling value proposition in bringing internet connectivity and a broad range of applications to MIPS-based digital home devices. We are working closely with customers and partners to ensure that critical technologies are available for developers to take advantage of Android for consumer electronics."
Together with ecosystem partners, silicon partners and working groups of the Open Embedded Software Foundation (OESF), an organization focused on driving Android beyond mobile handsets, MIPS Technologies is working to define standardized Android-based platforms for consumer devices such as set-top boxes, digital TVs, mobile internet devices (MIDs), home media players and VoIP systems.
Having already demonstrated Android running on a home media player and on a DTV reference design, MIPS and its partners plan to demonstrate more solutions in the coming months.
MIPS Technologies and its partners last week outlined their progress in taking Android beyond mobile handsets during forums in Taiwan and Japan. At the Japan forum -- sponsored by the OESF -- MIPS Technologies' long-time partner D2 Technologies demonstrated its mCUE converged communications client for Android-based devices.
The demonstration showed how embedded software products such as mCUE can enable VoIP, video chat and other IP communications in Android-based embedded equipment and consumer electronics devices.
Wednesday, July 8, 2009
MIPS, EE Solutions bring MIPS architecture to China and Taiwan semicon firms
SUNNYVALE, USA & HSINCHU CITY, TAIWAN: MIPS Technologies Inc., a leading provider of industry-standard processor architectures and cores for home entertainment, communications, networking and portable multimedia markets, and EE Solutions, a leading provider of ASIC and SoC design solutions, are teaming to provide semiconductor companies in China and Taiwan with easy access to MIPS' industry-standard technology.
EE Solutions licensed the synthesizable MIPS32 24KEc core as part of its digital IP portfolio and will work with MIPS to provide value-added solutions to joint customers.
EE Solutions has developed a hardened 24KEc core in TSMC 65nm process technology, resulting in proven expertise that it can leverage in engagements with customers. With MIPS' high-performance, low-power 24KEc core and design and turnkey services from EE Solutions, customers designing SoCs for multimedia devices such as set-top boxes, DTVs, and digital still cameras can get to market quickly at the lowest possible cost.
"We are pleased to work with MIPS Technologies, the leader in processor IP for many multimedia markets, to provide value to our joint customers across China and Taiwan. Together we can offer solutions that result in high-performance products with smaller die size-leading to reduced development costs. Customers can benefit from MIPS Technologies' industry leading technology and EE Solutions' proven record of providing customers with the ideal solutions to achieve their business objectives," said Jim Su, president, EE Solutions.
"Through this agreement with EE Solutions, a well-respected design services firm for the Greater China market, we are enabling companies across the region to get their differentiated products to market quickly," said Art Swift, vice president of marketing for MIPS Technologies. "EE Solutions' deep experience, engineering excellence and proven track record make them a trusted and important partner for MIPS. This agreement is yet another step in broadening access to the MIPS architecture in Greater China."
MIPS32 24KE family
The MIPS32 24KE core family leverages the high performance 24K microarchitecture while incorporating the MIPS DSP Application Specific Extension (ASE). These instructions provide signal processing performance of up to 3x over a range of embedded applications compared to RISC implementations without the DSP ASE. The 24KE family provides very efficient DSP capability while significantly reducing overall SoC die area, cost and power consumption.
The 24KEc core is a high-performance, low-power, core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor.
EE Solutions licensed the synthesizable MIPS32 24KEc core as part of its digital IP portfolio and will work with MIPS to provide value-added solutions to joint customers.
EE Solutions has developed a hardened 24KEc core in TSMC 65nm process technology, resulting in proven expertise that it can leverage in engagements with customers. With MIPS' high-performance, low-power 24KEc core and design and turnkey services from EE Solutions, customers designing SoCs for multimedia devices such as set-top boxes, DTVs, and digital still cameras can get to market quickly at the lowest possible cost.
"We are pleased to work with MIPS Technologies, the leader in processor IP for many multimedia markets, to provide value to our joint customers across China and Taiwan. Together we can offer solutions that result in high-performance products with smaller die size-leading to reduced development costs. Customers can benefit from MIPS Technologies' industry leading technology and EE Solutions' proven record of providing customers with the ideal solutions to achieve their business objectives," said Jim Su, president, EE Solutions.
"Through this agreement with EE Solutions, a well-respected design services firm for the Greater China market, we are enabling companies across the region to get their differentiated products to market quickly," said Art Swift, vice president of marketing for MIPS Technologies. "EE Solutions' deep experience, engineering excellence and proven track record make them a trusted and important partner for MIPS. This agreement is yet another step in broadening access to the MIPS architecture in Greater China."
MIPS32 24KE family
The MIPS32 24KE core family leverages the high performance 24K microarchitecture while incorporating the MIPS DSP Application Specific Extension (ASE). These instructions provide signal processing performance of up to 3x over a range of embedded applications compared to RISC implementations without the DSP ASE. The 24KE family provides very efficient DSP capability while significantly reducing overall SoC die area, cost and power consumption.
The 24KEc core is a high-performance, low-power, core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor.
Sunday, May 10, 2009
MIPS announces divestiture of Analog Business Group
MOUNTAIN VIEW, USA: MIPS Technologies Inc., a leading provider of industry-standard processor architectures and cores for home entertainment, communications, networking and portable multimedia markets, announced the divestiture of its Analog Business Group.
Synopsys Inc. acquired the business unit in an all-cash transaction for $22 million, effective immediately.
This transaction enables MIPS Technologies to focus exclusively on its core competencies in microprocessor IP, continuing to build on its leadership position in markets like the digital home and networking, while expanding its presence in other key markets. The Analog Business Group was formed through MIPS' acquisition of Chipidea Microelectronica S.A. in August 2007.
"We believe this action will improve shareholder value, increase profitability, boost our competitive position and enable us to focus all of our resources on solving our customers' most immediate design challenges," said John Bourgoin, MIPS Technologies president and CEO. "MIPS has tremendous opportunities in our industry-leading processor IP, development tools and robust ecosystem, and we are laser-focused on growing our business in these areas. Synopsys has a long-term mixed-signal IP business that will be significantly stronger as a result of this deal."
Synopsys Inc. acquired the business unit in an all-cash transaction for $22 million, effective immediately.
This transaction enables MIPS Technologies to focus exclusively on its core competencies in microprocessor IP, continuing to build on its leadership position in markets like the digital home and networking, while expanding its presence in other key markets. The Analog Business Group was formed through MIPS' acquisition of Chipidea Microelectronica S.A. in August 2007.
"We believe this action will improve shareholder value, increase profitability, boost our competitive position and enable us to focus all of our resources on solving our customers' most immediate design challenges," said John Bourgoin, MIPS Technologies president and CEO. "MIPS has tremendous opportunities in our industry-leading processor IP, development tools and robust ecosystem, and we are laser-focused on growing our business in these areas. Synopsys has a long-term mixed-signal IP business that will be significantly stronger as a result of this deal."
Friday, May 8, 2009
Synopsys acquires Analog Business Group of MIPS Technologies
MOUNTAIN VIEW, USA: Synopsys Inc. has acquired the Analog Business Group of MIPS Technologies, Inc. for $22 million in cash. The acquisition expands Synopsys' DesignWare intellectual property (IP) portfolio with a new family of analog IP such as Analog-to-Digital Converters, Digital-to-Analog Converters, Audio Codecs and Power Management. It will also add HDMI TX and RX protocols to Synopsys' existing interface IP solution.
Synopsys has been an established IP provider for more than a decade, providing complete solutions consisting of digital controllers, PHY and Verification IP for widely used protocols such as USB, PCI Express, DDR, SATA and Ethernet.
Synopsys expects the acquisition to benefit designers in a number of ways, including:
* Providing access to an even broader portfolio of high-quality interface and analog IP that supports the latest connectivity standards, process technologies and foundries - all from a single, trusted vendor; and
* Continuing to maintain the quality standards and excellent technical support which customers are accustomed to receiving from Synopsys.
"With this acquisition, Synopsys is well-positioned to provide our customers with a strong interface and analog IP portfolio that is silicon-proven, shipping in volume and unmatched in the industry," said Joachim Kunkel, vice president and general manager of the Solutions Group at Synopsys. "One of the reasons designers turn to Synopsys is because they have trust in the IP and know that we will be there for the long term. With the addition of the new analog IP products and the highly skilled engineering team, our customers will benefit from a broader portfolio of high quality IP, thereby reducing risk and speeding time-to-market."
Synopsys has been an established IP provider for more than a decade, providing complete solutions consisting of digital controllers, PHY and Verification IP for widely used protocols such as USB, PCI Express, DDR, SATA and Ethernet.
Synopsys expects the acquisition to benefit designers in a number of ways, including:
* Providing access to an even broader portfolio of high-quality interface and analog IP that supports the latest connectivity standards, process technologies and foundries - all from a single, trusted vendor; and
* Continuing to maintain the quality standards and excellent technical support which customers are accustomed to receiving from Synopsys.
"With this acquisition, Synopsys is well-positioned to provide our customers with a strong interface and analog IP portfolio that is silicon-proven, shipping in volume and unmatched in the industry," said Joachim Kunkel, vice president and general manager of the Solutions Group at Synopsys. "One of the reasons designers turn to Synopsys is because they have trust in the IP and know that we will be there for the long term. With the addition of the new analog IP products and the highly skilled engineering team, our customers will benefit from a broader portfolio of high quality IP, thereby reducing risk and speeding time-to-market."
OCP-IP releases OCP 3.0 specification
BEAVERTON, USA: Open Core Protocol International Partnership (OCP-IP) has released the OCP 3.0 specification for member review. This latest version contains extensions to support cache coherence and more aggressive power management, as well as an additional high-speed consensus profile and other new elements.
Embedded processors commonly used in SoCs often use local caches to improve performance and reduce power by storing frequently referenced storage locations in high bandwidth low latency local memories. Keeping such caches coherent with the external memories that they shadow requires either careful software engineering or costly hardware resources that have been considered too expensive for most SoCs.
However, maintaining coherence in embedded software is becoming very complex so the OCP 3.0 coherence extensions are included to enable hardware-based coherence among the wide variety of heterogeneous CPUs, DSPs, accelerators and streaming input/output devices that characterize advanced SoCs.
The OCP extensions differ from traditional coherence approaches by cleanly separating the primitive operations associated with maintaining coherence from the specific system-level approach for implementing the communication and storage aspects of a coherent system. This extends a key advantage of OCP -– the ability to develop IP cores independently from the system in which they will be used –- into the domain of cache coherent systems.
In particular, the OCP coherence extensions have been validated against both invalidate-based snoopy and directory-based coherence schemes.
As power minimization is important in most electronic systems, designers are increasingly implementing power management protocols on chip. OCP 3.0 defines a new connection protocol that allows the power management hardware to disconnect the OCP interface without losing any transaction so the manager may then independently shut off power.
Consensus profiles provide company engineers with standardized configurations of OCP options for specific system use cases, ensuring interoperability. A third profile (Profile 3) has been added in OCP 3.0. Profile 1 is a simple slave profile. Profile 2 is a high-speed profile, and Profile 3 is an advanced high-speed profile needed for high speed CPUs, high-performance video graphics accelerators and DRAMS. A detailed technical article on consensus profiles is available here.
“OCP-IP believes a standard is only proven through real-world implementations and products,” said Ian Mackintosh president and chairman of OCP-IP. “OCP-IP members, companies with world-class SoC design expertise in their own right, have used OCP in numerous SoC designs and have already shipped many hundreds of million of units. OCP 3.0 utilizes the collective experience of these SoC designers and EDA providers and directly addresses their enhancement recommendations with the new specification.”
Work on OCP 3.0 was executed by members of the OCP-IP Specification Working Group including: MIPS Technologies, Nokia, Sonics Inc, Texas Instruments, Toshiba and other industry leading companies.
Embedded processors commonly used in SoCs often use local caches to improve performance and reduce power by storing frequently referenced storage locations in high bandwidth low latency local memories. Keeping such caches coherent with the external memories that they shadow requires either careful software engineering or costly hardware resources that have been considered too expensive for most SoCs.
However, maintaining coherence in embedded software is becoming very complex so the OCP 3.0 coherence extensions are included to enable hardware-based coherence among the wide variety of heterogeneous CPUs, DSPs, accelerators and streaming input/output devices that characterize advanced SoCs.
The OCP extensions differ from traditional coherence approaches by cleanly separating the primitive operations associated with maintaining coherence from the specific system-level approach for implementing the communication and storage aspects of a coherent system. This extends a key advantage of OCP -– the ability to develop IP cores independently from the system in which they will be used –- into the domain of cache coherent systems.
In particular, the OCP coherence extensions have been validated against both invalidate-based snoopy and directory-based coherence schemes.
As power minimization is important in most electronic systems, designers are increasingly implementing power management protocols on chip. OCP 3.0 defines a new connection protocol that allows the power management hardware to disconnect the OCP interface without losing any transaction so the manager may then independently shut off power.
Consensus profiles provide company engineers with standardized configurations of OCP options for specific system use cases, ensuring interoperability. A third profile (Profile 3) has been added in OCP 3.0. Profile 1 is a simple slave profile. Profile 2 is a high-speed profile, and Profile 3 is an advanced high-speed profile needed for high speed CPUs, high-performance video graphics accelerators and DRAMS. A detailed technical article on consensus profiles is available here.
“OCP-IP believes a standard is only proven through real-world implementations and products,” said Ian Mackintosh president and chairman of OCP-IP. “OCP-IP members, companies with world-class SoC design expertise in their own right, have used OCP in numerous SoC designs and have already shipped many hundreds of million of units. OCP 3.0 utilizes the collective experience of these SoC designers and EDA providers and directly addresses their enhancement recommendations with the new specification.”
Work on OCP 3.0 was executed by members of the OCP-IP Specification Working Group including: MIPS Technologies, Nokia, Sonics Inc, Texas Instruments, Toshiba and other industry leading companies.
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