FREMONT, USA: Virage Logic Corp. has declared its recommended cash offer to acquire publicly held ARC International plc, a leading provider of consumer IP to OEM and semiconductor companies globally, unconditional in all respects.
With 84.68 percent of the ARC shares already tendered into the offer, Virage Logic will proceed to consummate the purchase of this ownership interest in ARC and will have ARC immediately apply to the UK Listing Authority and the London Stock Exchange for the delisting of ARC’s shares.
This all-cash transaction values ARC at 16.25 pence per share, or an equity value of approximately £25.2 million (approximately $42.0 million) on a fully-diluted basis.
“Although we are declaring the offer unconditional at this point, our objective is to reach 100 percent acceptance. To date we have acquired approximately 84.68 percent of the issued share capital of ARC and continue to pursue acceptances of the offer,” said J. Daniel McCranie, Virage Logic’s executive chairman.
“This acquisition significantly expands our market opportunity to include microprocessor cores and further underscores our vision of establishing Virage Logic as a broad-line supplier of highly differentiated semiconductor IP.”
Transaction details
On August 18, 2009, Virage Logic made a recommended cash offer of 16.25 pence per share for ARC’s issued share capital. The offer is being conducted under the rules of the U.K. City Code on Takeovers and Mergers.
The purchase of ARC’s shares in the offer will be funded out of Virage Logic’s existing cash resources. At the time it commenced the Offer, Virage Logic had received irrevocable undertakings from ARC shareholders representing, in aggregate, approximately 56 percent of ARC’s issued share capital. All of these shareholders have now tendered their acceptance of the Offer.
Now that Virage Logic has acquired 84.68 percent of ARC’s outstanding shares, immediate application will be made to the UK Listing Authority for the cancellation of listing of the ARC shares on the Official List and to the London Stock Exchange for cancellation of admission to trading of the ARC shares on its market for listed securities, in each case to take effect on, or shortly after, October 14, 2009, which is 20 business days following the date of this announcement.
Virage Logic also intends to apply for the re-registration of ARC as a private limited company under the relevant provisions of the Companies Act 2006.
Furthermore, if it receives sufficient valid acceptances of the offer (being not less than 90 percent of the ARC shares), Virage Logic intends to exercise its rights under Chapter 3 of Part 28 of the Companies Act 2006 to acquire compulsorily the remaining ARC shares on the same terms as the offer.
Cowen and Company, LLC and Arbuthnot Securities Limited are acting as joint financial advisors to Virage Logic. Jefferies International Limited and Woodside Capital Partners are acting as joint financial advisors to ARC.
Showing posts with label Virage Logic. Show all posts
Showing posts with label Virage Logic. Show all posts
Wednesday, September 16, 2009
Wednesday, August 19, 2009
Virage Logic announces intent to acquire ARC International
FREMONT, USA: Virage Logic Corp. announced its intent to acquire publicly held ARC International plc, a leading provider of consumer IP to OEMs and semiconductor companies globally.
The proposed acquisition would expand Virage Logic's ability to serve the global semiconductor market by complementing its existing portfolio of physical IP and standards-based advanced interface IP with ARC's widely accepted processor IP, a necessary component for complex SoC ICs.
The proposed all-cash transaction values ARC at 16.25 pence per share, or an equity value of approximately £25.2 million ($41.0 million) on a fully-diluted basis. The Directors of ARC have recommended unanimously that ARC's shareholders accept the offer.
Virage Logic expects that the offer document will be mailed to ARC shareholders shortly. The offer period will extend for a minimum of 21 days from the date the offer document has been mailed, and the transaction is expected to close by the end of Virage Logic's first fiscal quarter of 2010, which ends on December 31, 2009.
The offer is subject to certain limited closing conditions, including that at least 90 percent of the ARC shares have been tendered into the offer.
"The acquisition of ARC would represent another significant milestone in the execution of our vision of establishing Virage Logic as a broad-line supplier of highly differentiated semiconductor IP to our global IDM, foundry and fabless customers. Through both our organic and inorganic growth initiatives, we have significantly expanded our portfolio of standard products," said Dan McCranie, Virage Logic's executive chairman.
"With approximately $24 million in revenue for the trailing 12 months ended June 30, 2009 and over 150 customers, ARC would contribute meaningful scale to our business. Furthermore, ARC would significantly expand our market opportunity to include microprocessor cores, the largest segment of the semiconductor IP market."
"In our engagements with well over 300 existing worldwide customers, we have seen the need to provide additional IP building blocks to enable successful and timely development of large SoC products," said Dr. Alex Shubat, president and CEO of Virage Logic.
"Our highly differentiated product portfolio comprising memory compilers, logic libraries, non-volatile memory, test and repair solutions, and high speed interfaces have set the standard for superior quality and value added features for a variety of end applications. By bringing ARC's talented team into our company, we will be complementing our existing technological and operational nucleus to provide even more comprehensive product solutions for our customers."
"ARC has established a leading position in the provision of customizable Solution-to-Silicon IP to consumer and semiconductor companies globally. The company has been rationalized and strengthened under its new leadership, and with its market-leading technology and outstanding worldwide customer base, ARC is well positioned for a successful future," said Richard Barfield, Chairman of ARC.
"As Virage Logic has recognized, the combination of the technology, expertise and customer bases of ARC and Virage Logic will create substantial opportunities for the Enlarged Group and its customers. In addition, the ARC Directors believe that the Offer delivers value and certainty to ARC Shareholders. Consequently, the ARC Directors are able to recommend the Offer unanimously to ARC Shareholders."
On a non-GAAP basis, which excludes the effects of FAS123R stock compensation expense, restructuring, and amortization of intangible assets and acquisition related charges, Virage Logic expects the proposed acquisition to be accretive between $0.10 and $0.14 earnings per share to fiscal year 2010. Immediately following the closing of the acquisition, Virage Logic expects to have a cash balance of approximately $20-$23 million.
Cowen and Company, LLC and Arbuthnot Securities Limited are acting as joint financial advisors to Virage Logic. Jefferies International Limited and Woodside Capital Partners are acting as joint financial advisors to ARC.
The proposed acquisition would expand Virage Logic's ability to serve the global semiconductor market by complementing its existing portfolio of physical IP and standards-based advanced interface IP with ARC's widely accepted processor IP, a necessary component for complex SoC ICs.
The proposed all-cash transaction values ARC at 16.25 pence per share, or an equity value of approximately £25.2 million ($41.0 million) on a fully-diluted basis. The Directors of ARC have recommended unanimously that ARC's shareholders accept the offer.
Virage Logic expects that the offer document will be mailed to ARC shareholders shortly. The offer period will extend for a minimum of 21 days from the date the offer document has been mailed, and the transaction is expected to close by the end of Virage Logic's first fiscal quarter of 2010, which ends on December 31, 2009.
The offer is subject to certain limited closing conditions, including that at least 90 percent of the ARC shares have been tendered into the offer.
"The acquisition of ARC would represent another significant milestone in the execution of our vision of establishing Virage Logic as a broad-line supplier of highly differentiated semiconductor IP to our global IDM, foundry and fabless customers. Through both our organic and inorganic growth initiatives, we have significantly expanded our portfolio of standard products," said Dan McCranie, Virage Logic's executive chairman.
"With approximately $24 million in revenue for the trailing 12 months ended June 30, 2009 and over 150 customers, ARC would contribute meaningful scale to our business. Furthermore, ARC would significantly expand our market opportunity to include microprocessor cores, the largest segment of the semiconductor IP market."
"In our engagements with well over 300 existing worldwide customers, we have seen the need to provide additional IP building blocks to enable successful and timely development of large SoC products," said Dr. Alex Shubat, president and CEO of Virage Logic.
"Our highly differentiated product portfolio comprising memory compilers, logic libraries, non-volatile memory, test and repair solutions, and high speed interfaces have set the standard for superior quality and value added features for a variety of end applications. By bringing ARC's talented team into our company, we will be complementing our existing technological and operational nucleus to provide even more comprehensive product solutions for our customers."
"ARC has established a leading position in the provision of customizable Solution-to-Silicon IP to consumer and semiconductor companies globally. The company has been rationalized and strengthened under its new leadership, and with its market-leading technology and outstanding worldwide customer base, ARC is well positioned for a successful future," said Richard Barfield, Chairman of ARC.
"As Virage Logic has recognized, the combination of the technology, expertise and customer bases of ARC and Virage Logic will create substantial opportunities for the Enlarged Group and its customers. In addition, the ARC Directors believe that the Offer delivers value and certainty to ARC Shareholders. Consequently, the ARC Directors are able to recommend the Offer unanimously to ARC Shareholders."
On a non-GAAP basis, which excludes the effects of FAS123R stock compensation expense, restructuring, and amortization of intangible assets and acquisition related charges, Virage Logic expects the proposed acquisition to be accretive between $0.10 and $0.14 earnings per share to fiscal year 2010. Immediately following the closing of the acquisition, Virage Logic expects to have a cash balance of approximately $20-$23 million.
Cowen and Company, LLC and Arbuthnot Securities Limited are acting as joint financial advisors to Virage Logic. Jefferies International Limited and Woodside Capital Partners are acting as joint financial advisors to ARC.
Wednesday, July 29, 2009
Virage Logic intros SiPro PCI Express PHY IP
SAN FRANCISCO, USA: Virage Logic Corp. has announced its new offering, a silicon and volume production-proven 40-nanometer (nm) G PCI Express Gen1/Gen2 Physical Layer (PHY).
The SiPro™ PCI Express PHY product line represents the first offering in Virage Logic’s advanced interface IP SiPro product portfolio that is a result of its collaboration with AMD announced in January 2009. This agreement grants Virage Logic the rights to license and modify certain AMD standards-based advanced interface IP that was designed for and used in the 40nm ATI Radeon™ graphics products from AMD.
“Our relationship with AMD has enabled us to accelerate the expansion of our broad product portfolio with production-proven standards-based IP for PCI Express,” said Kamalesh Ruparel, vice president and general manager, Application Specific IP (ASIP) solutions, Virage Logic.
“As the semiconductor industry’s trusted IP partner, we are committed to helping our customers reduce risk and speed new product development, particularly at the advanced nodes such as 40nm. The introduction of SiPro PCI Express PHY is yet another example of how we are delivering on that commitment.”
The Virage Logic SiPro PCI Express PHY is based on the successful implementation by AMD at 65nm, 55nm and 40nm, where it has been used in high-volume production for PC-oriented chipsets and graphics adaptors.
PCI Express standards are typically used in high-performance applications delivering large amounts of data from point-to-point, including storage, servers, networking, communications, high-end video applications and add-on PC cards.
“AMD has a long history with Virage Logic and views them as a trusted provider of highly differentiated physical IP,” said Chekib Akrout, corporate vice president, Central Engineering, AMD.
“Virage Logic has made a long-standing commitment to providing high-quality advanced semiconductor IP solutions and AMD’s internally designed, production-proven IP is the perfect complement to Virage Logic’s comprehensive product offering.”
The SiPro™ PCI Express PHY product line represents the first offering in Virage Logic’s advanced interface IP SiPro product portfolio that is a result of its collaboration with AMD announced in January 2009. This agreement grants Virage Logic the rights to license and modify certain AMD standards-based advanced interface IP that was designed for and used in the 40nm ATI Radeon™ graphics products from AMD.
“Our relationship with AMD has enabled us to accelerate the expansion of our broad product portfolio with production-proven standards-based IP for PCI Express,” said Kamalesh Ruparel, vice president and general manager, Application Specific IP (ASIP) solutions, Virage Logic.
“As the semiconductor industry’s trusted IP partner, we are committed to helping our customers reduce risk and speed new product development, particularly at the advanced nodes such as 40nm. The introduction of SiPro PCI Express PHY is yet another example of how we are delivering on that commitment.”
The Virage Logic SiPro PCI Express PHY is based on the successful implementation by AMD at 65nm, 55nm and 40nm, where it has been used in high-volume production for PC-oriented chipsets and graphics adaptors.
PCI Express standards are typically used in high-performance applications delivering large amounts of data from point-to-point, including storage, servers, networking, communications, high-end video applications and add-on PC cards.
“AMD has a long history with Virage Logic and views them as a trusted provider of highly differentiated physical IP,” said Chekib Akrout, corporate vice president, Central Engineering, AMD.
“Virage Logic has made a long-standing commitment to providing high-quality advanced semiconductor IP solutions and AMD’s internally designed, production-proven IP is the perfect complement to Virage Logic’s comprehensive product offering.”
Tuesday, July 28, 2009
Virage Logic extends IP technology leadership to 32/28nm process
Design Automation Conference 2009, SAN FRANCISCO, USA: Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP partner, today announced it has extended its advanced IP technology leadership to the 32/28-nanometer process node with the tape out of a product test chip with multiple IPs optimized for a high performance application for an early adopter customer.
The product test chip has advanced power management and at-speed test capabilities to address the power and yield challenges of 32/28nm and smaller geometries. In addition to the product test chip, Virage Logic has also taped out multiple 32nm test chips at leading foundries.
Because of Virage Logic’s proven track record of success at the 40nm process technology that includes multiple customers in production, the early adopter customer selected Virage Logic to leverage the power management capabilities of the SiWare memory compilers and advanced embedded memory test and repair capabilities of the STAR memory system for its first 32/28nm chip.
“Every new process node brings new manufacturing challenges that can impact overall design schedules and time to yield. At the advanced process nodes such as 32/28nm, the industry’s leaders will carefully select partners that enable them to proceed with confidence,” said Brani Buric, executive vice president of marketing and sales at Virage Logic.
“With more than ten 40nm customers, Virage Logic has once again proven that it has the technology leadership and know-how to provide its customers with early access to IP that meets their SoC design performance, cost and yield/ramp to volume goals.”
The product test chip has advanced power management and at-speed test capabilities to address the power and yield challenges of 32/28nm and smaller geometries. In addition to the product test chip, Virage Logic has also taped out multiple 32nm test chips at leading foundries.
Because of Virage Logic’s proven track record of success at the 40nm process technology that includes multiple customers in production, the early adopter customer selected Virage Logic to leverage the power management capabilities of the SiWare memory compilers and advanced embedded memory test and repair capabilities of the STAR memory system for its first 32/28nm chip.
“Every new process node brings new manufacturing challenges that can impact overall design schedules and time to yield. At the advanced process nodes such as 32/28nm, the industry’s leaders will carefully select partners that enable them to proceed with confidence,” said Brani Buric, executive vice president of marketing and sales at Virage Logic.
“With more than ten 40nm customers, Virage Logic has once again proven that it has the technology leadership and know-how to provide its customers with early access to IP that meets their SoC design performance, cost and yield/ramp to volume goals.”
Monday, July 13, 2009
Chartered begins production ramp of enhanced 65nm low-power process
SINGAPORE: Chartered Semiconductor Manufacturing announced the general availability of an enhanced version of its 65nm low-power (LP) process, called 65nm LPe.
The 65nm LPe process utilizes innovative leakage-reduction techniques to significantly improve system-on-chip (SoC) standby power consumption by up to 50 percent.
The result is a lower-power process especially suited for battery-operated and cost-sensitive mobile applications that require active standby conditions, such as mobile handsets, multimedia players or personal internet devices. The process is also supported by a robust range of IP specifically optimized for the lower leakage capabilities.
Chartered is also offering an optimized RF platform solution based on the 65nm LPe process that combines RF physical design kits, broad IP support and a collaborative development system with its partners from the Wireless SoC Platform Alliance (WISPA) consortium. (See additional press release from July 13, 2009: “Chartered Offers 65nm RF Platform To Enable Single-Chip Wireless Applications”).
The 65nm LPe process significantly improves the performance-to-leakage ratio (Ion/Ioff) within the process’ pMOSFET. Given the same Ion (uA/um), the Ioff current is reduced by a magnitude of 20X.
This directly impacts the battery life of mobile applications as this leakage improvement is observable in both active and standby situations. In cases where a product operates in long standby situations such as a mobile phone, improvement in the standby power consumption can be as great as 15-25 percent, depending on the application.
A full suite of IP is available for the new process from leading suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic Circuits, Denali, Synopsys, True Circuits and Virage Logic.
The support includes analog front end (AFE), audio codecs, standard interfaces and a range of level physical IP libraries and memory compilers that have been specifically tuned to take advantage of the enhanced leakage capabilities of the process.
Chartered’s enhanced 65nm LPe process features a core 25 angstrom transistor oxide with three voltage options (Standard Vt, Low Vt, High Vt). The High Vt option offers the lowest leakage at 0.01nA/um and 0.007nA/um for the NMOS and PMOS transistors, respectively.
Two thick gate oxides are available: a 32A device for 1.8V; and a flexible, IP-enabled 2.5V 52A device that is also useable for 1.8V and 3.3V applications by varying the channel length. The back end of line (BEOL) metal implementation supports up to nine layers of copper to optimize die size and routing efficiency.
Manufactured on rotated substrates, the 65LPe process benefits from an increase in the pMOSFET hole mobility and saturation velocity without detrimentally affecting the nMOSFET.
“Today’s high-volume mobile applications require highly optimized silicon solutions that operate in an extremely power-efficient manner, but don’t compromise performance or functionality,” said Brian Klene, vice president, product marketing at Chartered.
“Our 65nm LPe process has been developed specifically with extended battery life in mind, with optimizations made to the process itself and our ecosystem of design support to improve efficiency significantly. The 65nm LPe process is a full-featured and flexible platform on which a wide variety of wireless, mobile and multimedia products can be based.”
The 65nm LPe process utilizes innovative leakage-reduction techniques to significantly improve system-on-chip (SoC) standby power consumption by up to 50 percent.
The result is a lower-power process especially suited for battery-operated and cost-sensitive mobile applications that require active standby conditions, such as mobile handsets, multimedia players or personal internet devices. The process is also supported by a robust range of IP specifically optimized for the lower leakage capabilities.
Chartered is also offering an optimized RF platform solution based on the 65nm LPe process that combines RF physical design kits, broad IP support and a collaborative development system with its partners from the Wireless SoC Platform Alliance (WISPA) consortium. (See additional press release from July 13, 2009: “Chartered Offers 65nm RF Platform To Enable Single-Chip Wireless Applications”).
The 65nm LPe process significantly improves the performance-to-leakage ratio (Ion/Ioff) within the process’ pMOSFET. Given the same Ion (uA/um), the Ioff current is reduced by a magnitude of 20X.
This directly impacts the battery life of mobile applications as this leakage improvement is observable in both active and standby situations. In cases where a product operates in long standby situations such as a mobile phone, improvement in the standby power consumption can be as great as 15-25 percent, depending on the application.
A full suite of IP is available for the new process from leading suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic Circuits, Denali, Synopsys, True Circuits and Virage Logic.
The support includes analog front end (AFE), audio codecs, standard interfaces and a range of level physical IP libraries and memory compilers that have been specifically tuned to take advantage of the enhanced leakage capabilities of the process.
Chartered’s enhanced 65nm LPe process features a core 25 angstrom transistor oxide with three voltage options (Standard Vt, Low Vt, High Vt). The High Vt option offers the lowest leakage at 0.01nA/um and 0.007nA/um for the NMOS and PMOS transistors, respectively.
Two thick gate oxides are available: a 32A device for 1.8V; and a flexible, IP-enabled 2.5V 52A device that is also useable for 1.8V and 3.3V applications by varying the channel length. The back end of line (BEOL) metal implementation supports up to nine layers of copper to optimize die size and routing efficiency.
Manufactured on rotated substrates, the 65LPe process benefits from an increase in the pMOSFET hole mobility and saturation velocity without detrimentally affecting the nMOSFET.
“Today’s high-volume mobile applications require highly optimized silicon solutions that operate in an extremely power-efficient manner, but don’t compromise performance or functionality,” said Brian Klene, vice president, product marketing at Chartered.
“Our 65nm LPe process has been developed specifically with extended battery life in mind, with optimizations made to the process itself and our ecosystem of design support to improve efficiency significantly. The 65nm LPe process is a full-featured and flexible platform on which a wide variety of wireless, mobile and multimedia products can be based.”
Thursday, July 2, 2009
Virage Logic expands India presence with broad IP portfolio, CorelEL as sales rep
FREMONT, USA: Virage Logic Corp. has expanded its presence in India with the appointment of CoreEL as its sales representative. CoreEL joins a growing global network of sales representatives that complement and expand the reach of Virage Logic’s direct sales channel.
CoreEL’s more than 15 years experience working with India’s networking, telecom, computing, consumer, industrial, defense and automotive customers make them ideally suited to represent Virage Logic’s broad portfolio of silicon proven IP.
“As the semiconductor industry continues to globalize and more semiconductor companies rely on their India-based teams to make SoC design project decisions, the time was right to bring CoreEL on board to service our growing India customer base,” noted Jai Iyer, Virage Logic’s vice president of Asia sales.
“We are confident that the combination of CoreEL’s strong technology and design services experience will enable them to provide the superior sales and support services Virage Logic’s customers worldwide have come to expect.”
“India is rich in engineering talent and a target for companies worldwide to tap into the engineering resources,” said Vishwanath Padur, vice president of Sales and Marketing for CoreEL.
“With Virage Logic’s highly differentiated IP offering -– including embedded SRAMs, embedded NVMs, embedded memory test and repair, logic libraries, memory development software, and interface IP solutions -– we look forward to being able to provide even greater value to our extensive customer base as we help them address their SoC design challenges.”
CoreEL’s more than 15 years experience working with India’s networking, telecom, computing, consumer, industrial, defense and automotive customers make them ideally suited to represent Virage Logic’s broad portfolio of silicon proven IP.
“As the semiconductor industry continues to globalize and more semiconductor companies rely on their India-based teams to make SoC design project decisions, the time was right to bring CoreEL on board to service our growing India customer base,” noted Jai Iyer, Virage Logic’s vice president of Asia sales.
“We are confident that the combination of CoreEL’s strong technology and design services experience will enable them to provide the superior sales and support services Virage Logic’s customers worldwide have come to expect.”
“India is rich in engineering talent and a target for companies worldwide to tap into the engineering resources,” said Vishwanath Padur, vice president of Sales and Marketing for CoreEL.
“With Virage Logic’s highly differentiated IP offering -– including embedded SRAMs, embedded NVMs, embedded memory test and repair, logic libraries, memory development software, and interface IP solutions -– we look forward to being able to provide even greater value to our extensive customer base as we help them address their SoC design challenges.”
Wednesday, July 1, 2009
Virage Logic sees strong adoption of 40nm IP product portfolio
FREMONT, USA: Virage Logic Corp. announced that since being named TSMC’s 40nm early development partner in 2007, the company has seen strong adoption of its extensive 40nm product portfolio.
Comprising embedded SRAMS, embedded memory test and repair, logic libraries, and memory development software, the Company’s silicon-proven 40nm product offering has been designed to optimize area, performance, power and yield.
Today, more than 10 customers rely on Virage Logic’s 40nm product portfolio to design more efficient chips more quickly and with less risk as they develop products for such end markets as graphics, consumer, enterprise, networking, wireless, and handheld.
“Virage Logic has a long, proven track record of being first-to-market at the advanced process technologies and with our extensive 40nm product portfolio, we are proud to offer our customers a competitive advantage at this advanced process node,” said Brani Buric, Virage Logic’s executive vice president, marketing and sales.
“Our SiWare Memory and SiWare Logic products provide designers with a comprehensive dashboard of options for the flexibility needed to efficiently manage design tradeoffs and meet customers’ specific requirements. For example, this dashboard enables our customers to achieve up to a 90% power savings in 40nm G and LP process nodes.
“Our STAR Memory System embedded test and repair offering extends the value we can deliver by enabling customers to dramatically ramp to volume at advanced nodes such as 40nm,” he said. “Finally, our product portfolio is supported by a range of engagement models to best meet the requirements of our fabless, integrated device manufacturer (IDM) and foundry customers.”
“TSMC selected Virage Logic as an early development partner at 40nm as a continuation of our collaboration in technologies ranging from 250nm to 40nm. Virage Logic and TSMC work closely to qualify IP through both Virage Logic’s procedures and TSMC’s procedures including silicon validation of these advanced technology IP solutions,” said Dan Kochpatcharin, deputy director, IP Portfolio Marketing at TSMC.
“These extensive silicon quality report results are available to designers of advanced SoCs for review when choosing Virage Logic’s broad IP portfolio on TSMC’s 40nm process.”
Comprising embedded SRAMS, embedded memory test and repair, logic libraries, and memory development software, the Company’s silicon-proven 40nm product offering has been designed to optimize area, performance, power and yield.
Today, more than 10 customers rely on Virage Logic’s 40nm product portfolio to design more efficient chips more quickly and with less risk as they develop products for such end markets as graphics, consumer, enterprise, networking, wireless, and handheld.
“Virage Logic has a long, proven track record of being first-to-market at the advanced process technologies and with our extensive 40nm product portfolio, we are proud to offer our customers a competitive advantage at this advanced process node,” said Brani Buric, Virage Logic’s executive vice president, marketing and sales.
“Our SiWare Memory and SiWare Logic products provide designers with a comprehensive dashboard of options for the flexibility needed to efficiently manage design tradeoffs and meet customers’ specific requirements. For example, this dashboard enables our customers to achieve up to a 90% power savings in 40nm G and LP process nodes.
“Our STAR Memory System embedded test and repair offering extends the value we can deliver by enabling customers to dramatically ramp to volume at advanced nodes such as 40nm,” he said. “Finally, our product portfolio is supported by a range of engagement models to best meet the requirements of our fabless, integrated device manufacturer (IDM) and foundry customers.”
“TSMC selected Virage Logic as an early development partner at 40nm as a continuation of our collaboration in technologies ranging from 250nm to 40nm. Virage Logic and TSMC work closely to qualify IP through both Virage Logic’s procedures and TSMC’s procedures including silicon validation of these advanced technology IP solutions,” said Dan Kochpatcharin, deputy director, IP Portfolio Marketing at TSMC.
“These extensive silicon quality report results are available to designers of advanced SoCs for review when choosing Virage Logic’s broad IP portfolio on TSMC’s 40nm process.”
Monday, June 29, 2009
Virage Logic joins Power.org community
PISCATAWAY, USA: Power.org, the organization that promotes and develops standards for Power Architecture technology, today announced that Virage Logic Corp., the semiconductor industry's trusted IP partner, has joined Power.org as a participant member.
Virage Logic provides an extensive range of semiconductor IP that removes the traditional bottleneck in processor design -- access to embedded memories and silicon implementation -- speeding time-to-market and helping minimize design costs.
"The strength of a processor is dependent on its peripherals and with Virage Logic's production-proven, advanced interface IP solutions, PowerPC-based designs can leverage the critical IP required for successful SoC designs," said Power.org CTO, Kaveh Massoudian.
"The company's technology and expertise will provide a valuable asset to the Power Architecture ecosystem, making Power Architecture technology available to the mass market and to the mainstream fabless semiconductor market."
Recently, Virage Logic announced an agreement with IBM designating the company as an IBM PowerPC Design Center, granting it the rights to license and distribute IBM's PowerPC processor and peripheral cores when combined with Virage Logic's broad portfolio of semiconductor IP.
"Our participation in Power.org allows us to broaden the portfolio of highly differentiated silicon-proven IP available to the Power.org community," said Dr. Yankin Tanurhan, vice president and general manager, non-volatile memory (NVM) solutions, Virage Logic. "We look forward to working closely with members of the organization to drive innovation while helping them achieve their cost, performance and time-to-market goals."
Virage Logic provides an extensive range of semiconductor IP that removes the traditional bottleneck in processor design -- access to embedded memories and silicon implementation -- speeding time-to-market and helping minimize design costs.
"The strength of a processor is dependent on its peripherals and with Virage Logic's production-proven, advanced interface IP solutions, PowerPC-based designs can leverage the critical IP required for successful SoC designs," said Power.org CTO, Kaveh Massoudian.
"The company's technology and expertise will provide a valuable asset to the Power Architecture ecosystem, making Power Architecture technology available to the mass market and to the mainstream fabless semiconductor market."
Recently, Virage Logic announced an agreement with IBM designating the company as an IBM PowerPC Design Center, granting it the rights to license and distribute IBM's PowerPC processor and peripheral cores when combined with Virage Logic's broad portfolio of semiconductor IP.
"Our participation in Power.org allows us to broaden the portfolio of highly differentiated silicon-proven IP available to the Power.org community," said Dr. Yankin Tanurhan, vice president and general manager, non-volatile memory (NVM) solutions, Virage Logic. "We look forward to working closely with members of the organization to drive innovation while helping them achieve their cost, performance and time-to-market goals."
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