Semico releases two reports on ASIC design starts

PHOENIX, USA: Semico Research Corp. has just released two reports that provide both an historical analysis and forecasts the future of ASIC design starts.

The current global economic slowdown is having an adverse impact on design starts for ASICs. The slowing of design start activity began at the end of 2008 and is continuing through 2009. Semico believes design activity will recover back to more historical norms in 2010.

The “ASIC Design Starts: Changes in Industry Dynamics” report provides an in-depth perspective by showing a comparison between design starts for SoCs and all other types of ASICs.

This report also examines the continuing increase in SoC design costs. ASIC design starts data show changes in design for each device type including analog, mixed signal, gate array, PLD, FPGA, performance SoC, value SoC and structured ASIC.

The design starts data is further segmented by: product type, process geometry, gate count and geographic region. This report contains a wealth of data in 55 tables and 58 figures/graphs.

The “ASIC Design Starts: By Key Applications Revisited II” report segments the data by 66 of the key end applications that drive the design starts market within the computing, communications, consumer, transportation and industrial segments. Within each end application, the data is further segmented by: Analog, Mixed Signal, Performance and Value SoC, PLD, FPGA, Gate Array and Structured ASIC. This report contains an enormous amount of data in 134 tables and 69 figures/graphs.



Both reports complement each other. For each segment, they include design starts and the ASIC unit volumes associated with those design starts. While they use the same worldwide design starts information, each report analyzes the data from a different perspective.

Altera on FPGAs outlook for 2009

Hardly any segment of the global semiconductor industry has escaped the economic financial crisis! Nevertheless, as the year draws to a close, several segments are planning strategies for tackling what could well be a difficult 2009! FPGAs are no exception!

Jennifer Lo, Senior Marketing Manager, Altera Asia Pacific, agrees. Highlighting the impact, as per reports in the media, the economical environment we are getting into is extremely challenging. Recently, Gartner lowered its 2009 semiconductor forecast to 'down 16 percent' as compared to 2008.

Altera placed strongly
Lo says that compared to the other semiconductor companies, many of whom are taking very drastic measures in cutting down costs and preserving capital, Altera is in a very strong position, both financially and product-wise.

Financially, Altera is said to have taken steps to focus on cost reductions and simplification internally, a few years ago. The company is seeing great results from those efforts. "You may check our financial data and find that we are essentially debt-free and have very healthy balance sheet. We continue to be profitable even under the very challenging environment we are in," Lo contends.

Product-wise, Altera announced a few days ago that it is shipping the industry’s 40nm product, considered a key milestone. "We are very excited about it with this new product family, Stratix IV, which offers the industry’s largest density, highest performance, highest system bandwidth and lowest power, targeting customers in a variety of markets, including communications, broadcast, test, medical and military," she says.

Going forward in 2009, Altera will continue to rollout the rest of the members in the Stratix IV product family. It will also continue to execute new product strategies in the plan with full confidence.

Tackling demand weakness in FPGAs
There have been whispers regarding demand weakness in the FPGA industry. On the contrary, Lo adds that lower power, lower cost and smaller space are still common needs for portable applications for 2009. These needs may drive PLD vendors to focus on architecture and process to address power and cost. Also, work on package to develop a smaller device. Altera's goal is to still focus on these common needs.

The Altera MAX II Z already offers the lowest dynamic power and comparable static power in industry already. The company may focus more on package size on 2009.

Although leading-edge FPGAs are scaling to 40nm and beyond, have the tools caught up with these new and complex processes? She says that lowering power consumption and improving customer productivity have been the focus of Altera's product strategies for the past few years.

Lo adds: "Lowering power consumption means lowering costs for customers, not only in the BOM cost (reducing heatsink or cooling requirement), but also the ongoing operating cost (fans, air-conditioning costs,…etc). At this day and age of ever increasing fuel and electricity costs, this is gaining significance in customers' selection consideration. Seeing such a need, reducing device power consumption has been a major element in the company's product planning and execution."

Altera's Max II Z product in the low-cost CPLD line offers the lowest dynamic power and static power in the industry that is catered for the portable applications. On the high end of the spectrum, with Stratix IV GX, for example, with the advanced 40nm process node, Altera utilizes the 'Strained Silicon' technology, lower core voltage of 0.9V, triple gate oxide, as well as low-K inter-metal dielectric material low power transceiver designs.

"In terms of design, we put in extra effort in lowering the overall power consumption in the transceivers as well as optimized DDR memory interfaces," she notes.

Coupled with programmable power technology, which allows customers to use high performance (hence, high power consumption) circuitry for design along the critical path, while either using low-power circuit on other parts of the design or turning the logic blocks completely off while not in use, all process and design innovations work together toward one common goal of lowering the overall power consumption in the customer design.

Lo says: "In customer productivity improvement, we’ve invested in the feature sets in our design software, Quartus II, to enable team-based designs, incremental compilation, as well as faster compilation time compared to the other competing software. We also have a wide suite of IPs in a multitude of applications and technologies, such as our Nios embedded processors, the many memory interfaces and peripherals. Combining all of those with our SOPCBuilder tool also enables customers to integrate system designs with very much reduced time and effort."

There have also been some talks lately about FPGA design starts being quite flat over the last couple of years.

Altera sees a lot of new market applications for FPGAs, apart from the traditional communications market. Out of the many market segments that it participates in, the company feels that communications, military and industrial segments will be in better situation than others in the next couple of years. Needless to say, Altera will continue to focus on these segments.

Tackling complexity
Tackling complexity is a major focus area for projecting FPGAs as a growth segment for 2009.

Lo says: that as with other previous downturns, the industry may go through its reformation, which may inevitably involve some weaker companies to either go out of business due to deteriorating business environment or get acquired by stronger companies. Altera is very confident that programmable logic, with its highly flexibility, versatile application, will have a good market position in 2009.

The Hardcopy ASIC is said to have been Altera's major differentiator from the other PLD/FPGA vendors.

"We are the only company having both an FPGA vehicle to enable fast time-to-market and simultaneously possessing the seamless migration platform to low-cost production support using Hardcopy ASIC. With the industry trend of fewer and fewer ASIC starts due to the high NRE costs and high justifying volume, there will also be less investment in the ASSP front given the contracting demand. We see Hardcopy as a major competitive edge that will us bring to a different rank in the industry," she notes.

Indeed, it is good to see companies thinking very hard about tackling a difficult 2009! There's lot of fight left, and it's not that semiconductor companies haven't faced downturns earlier. Keep the faith and allow these folks to come up tops again!

Altera strategy to partner with Indian design services firms

Turning my attention to the programmable logic market, I took advantage of my recent meeting with Jordan Plofsky, Senior Vice President Market, Altera Corp., during the Altera SOPC conference.

Programmable logic consumption in India has been estimated at between $20-$25 million in 2008, largely driven by strong growth in communications infrastructure and increased spending in the military sector. The Indian programmable logic market is likely to grow at a CAGR of 25 percent over the next three years.

Altera's India strategy
In this context, it will be interesting to note Altera's strategy within the Indian semiconductor industry.

Plofsky says that as multinational companies are transferring more design work to their R&D teams in India, local companies are expanding their range of products, and independent design service companies are capturing a bigger piece of the outsourced design pie, Altera forecasts the increased need for high quality application support.

He says: "Unlike other companies who have design services operations in India, which compete with the local independent design services, our strategy is to partner with the local India design services industry. We are expanding our direct and indirect support channels to provide higher quality services to our customers here."

Altera is also supporting the development of the education sector in India, which is modernizing to turn out well trained engineers to satisfy the appetite of the industry. "We also run industrial workshops and seminars, like the recent SOPC World in Bangalore and New Delhi, to educate the design community on the direction of semiconductor technology," adds Plofsky.

Altera has also set up Altera Joint Laboratories in leading universities across India to provide a better platform for undergraduates to grasp basics of programmability.

Role in solar?
With investments in solar/PV happening, is there a role for Altera and other FPGA companies? This is a question that I invariably ask everyone in the semiconductor industry!

According to Plofsky, one of the promising applications is smart metering. It is the practice of getting the users and the infrastructure to be power aware and then using different usage patterns to lower energy usage and energy costs by applying smart algorithms.

Addressing low-power design
Power consumption has always been a big concern for designers in all markets and Altera has a number of different solutions.

In the CPLD area, Altera announced its zero power MAX IIZ devices in late 2007. Offering the highest density and I/O count in packages as small as 5x5mm, compared to macrocell-based CPLDs, MAX IIZ devices allow designers to meet changing functional requirements and lower power while saving board space.

Consuming 75 percent less power than competing FPGAs, the Altera Cyclone III devices are the industry's first and only 65-nm low-cost FPGA family, and offer digital system designers an unprecedented combination of density, power and cost.

To address the low-power demands of high density customers, the Stratix III and Stratix IV family members feature Altera's patented Programmable Power Technology. This power-saving technology optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design. And in addition these designs can be converted to HardCopy ASIC devices that can reduce power consumption by 50-70 percent.

As for new products in the LTE, TD-SCDMA and NFC spaces, Plofsky says that with the new 40-nm devices, Altera is uniquely positioned to deliver solutions that provide the density, performance and power for these emerging applications. The combination of DSP blocks, memory and transceivers was optimized for these communication applications.

Roadmap beyond
Altera just announced its 40nm devices in May and it is said to be on target to deliver those devices by the end of 2008.

Adds Plofsky: "We have already started development work on smaller process geometries with test chips in fab now, but it is too early to go into any family detail at this time."

Introducing FPGA Central!

All of those related to the FPGA and VLSI segments, there's reason to rejoice. The world's first dedicated portal on FPGAs is here!

FPGA Central is said to be central place to find complete info about FPGA vendors, products, IPs, etc.

Field programmable gate array, aka, FPGAs is a semiconductor device containing programmable logic components called 'logic blocks', and programmable interconnects. They are especially popular for prototyping integrated circuit designs. Once the design is set, hardwired chips are produced for faster performance. Its flexibility and low cost of implementation is the key factor for its success.

FPGA Central aims to bring all FPGA related information under one central location. A vendor neutral place to find everything about FPGAs, CPLDs, EDA Tools for FPGAs.

FPGA Central has been created to provide a central place for FPGA vendors and users to share experiences and information about FPGA design, development, verification, validation, process, tools and products.

The sites major feature includes:
* Largest FPGA vendor directory (over 450)
* Vast product directory (over 800)
* IP catalog (over 750)
* Find FPGA events around the world
* FPGA discussion forums
* Latest FPGA news and press releases
* FPGA jobs listing

A release said: "We are enhancing user experience by providing reviews and ratings of all the listing on our Web site. The users are encouraged to discuss their problems and share thoughts." This is just the beginning! Over the next couple of months, FPGA Central plans to add more features to help users to make more informative decisions and vendors to showcase their products.

Need I say more? I was also able to post two articles and the previous blog on the ISA-VSI awards on FPGA Central. Look forward to receiving the newsletters as well. At least, I won't need to look around all over the Web for FPGA related stuff, and believe that FPGA Central would do the job for me.