SANTA CLARA, USA: Calypto Design Systems Inc. announced it has developed the industry’s most accurate register-transfer level (RTL) power analysis capability by applying its patented sequential analysis technology to enable accurate power measurement in its PowerPro Analyzer tool.
The tool performs sequential analysis of the entire design, delivering power measurement results that are significantly more accurate than the decade-old RTL power analysis tools in use today. These obsolete tools are based on combinational analysis which limits the accuracy of switching activity propagation compared to the actual sequential circuit activity. Sequential analysis ensures switching activity propagation estimated by the tool closely correlates with real life circuit activity.
By dramatically improving RTL power analysis accuracy, PowerPro Analyzer will enable designers to finally move away from time-consuming, gate-level power analysis flows.
These flows require designers to run complex gate-level simulations in order to provide the power analysis tool with accurate design behavior that emulates real-world functionality. Running those same simulations at the RTL level improves efficiency by 10x, often reducing the overall power analysis task time from days to hours.
Moreover, RTL-level simulation is part of the standard simulation regression method used by designers to verify their design. The RTL simulation results can be provided to Calypto’s PowerPro Analyzer without adding to design schedules.
“The inaccuracy of existing RTL power analysis tools has limited their adoption and forced the industry to continue using complex, schedule-extending, gate-level power analysis techniques,” said Tom Sandoval, chief executive officer of Calypto.
“Having experienced the benefits of sequential analysis technology for RTL power optimization, our customers have asked us to solve the shortcomings of existing RTL power analysis tools, and we are answering this call by adding power analysis capabilities to PowerPro Analyzer.”
Showing posts with label Calypto Design Systems. Show all posts
Showing posts with label Calypto Design Systems. Show all posts
Tuesday, August 25, 2009
Tuesday, July 28, 2009
Calypto's fully automated sequential optimization flow for high-performance IP blocks
SAN FRANCISCO, USA: Calypto Design Systems Inc. has announced a fully automated design flow aimed at advancing the delivery of optimized, high-performance IP blocks found in today’s leading SoC designs.
Enabled by Calypto’s SLEC RTL tool and new analysis capabilities in its proven PowerPro CG (clock gating) tool, Calypto’s Sequential Optimization Flow allows designers, for the first time, to use a fully automated flow to optimize power, area, and timing for high-performance IP blocks, such as microprocessors and digital signal processors (DSPs). Using the flow, designers are also assured that functionality is maintained throughout the process.
Calypto will demonstrate its Sequential Optimization Flow this week at its booth during the 2009 Design Automation Conference (DAC) held in San Francisco.
"With each new generation of electronics products, SoC designers are challenged to deliver higher performance functions that dissipate less power and occupy less silicon area than the previous generation," said Tom Sandoval, CEO of Calypto.
"We have developed an automated flow that dramatically reduces the design time and resources required to deliver low-power, high-performance, differentiated functionality. As a result, even small SoC design teams are enabled to efficiently meet their strict power, performance and area goals using an automated method that includes proven tools for both optimization and comprehensive verification."
Without an automated approach, design teams have been forced to engage in manual optimizations that can be costly, time consuming and error prone. This process frequently results in timing issues which, in turn, lead to increased circuit area and power consumption.
Moreover, manual optimizations require extensive resources and unique skill sets, making the process off-limits to smaller design teams. Calypto’s new Sequential Optimization Flow addresses these challenges.
Calypto's new Sequential Optimization Flow includes PowerPro CG, which takes an RTL design and automatically generates a power-optimized RTL design. Both the original and power-optimized RTL designs are run through a third-party synthesis tool, such as the Encounter RTL Compiler from Cadence Design Systems, Inc., to create two gate-level netlists.
With the new automated analysis capabilities of PowerPro CG, the timing and power consumption of both netlists are automatically analyzed so that targeted retiming synthesis can be run on the power-optimized, gate-level netlist. Using Calypto’s SLEC RTL, functional equivalence between the original RTL and the new timing- and power-optimized gate level netlist is verified.
By combining gate-level retiming with automated RTL power optimization and sequential logic equivalence checking, Calypto’s Sequential Optimization Flow enables SoC design teams to optimize power, area and timing for IP blocks and complex functions that were previously considered off-limits to such optimizations.
New sequential optimization flow @ DAC 2009
Calypto is showcasing the results of running the Sequential Optimization Flow on the Sun Microsystems OpenSPARC T1 processor core at the 2009 DAC. Sun has made this 64-bit, high-throughput, low-power core available to the public under the GNU v2.0 license.
Calypto will demonstrate how running the core through the flow results in a 24 percent power advantage and almost five percent area advantage over the original core, with no performance impact. DAC attendees will see, firsthand, the effectiveness of the flow. Details of the Sequential Optimization Flow and the results of using the flow on the OpenSPARC core will be provided.
Calypto will also demonstrate its full suite of PowerPro and SLEC products at this year's DAC in booth #1610, being held July 26-31 in San Francisco at the Moscone Center.
Available now, Calypto’s PowerPro CG runs on PC platforms running Linux and is priced at $295,000 (US) for a one-year, time-based license. Existing PowerPro CG customers will be upgraded to the new version at no charge. SLEC RTL is available now and is priced at $175,000 (US) for a one-year, time-based license. Synthesis solutions are available directly from their manufacturers.
Enabled by Calypto’s SLEC RTL tool and new analysis capabilities in its proven PowerPro CG (clock gating) tool, Calypto’s Sequential Optimization Flow allows designers, for the first time, to use a fully automated flow to optimize power, area, and timing for high-performance IP blocks, such as microprocessors and digital signal processors (DSPs). Using the flow, designers are also assured that functionality is maintained throughout the process.
Calypto will demonstrate its Sequential Optimization Flow this week at its booth during the 2009 Design Automation Conference (DAC) held in San Francisco.
"With each new generation of electronics products, SoC designers are challenged to deliver higher performance functions that dissipate less power and occupy less silicon area than the previous generation," said Tom Sandoval, CEO of Calypto.
"We have developed an automated flow that dramatically reduces the design time and resources required to deliver low-power, high-performance, differentiated functionality. As a result, even small SoC design teams are enabled to efficiently meet their strict power, performance and area goals using an automated method that includes proven tools for both optimization and comprehensive verification."
Without an automated approach, design teams have been forced to engage in manual optimizations that can be costly, time consuming and error prone. This process frequently results in timing issues which, in turn, lead to increased circuit area and power consumption.
Moreover, manual optimizations require extensive resources and unique skill sets, making the process off-limits to smaller design teams. Calypto’s new Sequential Optimization Flow addresses these challenges.
Calypto's new Sequential Optimization Flow includes PowerPro CG, which takes an RTL design and automatically generates a power-optimized RTL design. Both the original and power-optimized RTL designs are run through a third-party synthesis tool, such as the Encounter RTL Compiler from Cadence Design Systems, Inc., to create two gate-level netlists.
With the new automated analysis capabilities of PowerPro CG, the timing and power consumption of both netlists are automatically analyzed so that targeted retiming synthesis can be run on the power-optimized, gate-level netlist. Using Calypto’s SLEC RTL, functional equivalence between the original RTL and the new timing- and power-optimized gate level netlist is verified.
By combining gate-level retiming with automated RTL power optimization and sequential logic equivalence checking, Calypto’s Sequential Optimization Flow enables SoC design teams to optimize power, area and timing for IP blocks and complex functions that were previously considered off-limits to such optimizations.
New sequential optimization flow @ DAC 2009
Calypto is showcasing the results of running the Sequential Optimization Flow on the Sun Microsystems OpenSPARC T1 processor core at the 2009 DAC. Sun has made this 64-bit, high-throughput, low-power core available to the public under the GNU v2.0 license.
Calypto will demonstrate how running the core through the flow results in a 24 percent power advantage and almost five percent area advantage over the original core, with no performance impact. DAC attendees will see, firsthand, the effectiveness of the flow. Details of the Sequential Optimization Flow and the results of using the flow on the OpenSPARC core will be provided.
Calypto will also demonstrate its full suite of PowerPro and SLEC products at this year's DAC in booth #1610, being held July 26-31 in San Francisco at the Moscone Center.
Available now, Calypto’s PowerPro CG runs on PC platforms running Linux and is priced at $295,000 (US) for a one-year, time-based license. Existing PowerPro CG customers will be upgraded to the new version at no charge. SLEC RTL is available now and is priced at $175,000 (US) for a one-year, time-based license. Synthesis solutions are available directly from their manufacturers.
Monday, July 20, 2009
Calypto enables ESL design, verification of complex designs
Design Automation Conference 2009, SANTA CLARA, USA: Enabling electronic system level (ESL) design flows for increasingly complex system on a chip (SOC) devices, Calypto Design Systems Inc. announced the release of SLEC 4.0, the latest version of its popular sequential logic equivalence checking (SLEC) product family.
SLEC is the semiconductor industry’s only comprehensive functional verification solution that formally verifies equivalence between ESL models and RTL implementations. The new version has up to five times the capacity of the previous version and provides tighter integration with the leading high-level synthesis (HLS) tools from Cadence Design Systems, Mentor Graphics, and Forte.
“HLS tools are becoming more efficient at handling larger functions. As a result, customers are applying HLS tools to design blocks with significant complexity, especially from a sequential perspective,” said Tom Sandoval, CEO of Calypto Design Systems.
“SLEC 4.0 keeps pace with the most sophisticated designs and provides an automated path to comprehensive verification with the industry’s only proven sequential equivalence checker. With SLEC, designers can avoid running time-consuming simulations and can uncover bugs that might otherwise go undetected and cause catastrophic delays to product development timelines.”
Calypto pioneered sequential logic equivalence checking when it announced its first version of SLEC nearly five years ago. Since that time, SLEC’s capacity has grown from thousand-gate blocks and tens of cycles of sequential complexity to hundreds of thousands of gates and thousands of cycles of sequential complexity.
The verification challenges have increased exponentially with these more sophisticated functions, making traditional simulation-based verification even less effective.
Optimized database and improved integration with HLS tools
Featuring algorithmic enhancements to Calypto’s patented word level solvers, the latest version of SLEC also includes dramatic improvement to SLEC’s proprietary database that results in a reduced memory footprint while SLEC is running. Together, these advancements enable the tool to handle larger, more complex designs.
As a result, designers can more freely use high level synthesis for the generation of highly complex functions, knowing that SLEC can provide comprehensive verification. The interface between SLEC and the leading HLS tools — Mentor Catapult, Cadence C-to-Silicon compiler, and Forte Cynthesizer — has also been improved in SLEC 4.0 to ensure an automated, efficient path to formal verification, requiring little or no user intervention.
Multiple clock support added
The ability to handle multiple clock designs has traditionally been a limitation with sequential logic equivalence checking. As SLEC capacity has increased, allowing the tool to support larger and more complex graphics, networking, multimedia, and wireless functions, the need to comprehensively verify designs with multiple clocks has become more and more prevalent.
With version 4.0, SLEC customers can now fully verify designs with multiple, independent clocks. For example, SLEC RTL can verify that the relationship between two clocks -- e.g., one clock is a multiple of another) is not disrupted by the manual introduction of sequential optimizations for power or performance by a designer. SLEC RTL can also now detect the illegal mixing of signals from different clock domains introduced by sequential transformations.
The SLEC family of products includes:
* SLEC System: Formally verifies equivalence of system-level models and RTL designs.
* SLEC System-HLS: Formally verifies that an RTL design generated using high-level synthesis is functionally equivalent to its corresponding system level model.
* SLEC RTL: Formally ensures functional equivalence between a golden RTL model and a corresponding RTL model has been sequentially modified to reduce power or improve performance.
* SLEC Pro: Comprehensively verifies that an RTL design generated by Calypto’s PowerPro product is functionally equivalent to its corresponding golden RTL model.
* SLEC 4.0 Showcased at 2009 DAC, Calypto to Present and Co-host Luncheon.
SLEC is the semiconductor industry’s only comprehensive functional verification solution that formally verifies equivalence between ESL models and RTL implementations. The new version has up to five times the capacity of the previous version and provides tighter integration with the leading high-level synthesis (HLS) tools from Cadence Design Systems, Mentor Graphics, and Forte.
“HLS tools are becoming more efficient at handling larger functions. As a result, customers are applying HLS tools to design blocks with significant complexity, especially from a sequential perspective,” said Tom Sandoval, CEO of Calypto Design Systems.
“SLEC 4.0 keeps pace with the most sophisticated designs and provides an automated path to comprehensive verification with the industry’s only proven sequential equivalence checker. With SLEC, designers can avoid running time-consuming simulations and can uncover bugs that might otherwise go undetected and cause catastrophic delays to product development timelines.”
Calypto pioneered sequential logic equivalence checking when it announced its first version of SLEC nearly five years ago. Since that time, SLEC’s capacity has grown from thousand-gate blocks and tens of cycles of sequential complexity to hundreds of thousands of gates and thousands of cycles of sequential complexity.
The verification challenges have increased exponentially with these more sophisticated functions, making traditional simulation-based verification even less effective.
Optimized database and improved integration with HLS tools
Featuring algorithmic enhancements to Calypto’s patented word level solvers, the latest version of SLEC also includes dramatic improvement to SLEC’s proprietary database that results in a reduced memory footprint while SLEC is running. Together, these advancements enable the tool to handle larger, more complex designs.
As a result, designers can more freely use high level synthesis for the generation of highly complex functions, knowing that SLEC can provide comprehensive verification. The interface between SLEC and the leading HLS tools — Mentor Catapult, Cadence C-to-Silicon compiler, and Forte Cynthesizer — has also been improved in SLEC 4.0 to ensure an automated, efficient path to formal verification, requiring little or no user intervention.
Multiple clock support added
The ability to handle multiple clock designs has traditionally been a limitation with sequential logic equivalence checking. As SLEC capacity has increased, allowing the tool to support larger and more complex graphics, networking, multimedia, and wireless functions, the need to comprehensively verify designs with multiple clocks has become more and more prevalent.
With version 4.0, SLEC customers can now fully verify designs with multiple, independent clocks. For example, SLEC RTL can verify that the relationship between two clocks -- e.g., one clock is a multiple of another) is not disrupted by the manual introduction of sequential optimizations for power or performance by a designer. SLEC RTL can also now detect the illegal mixing of signals from different clock domains introduced by sequential transformations.
The SLEC family of products includes:
* SLEC System: Formally verifies equivalence of system-level models and RTL designs.
* SLEC System-HLS: Formally verifies that an RTL design generated using high-level synthesis is functionally equivalent to its corresponding system level model.
* SLEC RTL: Formally ensures functional equivalence between a golden RTL model and a corresponding RTL model has been sequentially modified to reduce power or improve performance.
* SLEC Pro: Comprehensively verifies that an RTL design generated by Calypto’s PowerPro product is functionally equivalent to its corresponding golden RTL model.
* SLEC 4.0 Showcased at 2009 DAC, Calypto to Present and Co-host Luncheon.
Friday, June 12, 2009
Calypto delivers ‘picture perfect’ ESL solution to Casio
SANTA CLARA, USA: Demonstrating the widespread adoption of its popular SLEC System HLS (High Level Synthesis) tool, Calypto Design Systems, a leader in sequential analysis technology, announced that Casio will incorporate SLEC into its electronic system level (ESL) design flow for new digital camera designs.
Casio plans to pair Calypto’s formal verification tool with the Cadence Design Systems' C-to-Silicon Compiler to improve design efficiency and reduce time-to-tomarket for its digital cameras.
The combination of the Cadence and Calypto technologies allows engineers to work at a much higher level of abstraction, engaging in true ESL design. Using C-to-Silicon Compiler, Casio will automatically generate synthesizable register transfer level (RTL) code from SystemC code that can then be comprehensively verified by SLEC SystemHLS.
The automated ESL flow will allow Casio to run multiple “what if” scenarios and evaluate different design implementations to ensure that the final product delivers the best combination of cost and performance possible while ensuring functional correctness.
“Digital camera design has become increasingly sophisticated, and gate complexity is now 10 times what it was just three years ago,” said Kazuyuki Kurosawa, section manager of Digital Camera Product Unit, Casio. “Before implementing an automated unified ESL flow, we were forced to engage in time-consuming RTL hand coding and verification through RTL simulation regressions to generate and verify our design –– a process that consumed valuable engineering resources and limited our ability to innovate. By automating these two complex steps, Calypto and Cadence allow us to reduce design time and focus our resources on bringing true differentiation to our products.”
“There is an ongoing effort for design teams to find ways to increase productivity and achieve faster time-to-market,” said Tom Sandoval, CEO Calypto Design Systems. “Cadence C-to-Silicon Compiler and its integration with Calypto’s SLEC SystemHLS are proven to meet this demand, allowing designers to use their valuable design time for innovation, rather than tedious simulation and coding.”
Cadence's C-to-Silicon Compiler bridges the gap between RTL design and system-level models, usually written in C/C++ and SystemC. Fulfilling the industry requirement for formal equivalence checking, designers can then perform comprehensive functional verification using the Calypto SLEC System-HLS to formally verify equivalence between SystemC ESL models and RTL implementations.
By integrating their technologies, Cadence and Calypto deliver a fully automated system-level design solution that dramatically increases designer productivity.
“Our customers now have a best-in-class comprehensive solution for system level design and verification,” said Michael McNamara, vice president and general manager of the Systems Software Group at Cadence Design Systems. “The tight integration between Calypto’s SLEC SystemHLS and Cadence C-to-Silicon Compiler gives our customers an optimal flow that is rapidly becoming a standard approach for advanced SoC design.”
Casio plans to pair Calypto’s formal verification tool with the Cadence Design Systems' C-to-Silicon Compiler to improve design efficiency and reduce time-to-tomarket for its digital cameras.
The combination of the Cadence and Calypto technologies allows engineers to work at a much higher level of abstraction, engaging in true ESL design. Using C-to-Silicon Compiler, Casio will automatically generate synthesizable register transfer level (RTL) code from SystemC code that can then be comprehensively verified by SLEC SystemHLS.
The automated ESL flow will allow Casio to run multiple “what if” scenarios and evaluate different design implementations to ensure that the final product delivers the best combination of cost and performance possible while ensuring functional correctness.
“Digital camera design has become increasingly sophisticated, and gate complexity is now 10 times what it was just three years ago,” said Kazuyuki Kurosawa, section manager of Digital Camera Product Unit, Casio. “Before implementing an automated unified ESL flow, we were forced to engage in time-consuming RTL hand coding and verification through RTL simulation regressions to generate and verify our design –– a process that consumed valuable engineering resources and limited our ability to innovate. By automating these two complex steps, Calypto and Cadence allow us to reduce design time and focus our resources on bringing true differentiation to our products.”
“There is an ongoing effort for design teams to find ways to increase productivity and achieve faster time-to-market,” said Tom Sandoval, CEO Calypto Design Systems. “Cadence C-to-Silicon Compiler and its integration with Calypto’s SLEC SystemHLS are proven to meet this demand, allowing designers to use their valuable design time for innovation, rather than tedious simulation and coding.”
Cadence's C-to-Silicon Compiler bridges the gap between RTL design and system-level models, usually written in C/C++ and SystemC. Fulfilling the industry requirement for formal equivalence checking, designers can then perform comprehensive functional verification using the Calypto SLEC System-HLS to formally verify equivalence between SystemC ESL models and RTL implementations.
By integrating their technologies, Cadence and Calypto deliver a fully automated system-level design solution that dramatically increases designer productivity.
“Our customers now have a best-in-class comprehensive solution for system level design and verification,” said Michael McNamara, vice president and general manager of the Systems Software Group at Cadence Design Systems. “The tight integration between Calypto’s SLEC SystemHLS and Cadence C-to-Silicon Compiler gives our customers an optimal flow that is rapidly becoming a standard approach for advanced SoC design.”
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