WILSONVILLE, USA: Mentor Graphics Corp. recently announced results for the fiscal second quarter 2010, ending July 31, 2009. For the quarter, the company reported revenues of $182.6 million, non-GAAP earnings per share of $.02, and a GAAP loss per share of $.22. Bookings for the quarter rose 15 percent over the prior fiscal second quarter.
“The quarter’s strong bookings performance was driven by new customers and new products. Though the business climate is still difficult, we did see strong sequential increases in consulting and distributor bookings during the quarter, both signs we take as indicators of an improving customer environment,” said Walden C. Rhines, CEO and chairman of Mentor Graphics.
“The company continues to build its strength in new markets, expanding its electronic system level design (ESL) and low-power product offerings during the quarter. Taiwan Semiconductor Manufacturing Co.'s (TSMC) inclusion of a full Mentor low-power implementation flow in their Reference Flow 10.0 further strengthens the company’s position in the physical implementation market.”
During the quarter, Mentor released a new version of its Catapult C synthesis tool enabling full chip synthesis, including control logic, and better power management. The company also released its PADS 9.0 printed circuit board flow which incorporated new collaboration, manufacturing and analysis tools.
At the Design Automation Conference (DAC) in July, Mentor advanced its full system low-power strategy by launching its VistaTM platform which enables engineers to model power early in the design cycle. Also at DAC, Mentor and its partners detailed the company’s multi-operating system, multi-core embedded system strategy featuring Linux, Android, and Nucleus operating systems.
Last Tuesday, the company closed its acquisition of LogicVision announced during the second quarter. The acquisition strengthens the company’s market-leading position in the design-for-test market by combining LogicVision’s strength in built-in-self-test (BIST) with the company’s strength in automated test pattern generation (ATPG) and embedded test pattern compression technology.
“With a tight rein on costs and the beginnings of an improving economic climate, the company performed better than we were confident to predict,” said Gregory K. Hinckley, president of Mentor Graphics. “The contract renewals we had in the quarter were at similar levels to their previous contract values, which was an improvement from the first quarter’s renewal rates. And despite acquisitions, headcount and operating expenses are down from a year ago, as the company continued to attack costs like travel, facilities and outside services.”
Outlook
For the third quarter fiscal 2010, the company expects revenue of about $183 million, non-GAAP earnings per share of about $.01 and a GAAP loss per share of about $.19.
Showing posts with label ESL. Show all posts
Showing posts with label ESL. Show all posts
Monday, August 24, 2009
Monday, July 20, 2009
Calypto enables ESL design, verification of complex designs
Design Automation Conference 2009, SANTA CLARA, USA: Enabling electronic system level (ESL) design flows for increasingly complex system on a chip (SOC) devices, Calypto Design Systems Inc. announced the release of SLEC 4.0, the latest version of its popular sequential logic equivalence checking (SLEC) product family.
SLEC is the semiconductor industry’s only comprehensive functional verification solution that formally verifies equivalence between ESL models and RTL implementations. The new version has up to five times the capacity of the previous version and provides tighter integration with the leading high-level synthesis (HLS) tools from Cadence Design Systems, Mentor Graphics, and Forte.
“HLS tools are becoming more efficient at handling larger functions. As a result, customers are applying HLS tools to design blocks with significant complexity, especially from a sequential perspective,” said Tom Sandoval, CEO of Calypto Design Systems.
“SLEC 4.0 keeps pace with the most sophisticated designs and provides an automated path to comprehensive verification with the industry’s only proven sequential equivalence checker. With SLEC, designers can avoid running time-consuming simulations and can uncover bugs that might otherwise go undetected and cause catastrophic delays to product development timelines.”
Calypto pioneered sequential logic equivalence checking when it announced its first version of SLEC nearly five years ago. Since that time, SLEC’s capacity has grown from thousand-gate blocks and tens of cycles of sequential complexity to hundreds of thousands of gates and thousands of cycles of sequential complexity.
The verification challenges have increased exponentially with these more sophisticated functions, making traditional simulation-based verification even less effective.
Optimized database and improved integration with HLS tools
Featuring algorithmic enhancements to Calypto’s patented word level solvers, the latest version of SLEC also includes dramatic improvement to SLEC’s proprietary database that results in a reduced memory footprint while SLEC is running. Together, these advancements enable the tool to handle larger, more complex designs.
As a result, designers can more freely use high level synthesis for the generation of highly complex functions, knowing that SLEC can provide comprehensive verification. The interface between SLEC and the leading HLS tools — Mentor Catapult, Cadence C-to-Silicon compiler, and Forte Cynthesizer — has also been improved in SLEC 4.0 to ensure an automated, efficient path to formal verification, requiring little or no user intervention.
Multiple clock support added
The ability to handle multiple clock designs has traditionally been a limitation with sequential logic equivalence checking. As SLEC capacity has increased, allowing the tool to support larger and more complex graphics, networking, multimedia, and wireless functions, the need to comprehensively verify designs with multiple clocks has become more and more prevalent.
With version 4.0, SLEC customers can now fully verify designs with multiple, independent clocks. For example, SLEC RTL can verify that the relationship between two clocks -- e.g., one clock is a multiple of another) is not disrupted by the manual introduction of sequential optimizations for power or performance by a designer. SLEC RTL can also now detect the illegal mixing of signals from different clock domains introduced by sequential transformations.
The SLEC family of products includes:
* SLEC System: Formally verifies equivalence of system-level models and RTL designs.
* SLEC System-HLS: Formally verifies that an RTL design generated using high-level synthesis is functionally equivalent to its corresponding system level model.
* SLEC RTL: Formally ensures functional equivalence between a golden RTL model and a corresponding RTL model has been sequentially modified to reduce power or improve performance.
* SLEC Pro: Comprehensively verifies that an RTL design generated by Calypto’s PowerPro product is functionally equivalent to its corresponding golden RTL model.
* SLEC 4.0 Showcased at 2009 DAC, Calypto to Present and Co-host Luncheon.
SLEC is the semiconductor industry’s only comprehensive functional verification solution that formally verifies equivalence between ESL models and RTL implementations. The new version has up to five times the capacity of the previous version and provides tighter integration with the leading high-level synthesis (HLS) tools from Cadence Design Systems, Mentor Graphics, and Forte.
“HLS tools are becoming more efficient at handling larger functions. As a result, customers are applying HLS tools to design blocks with significant complexity, especially from a sequential perspective,” said Tom Sandoval, CEO of Calypto Design Systems.
“SLEC 4.0 keeps pace with the most sophisticated designs and provides an automated path to comprehensive verification with the industry’s only proven sequential equivalence checker. With SLEC, designers can avoid running time-consuming simulations and can uncover bugs that might otherwise go undetected and cause catastrophic delays to product development timelines.”
Calypto pioneered sequential logic equivalence checking when it announced its first version of SLEC nearly five years ago. Since that time, SLEC’s capacity has grown from thousand-gate blocks and tens of cycles of sequential complexity to hundreds of thousands of gates and thousands of cycles of sequential complexity.
The verification challenges have increased exponentially with these more sophisticated functions, making traditional simulation-based verification even less effective.
Optimized database and improved integration with HLS tools
Featuring algorithmic enhancements to Calypto’s patented word level solvers, the latest version of SLEC also includes dramatic improvement to SLEC’s proprietary database that results in a reduced memory footprint while SLEC is running. Together, these advancements enable the tool to handle larger, more complex designs.
As a result, designers can more freely use high level synthesis for the generation of highly complex functions, knowing that SLEC can provide comprehensive verification. The interface between SLEC and the leading HLS tools — Mentor Catapult, Cadence C-to-Silicon compiler, and Forte Cynthesizer — has also been improved in SLEC 4.0 to ensure an automated, efficient path to formal verification, requiring little or no user intervention.
Multiple clock support added
The ability to handle multiple clock designs has traditionally been a limitation with sequential logic equivalence checking. As SLEC capacity has increased, allowing the tool to support larger and more complex graphics, networking, multimedia, and wireless functions, the need to comprehensively verify designs with multiple clocks has become more and more prevalent.
With version 4.0, SLEC customers can now fully verify designs with multiple, independent clocks. For example, SLEC RTL can verify that the relationship between two clocks -- e.g., one clock is a multiple of another) is not disrupted by the manual introduction of sequential optimizations for power or performance by a designer. SLEC RTL can also now detect the illegal mixing of signals from different clock domains introduced by sequential transformations.
The SLEC family of products includes:
* SLEC System: Formally verifies equivalence of system-level models and RTL designs.
* SLEC System-HLS: Formally verifies that an RTL design generated using high-level synthesis is functionally equivalent to its corresponding system level model.
* SLEC RTL: Formally ensures functional equivalence between a golden RTL model and a corresponding RTL model has been sequentially modified to reduce power or improve performance.
* SLEC Pro: Comprehensively verifies that an RTL design generated by Calypto’s PowerPro product is functionally equivalent to its corresponding golden RTL model.
* SLEC 4.0 Showcased at 2009 DAC, Calypto to Present and Co-host Luncheon.
Friday, June 12, 2009
Calypto delivers ‘picture perfect’ ESL solution to Casio
SANTA CLARA, USA: Demonstrating the widespread adoption of its popular SLEC System HLS (High Level Synthesis) tool, Calypto Design Systems, a leader in sequential analysis technology, announced that Casio will incorporate SLEC into its electronic system level (ESL) design flow for new digital camera designs.
Casio plans to pair Calypto’s formal verification tool with the Cadence Design Systems' C-to-Silicon Compiler to improve design efficiency and reduce time-to-tomarket for its digital cameras.
The combination of the Cadence and Calypto technologies allows engineers to work at a much higher level of abstraction, engaging in true ESL design. Using C-to-Silicon Compiler, Casio will automatically generate synthesizable register transfer level (RTL) code from SystemC code that can then be comprehensively verified by SLEC SystemHLS.
The automated ESL flow will allow Casio to run multiple “what if” scenarios and evaluate different design implementations to ensure that the final product delivers the best combination of cost and performance possible while ensuring functional correctness.
“Digital camera design has become increasingly sophisticated, and gate complexity is now 10 times what it was just three years ago,” said Kazuyuki Kurosawa, section manager of Digital Camera Product Unit, Casio. “Before implementing an automated unified ESL flow, we were forced to engage in time-consuming RTL hand coding and verification through RTL simulation regressions to generate and verify our design –– a process that consumed valuable engineering resources and limited our ability to innovate. By automating these two complex steps, Calypto and Cadence allow us to reduce design time and focus our resources on bringing true differentiation to our products.”
“There is an ongoing effort for design teams to find ways to increase productivity and achieve faster time-to-market,” said Tom Sandoval, CEO Calypto Design Systems. “Cadence C-to-Silicon Compiler and its integration with Calypto’s SLEC SystemHLS are proven to meet this demand, allowing designers to use their valuable design time for innovation, rather than tedious simulation and coding.”
Cadence's C-to-Silicon Compiler bridges the gap between RTL design and system-level models, usually written in C/C++ and SystemC. Fulfilling the industry requirement for formal equivalence checking, designers can then perform comprehensive functional verification using the Calypto SLEC System-HLS to formally verify equivalence between SystemC ESL models and RTL implementations.
By integrating their technologies, Cadence and Calypto deliver a fully automated system-level design solution that dramatically increases designer productivity.
“Our customers now have a best-in-class comprehensive solution for system level design and verification,” said Michael McNamara, vice president and general manager of the Systems Software Group at Cadence Design Systems. “The tight integration between Calypto’s SLEC SystemHLS and Cadence C-to-Silicon Compiler gives our customers an optimal flow that is rapidly becoming a standard approach for advanced SoC design.”
Casio plans to pair Calypto’s formal verification tool with the Cadence Design Systems' C-to-Silicon Compiler to improve design efficiency and reduce time-to-tomarket for its digital cameras.
The combination of the Cadence and Calypto technologies allows engineers to work at a much higher level of abstraction, engaging in true ESL design. Using C-to-Silicon Compiler, Casio will automatically generate synthesizable register transfer level (RTL) code from SystemC code that can then be comprehensively verified by SLEC SystemHLS.
The automated ESL flow will allow Casio to run multiple “what if” scenarios and evaluate different design implementations to ensure that the final product delivers the best combination of cost and performance possible while ensuring functional correctness.
“Digital camera design has become increasingly sophisticated, and gate complexity is now 10 times what it was just three years ago,” said Kazuyuki Kurosawa, section manager of Digital Camera Product Unit, Casio. “Before implementing an automated unified ESL flow, we were forced to engage in time-consuming RTL hand coding and verification through RTL simulation regressions to generate and verify our design –– a process that consumed valuable engineering resources and limited our ability to innovate. By automating these two complex steps, Calypto and Cadence allow us to reduce design time and focus our resources on bringing true differentiation to our products.”
“There is an ongoing effort for design teams to find ways to increase productivity and achieve faster time-to-market,” said Tom Sandoval, CEO Calypto Design Systems. “Cadence C-to-Silicon Compiler and its integration with Calypto’s SLEC SystemHLS are proven to meet this demand, allowing designers to use their valuable design time for innovation, rather than tedious simulation and coding.”
Cadence's C-to-Silicon Compiler bridges the gap between RTL design and system-level models, usually written in C/C++ and SystemC. Fulfilling the industry requirement for formal equivalence checking, designers can then perform comprehensive functional verification using the Calypto SLEC System-HLS to formally verify equivalence between SystemC ESL models and RTL implementations.
By integrating their technologies, Cadence and Calypto deliver a fully automated system-level design solution that dramatically increases designer productivity.
“Our customers now have a best-in-class comprehensive solution for system level design and verification,” said Michael McNamara, vice president and general manager of the Systems Software Group at Cadence Design Systems. “The tight integration between Calypto’s SLEC SystemHLS and Cadence C-to-Silicon Compiler gives our customers an optimal flow that is rapidly becoming a standard approach for advanced SoC design.”
Thursday, September 25, 2008
Mentor on EDA trends and solar/PV
This is a continuation of my recent discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.
There have been whispers that the EDA industry has been presently lagging behind semiconductors and is in the catch-up mode. "That’s a matter of perspective. There are definitely unsolved challenges at 32nm and 22nm, but the reality is that we are still in the technology development stage," he says.
For EDA tools that address implementation and manufacturing issues (i.e., Mentor design-to-silicon products), there are dependencies that cannot be fully resolved until the process technology has stabilized. Mentor Graphics is laying the groundwork for those challenges and working in concert with the process technology leaders to ensure that our products address all issues and are production-worthy before the process technology goes mainstream.
On the other hand, although Mentor’s products are fully-qualified for 45nm, there have only been a handful of tapeouts at that node, so for the majority of customers, we are ahead of the curve.
On ESL and DFM as growth drivers
ESL and DFM are said to be the new growth drivers. Sawicki adds: "As Wally Rhines has said in his public presentations, system level design and IC implementation are the stages of development where there are the most challenges, and therefore the most opportunities. To continue the traditional grow spiral that the electronic industry has enjoyed as a result of device scaling, we need more sophisticated EDA solutions to deal with both of these challenges."
ESL is responding to the growth of design complexity and the need for earlier and more thorough design verification, including low power characteristics, and software integration.
The Design-to-Silicon division is addressing the issues of IC implementation which result not only from the increase in design complexity and devices sizes, but also from increasing sensitivity of the manufacturing process to physical design decisions, a phenomenon often referred to as “manufacturing variability.”
Although the term “Design-For-Manufacturing” reflects the need to consider manufacturability in design and to optimize for both functional and parametric yield, it is important to emphasize that DFM is not simply an additional tool or discrete step in the design process, but rather an integration of manufacturing process information throughout the IC implementation flow.
With single threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out. It would be interesting to see how is Mentor handling this.
According to Sawicki, Mentor has incorporated sophisticated multi-threading and multi-processing technologies into all of its performance-sensitive applications, from place-and-route, through physical verification, resolution enhancement and testing.
He says, "Our tools have a track record of impressive and consistent and performance and scalability improvements, which is why we continue to lead the industry in performance."
In addition to merely adding multi-threading and support for multi-core processors, Calibre products have a robust workflow management environment that automatically distributes the processing workload in the most efficient manner across any number of available clustered computing nodes.
Mentor's Olympus-SoC place-and-route is inherently scalable due to its advanced architecture which includes an extremely efficient graph representation for timing information, and a very concise memory footprint. In addition, all the engines within Olympus-SoC can take advantage of multi-threaded and multi-core processors for high performance. These features enable Olympus-SoC to handle 100M+ gates designs in flat mode without excessive turnaround time.
Mentor’s ATPG tools are also designed to operate in multiprocessing mode over the multiple computing platforms to reduce test pattern generation time. In addition, Mentor test pattern compression technology reduces test pattern volume and test time, making it feasible to fully test 100M gate devices and maintain product quality without an explosion in test cost.
With EDA is starting to move up to the system level, will this make EDA less dependent on the semiconductor world?
Sawicki agrees that there are challenges at both the front end and back end of the electronic products design and manufacturing life cycle. Both of these opportunities are growing. In addition, developments like multi-level (3D) die packaging, through-silicon via (TSV) structures and other non-traditional techniques for device scaling are pushing system and silicon design issues closer together.
Reaching the 22nm node will require highly compute intensive EDA techniques for physical design to compensate for limitations in the manufacturing process. Beyond that, we could see a major shift to new materials and manufacturing techniques that would open new green fields for EDA in the IC implementation flow.
EDA going forward
How does Mentor see the EDA industry evolving, going forward?
Sawicki adds: "There are three key trends to watch. Firstly, for design to remain affordable at the leading edge, we need to enable radical increases in productivity. Electronic System Level (ESL) design is the key here, allowing designers to move to a new level of abstraction for both design and verification.
"Secondly, the challenges of manufacturing a well-yielding and reliable device as we move to 22nm will require a far more sophisticated physical implementation environment—one that accounts for physical effects in the design loop, and accounts for manufacturing variability in it's optimization routines.
"Finally, the manufacturing challenges also open significant opportunity for EDA in the manufacturing space. A great example of this is the September 17, 2008 announcement we did with IBM on a joint development program to enable manufacturing at the 22nm node."
Finally, given the roles already defined by Magma and Synopsys in solar, is there an opportunity for EDA in solar/PV?
According to Sawicki, as the photovoltaic devices have very simple and regular structures, most of the opportunity for EDA is not in logic design tools, but in material science, transistor-level device modeling, and manufacturing efficiencies with a focus on conversion efficiency and manufacturing cost reduction.
EDA's role in solar will be in the newer areas related to Design-for-Manufacturing and other manufacturing optimizations, he concludes.
Our last discussion on DFM will follow in a later blog post!
There have been whispers that the EDA industry has been presently lagging behind semiconductors and is in the catch-up mode. "That’s a matter of perspective. There are definitely unsolved challenges at 32nm and 22nm, but the reality is that we are still in the technology development stage," he says.
For EDA tools that address implementation and manufacturing issues (i.e., Mentor design-to-silicon products), there are dependencies that cannot be fully resolved until the process technology has stabilized. Mentor Graphics is laying the groundwork for those challenges and working in concert with the process technology leaders to ensure that our products address all issues and are production-worthy before the process technology goes mainstream.
On the other hand, although Mentor’s products are fully-qualified for 45nm, there have only been a handful of tapeouts at that node, so for the majority of customers, we are ahead of the curve.
On ESL and DFM as growth drivers
ESL and DFM are said to be the new growth drivers. Sawicki adds: "As Wally Rhines has said in his public presentations, system level design and IC implementation are the stages of development where there are the most challenges, and therefore the most opportunities. To continue the traditional grow spiral that the electronic industry has enjoyed as a result of device scaling, we need more sophisticated EDA solutions to deal with both of these challenges."
ESL is responding to the growth of design complexity and the need for earlier and more thorough design verification, including low power characteristics, and software integration.
The Design-to-Silicon division is addressing the issues of IC implementation which result not only from the increase in design complexity and devices sizes, but also from increasing sensitivity of the manufacturing process to physical design decisions, a phenomenon often referred to as “manufacturing variability.”
Although the term “Design-For-Manufacturing” reflects the need to consider manufacturability in design and to optimize for both functional and parametric yield, it is important to emphasize that DFM is not simply an additional tool or discrete step in the design process, but rather an integration of manufacturing process information throughout the IC implementation flow.
With single threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out. It would be interesting to see how is Mentor handling this.
According to Sawicki, Mentor has incorporated sophisticated multi-threading and multi-processing technologies into all of its performance-sensitive applications, from place-and-route, through physical verification, resolution enhancement and testing.
He says, "Our tools have a track record of impressive and consistent and performance and scalability improvements, which is why we continue to lead the industry in performance."
In addition to merely adding multi-threading and support for multi-core processors, Calibre products have a robust workflow management environment that automatically distributes the processing workload in the most efficient manner across any number of available clustered computing nodes.
Mentor's Olympus-SoC place-and-route is inherently scalable due to its advanced architecture which includes an extremely efficient graph representation for timing information, and a very concise memory footprint. In addition, all the engines within Olympus-SoC can take advantage of multi-threaded and multi-core processors for high performance. These features enable Olympus-SoC to handle 100M+ gates designs in flat mode without excessive turnaround time.
Mentor’s ATPG tools are also designed to operate in multiprocessing mode over the multiple computing platforms to reduce test pattern generation time. In addition, Mentor test pattern compression technology reduces test pattern volume and test time, making it feasible to fully test 100M gate devices and maintain product quality without an explosion in test cost.
With EDA is starting to move up to the system level, will this make EDA less dependent on the semiconductor world?
Sawicki agrees that there are challenges at both the front end and back end of the electronic products design and manufacturing life cycle. Both of these opportunities are growing. In addition, developments like multi-level (3D) die packaging, through-silicon via (TSV) structures and other non-traditional techniques for device scaling are pushing system and silicon design issues closer together.
Reaching the 22nm node will require highly compute intensive EDA techniques for physical design to compensate for limitations in the manufacturing process. Beyond that, we could see a major shift to new materials and manufacturing techniques that would open new green fields for EDA in the IC implementation flow.
EDA going forward
How does Mentor see the EDA industry evolving, going forward?
Sawicki adds: "There are three key trends to watch. Firstly, for design to remain affordable at the leading edge, we need to enable radical increases in productivity. Electronic System Level (ESL) design is the key here, allowing designers to move to a new level of abstraction for both design and verification.
"Secondly, the challenges of manufacturing a well-yielding and reliable device as we move to 22nm will require a far more sophisticated physical implementation environment—one that accounts for physical effects in the design loop, and accounts for manufacturing variability in it's optimization routines.
"Finally, the manufacturing challenges also open significant opportunity for EDA in the manufacturing space. A great example of this is the September 17, 2008 announcement we did with IBM on a joint development program to enable manufacturing at the 22nm node."
Finally, given the roles already defined by Magma and Synopsys in solar, is there an opportunity for EDA in solar/PV?
According to Sawicki, as the photovoltaic devices have very simple and regular structures, most of the opportunity for EDA is not in logic design tools, but in material science, transistor-level device modeling, and manufacturing efficiencies with a focus on conversion efficiency and manufacturing cost reduction.
EDA's role in solar will be in the newer areas related to Design-for-Manufacturing and other manufacturing optimizations, he concludes.
Our last discussion on DFM will follow in a later blog post!
Monday, September 22, 2008
Despite EDA challenges, Mentor keeps faith on India
Great! All of these EDA firms, despite their current financial woes, remain strong and bullish on India! Mentor Graphics is no exception in this case!
It is well documented that the global EDA industry, along with the global semiconductor industry, has not had a smooth ride this year. However, this situation has only made both the industries work harder toward restoring some recovery.
Thanks to Veeresh Shetty, a dear friend, and Marcom Manager-Pacrim South, Mentor Graphics, I had the pleasure of meeting up with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics Corp., during the recently held EDA Tech Forum in Bangalore.
We discussed a range of issues, such as the state of the EDA industry, Mentor's focus on India, and low-power design challenges. I did not discuss the proposed acquisition of Mentor by Cadence, as I feel it is no point in going over what was never on the cards, at least, for now.
According to Sawicki, Mentor Graphics is very optimistic about semiconductors and electronics, especially in India. "The EDA industry is currently having a pretty challenging environment. The recession in 2002 was the deepest in its history," he says.
"We (the EDA industry) haven't had the growth rates we would like. However, we have done better. We have re-invented Mentor," adds Sawicki. "We have now invested more in back-and-route ICs, which is about 40 percent of our revenue. Our product portfolio is the youngest within the company." He adds that the recession has been more in semiconductors. However, take out memory, and the scenario changes.
The drive of the semiconductor industry toward smaller and smaller features sizes requires more sophisticated correction methods to guarantee the final tolerances for the etched features in both wafer manufacturing and mask making.
Flat growth likely for EDA
Commenting on EDA industry's growth, Sawicki, adds that growth will be flat in 2008. Interestingly, the growth rate for EDA was 10 percent during the last two years. He notes: "EDA always does best when it delivers new technology. There are two reasons. One, on the manufacturing side of things. The extra results will be completely delivered by the software."
The other reason is that the aspects of manufacturing power and manageability will assume great importance. "Finally, the ESL space also provides the potential for growth. It also brings out a whole new design capability," he notes.
Given the global semiconductor scenario, Mentor is also looking at other markets outside semiconductors, especially automotive. Sawicki adds that this quarter, 20 percent of Mentor's business has been from the automotive segment.
There have been several global initiatives aimed at consolidation in the recent past. Sawicki says: "Consolidation should not be looked at as a goal. We also do acquisitions in the technology space. It augments a strong position."
So what are some of the other challenges facing the industry? Sawicki lists those as the economics of the industry itself, especially the design and verification costs.
On low power design, Sawicki agrees that there has been a transition of electronics from the US to Asia. "You have got to handle far lower power downward. We can reduce leakage current by 20-30 percent. Looking forward, how do you tie in ESL with physical design? When doing ESL, you can do architectural exploration. I will have my ESL to drive the place-and-route tool. I can get fast execution as well as low leakage power."
He advises that India has the ability to go beyond the innovation that has been happening.
Mentor in India
Mentor Graphics has three sites in India. It has R&D centers in Hyderabad and Noida, near New Delhi, and a sales and support office in Bangalore. The Hyderabad R&D center handles system design, while the Noida R&D center takes care of the front-end side, such as functional verification products.
Raghu Panicker, sales director, India, Mentor Graphics, says that the company has been very bullish on India. "We do not see any lull anywhere. Lot of design starts are happening here, in India," he adds.
I will continue my conversation with Joseph Sawicki in the next blog!
It is well documented that the global EDA industry, along with the global semiconductor industry, has not had a smooth ride this year. However, this situation has only made both the industries work harder toward restoring some recovery.
Thanks to Veeresh Shetty, a dear friend, and Marcom Manager-Pacrim South, Mentor Graphics, I had the pleasure of meeting up with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics Corp., during the recently held EDA Tech Forum in Bangalore.We discussed a range of issues, such as the state of the EDA industry, Mentor's focus on India, and low-power design challenges. I did not discuss the proposed acquisition of Mentor by Cadence, as I feel it is no point in going over what was never on the cards, at least, for now.
According to Sawicki, Mentor Graphics is very optimistic about semiconductors and electronics, especially in India. "The EDA industry is currently having a pretty challenging environment. The recession in 2002 was the deepest in its history," he says.
"We (the EDA industry) haven't had the growth rates we would like. However, we have done better. We have re-invented Mentor," adds Sawicki. "We have now invested more in back-and-route ICs, which is about 40 percent of our revenue. Our product portfolio is the youngest within the company." He adds that the recession has been more in semiconductors. However, take out memory, and the scenario changes.
The drive of the semiconductor industry toward smaller and smaller features sizes requires more sophisticated correction methods to guarantee the final tolerances for the etched features in both wafer manufacturing and mask making.
Flat growth likely for EDA
Commenting on EDA industry's growth, Sawicki, adds that growth will be flat in 2008. Interestingly, the growth rate for EDA was 10 percent during the last two years. He notes: "EDA always does best when it delivers new technology. There are two reasons. One, on the manufacturing side of things. The extra results will be completely delivered by the software."
The other reason is that the aspects of manufacturing power and manageability will assume great importance. "Finally, the ESL space also provides the potential for growth. It also brings out a whole new design capability," he notes.
Given the global semiconductor scenario, Mentor is also looking at other markets outside semiconductors, especially automotive. Sawicki adds that this quarter, 20 percent of Mentor's business has been from the automotive segment.
There have been several global initiatives aimed at consolidation in the recent past. Sawicki says: "Consolidation should not be looked at as a goal. We also do acquisitions in the technology space. It augments a strong position."
So what are some of the other challenges facing the industry? Sawicki lists those as the economics of the industry itself, especially the design and verification costs.
On low power design, Sawicki agrees that there has been a transition of electronics from the US to Asia. "You have got to handle far lower power downward. We can reduce leakage current by 20-30 percent. Looking forward, how do you tie in ESL with physical design? When doing ESL, you can do architectural exploration. I will have my ESL to drive the place-and-route tool. I can get fast execution as well as low leakage power."
He advises that India has the ability to go beyond the innovation that has been happening.
Mentor in India
Mentor Graphics has three sites in India. It has R&D centers in Hyderabad and Noida, near New Delhi, and a sales and support office in Bangalore. The Hyderabad R&D center handles system design, while the Noida R&D center takes care of the front-end side, such as functional verification products.
Raghu Panicker, sales director, India, Mentor Graphics, says that the company has been very bullish on India. "We do not see any lull anywhere. Lot of design starts are happening here, in India," he adds.
I will continue my conversation with Joseph Sawicki in the next blog!
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