Synopsys, Mentor, CoWare join ARM Fast Models Enablement Program

CAMBRIDGE, UK: ARM announced at DAC, San Francisco, that CoWare, Mentor Graphics and Synopsys Inc. have joined the ARM Fast Models Enablement Program.

Members of the Program are able to integrate fully validated Fast Models from ARM, for a range of ARM processors, into their virtual platform environments and deliver to their customers.

This ensures that mutual customers can create complete ARM Powered virtual platforms using the design flow of their choice. By using virtual platforms built around ARM processor Fast Models, engineers can develop software well in advance of final hardware implementation, with application and driver software running at near to real-time system performance.

The Fast Models product family from ARM includes programmer's view (PV) models for the ARM9, ARM11 and Cortex families of processors, including the Cortex-A9 MPCore multicore processor. The Fast Model products also include configuration tools that enable the export of ARM processor-based subsystems with OSCI SystemC and TLM-2.0 compliant interfaces.

"We are seeing a growing demand for high-performance models in the industry," said John Cornish, EVP and general manager, System Design Division, ARM. "The TLM-2.0 interface enables our customers to combine our processor Fast Models with models of their other IP to create complete virtual platforms in the design environment of their choice."

"CoWare has successfully delivered Electronic System Virtualization solutions for ARM processor-based designs for many years supporting architecture design, verification, software development, integration and test. With our further engagement in this broader program covering the ARM Cortex Fast Models, we continue to expand this position to serve the growing needs of our joint customers," said Marc Serughetti, vice president of Marketing and Business Development at CoWare Inc.

"This integration and partnership is already proven and in use at several customers resulting in significant time-to-market benefits for those customers."

"Mentor’s Vista technology offers a comprehensive architecture design and prototyping solution that relies on fast processor and peripheral models as an essential part of the solution. The integration of the architecturally accurate ARM Fast Models into our Vista Platform will deliver significant value to our mutual customers," said Simon Bloch, Mentor Graphics vice president and general manager, design and synthesis division.

"In addition, ARM’s Fast Models are compatible with Vista’s TLM scalable modeling methodology that provides the timing and power layers essential for optimizing performance and power at the transaction level of abstraction."

"As a leading IP provider, Synopsys already provides OSCI TLM-2.0 compliant transaction-level models for several processor families including ARM and Synopsys DesignWare Cores and components for SoC infrastructure, AMBA interconnect, CoreConnect and PrimeCell peripherals in the Synopsys DesignWare System-level Library," said Frank Schirrmeister, director product marketing for the Solutions Group at Synopsys.

"The ARM PV Enablement Program allows our users to draw from a larger number of models and enables Synopsys to validate interoperability of Synopsys’ Innovator development environment for virtual platforms with ARM processor-based subsystems using Fast Models from ARM."

Availability
Fast Models Version 5.0 including the SystemC/TLM-2.0 compatible export capability is available for immediate licensing from ARM. 45-day evaluations are available through the Program members in concert with their respective integrated solutions through the PV Enablement Program.

NXP deploys integrated CoWare and ARM Cortex processor-based solution in VPE

SAN JOSE, USA & CAMBRIDGE, UK: CoWare, Inc., the leading supplier of Electronic System Virtualization™ software and services, and ARM, announced that NXP has successfully deployed their joint software development solution, integrating Fast Models from ARM for Cortex™ processors™ in CoWare’s Virtual Platform technology.

NXP uses the joint ARM-CoWare offering in their own SystemC based Virtual Prototyping Environment (VPE). The software development solution is enabling NXP to reduce development costs, improve software developer productivity and achieve faster time-to-market.

VPE is NXP’s internal development environment utilizing the virtualized representation of an electronic system. It removes the dependency on the availability of expensive hardware prototypes and development test benches and provides cost-effective software development capabilities for debugging and analysis.

NXP’s VPE is based on CoWare’s technology. Using their VPE with the ARM® Cortex-A9 processor-based Fast Model, NXP ported Linux in record time, ahead of RTL availability and faster than with traditional emulation based development methods. Support by CoWare’s services organization combined with key VPE features enabled this productivity boost. Key VPE features include:

* Enhanced debug visibility combining CoWare Virtual Platform Analyzer with a software debugger.
* Reproducibility and predictability through full scripting environment.
* High-speed simulation performance for the Cortex-A9 subsystem, including higher performance than traditional emulation methods.
* Ease of deployment across multiple engineering sites around the world.

“NXP is a world leader in developing advanced digital products -- from portable media players, TVs and set-top boxes, to identification applications, cars and a wide range of other electronic devices,” said Barry Dennington, Senior Vice President, CIT Design and Flows, NXP Semiconductors.

“The co-operation between ARM and CoWare to enable VPEs for software development on Cortex processor-based designs made it possible for us to significantly save on the software development and validation effort for our next-generation consumer device, thus reducing cost while at the same time accelerating the time-to-market of the device.”

“ARM is dedicated to enabling developers to get the most out of their ARM processor-based designs,” said John Cornish, Executive Vice President and General Manager of ARM, System Design Division. “In a close collaboration with CoWare, we have been able to combine the value of the Virtual Platform technology and Fast Models enabling NXP to distribute fast, trusted, and reliable virtual prototypes for software development.”

“Last year, NXP successfully established its powerful VPE environment based on CoWare technology and deployed it company wide for the development of its leading designs,” said Marc Serughetti, Vice President, Marketing and Business Development, CoWare.

“The tight partnership between CoWare and ARM, through the integration of the Fast Models for the ARM Cortex processors in CoWare Virtual Platform combined with expert support, has provided NXP with quantifiable results showing the benefits of electronic system virtualization.”

CoWare, EVE link electronic system virtualization, emulation for ARM AXI-based systems

SAN JOSE, USA: CoWare, the leading supplier of Electronic System Virtualization software and services, and EVE, a leader in hardware/software co-verification, announced the first fully-integrated, high-performance solution combining virtualization and emulation to enable pre-silicon software development and hardware/software co-verification for multicore ARM AXI-based system-on-chip (SoC) designs.

CoWare Virtual Platform and EVE’s ZeBu (for zero bugs) emulation uses CoWare’s fast untimed emulation adapters and EVE’s Synthesizable AXI Transactors. This bridges the gap between the virtualized, transaction-level representation of the system for software development and the register transfer level (RTL) implementation of subsystem hardware in emulation.

The hybrid, off-the-shelf solution enables fast and efficient development of hardware-dependent software and hardware/software co-verification ahead of first silicon. By enabling transaction-based communication of RTL design blocks with an electronic system level (ESL) environment at 100,000s transactions/second, it accelerates the development cycle for SoC designs while increasing verification productivity.

“With the challenges of multicore system design, software developers must start their work earlier with efficient debugging and analysis capabilities adapted to multicore platforms,” remarks Patrick Sheridan, CoWare’s marketing director. “This joint solution enables exactly that by allowing CoWare Virtual Platforms to be created sooner by leveraging AXI application subsystem RTL in emulation, while still providing the debug visibility and simulation speed they need for the entire system.”

“When designing new application subsystems or integrating existing subsystems into SoC architectures, it is critical to perform hardware/software co-verification and pre-silicon software validation as early as possible,” adds Lauro Rizzatti, general manager of EVE USA.

“The off-the-shelf integration of our Synthesizable AXI Transactors for ZeBu with the CoWare Virtual Platform environment enables this work to start before the entire system RTL code is available, while reusing the software-driven tests developed with the virtual platform.”

CoWare reduces design cost for complex ARM AMBA platform optimization

SAN JOSE, USA: CoWare Inc., a leading supplier of Electronic System Virtualization software and services, announced the availability of a new Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect, enabling early and efficient optimization of next-generation SoC architectures using ARM AMBA-based virtual platforms.

CoWare virtual platforms for architecture design are the virtualized representation of an electronic system used for the purpose of system-level performance analysis and architecture optimization.

The new flow provides system architects with the ability to efficiently capture the dynamic performance workloads of each application subsystem of a multi-function SoC in the form of transaction traffic, months before software is available and with minimum modeling effort using a well-defined, repeatable methodology.

CoWare is the leading global supplier of electronic system virtualization solutions for software development, platform architecture design and platform verification of ARM-based platforms. CoWare combines ARM instruction-accurate processor models and implementation-accurate Carbonized ARM models within one standards-based SystemC design environment.

The CoWare solutions enable engineers to take full advantage of the capabilities of the entire range of ARM system elements in the context of the actual design; from ARM memory controllers and interconnects to application and embedded processors and embedded firmware.

“CoWare has been the leader in electronic system virtualization solutions for ARM technology-based platforms for more than 10 years now,” said Johannes Stahl, vice president of marketing and business development at CoWare. “This new flow captures the production-proven design methods successfully deployed by CoWare customers to analyze and improve next-generation system performance and cost sooner by using transaction traffic generation, while retaining full support in the same environment for the HW-SW performance validation of early architectural decisions using cycle-accurate processor models and software, as they become available throughout the development process.”

CoWare capabilities
The new Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect is enabled by CoWare’s advanced system-level design features, including:

* Trace- and task-driven generation of transaction traffic, enabling creation of performance workload models reflecting the application performance workloads of the multi-function use-cases for interconnect and memory subsystem analysis;

* Integrated graphical environment for transaction tracing and statistical port analysis enabling platform model validation and system-level performance measurement of transaction count, transaction throughput, and transaction latency;

* Support for simulation and analysis of multiple TLM protocols at mixed levels of abstraction, including TLM-2.0 and cycle-accurate AHB, APB, and AXI communication protocols, and user-defined data collection based on SCV transaction recording;

* Scripting support for simulation sweeping of traffic scenarios and IP parameters across multiple simulations enabling design space exploration, sensitivity analysis using spreadsheets, and root cause analysis;

* CoStart services for rapid end-user ramp-up with AXI-based designs.

CoWare Platform Architect tool and IP model enhancements and CoWare CoStart services are available immediately for use with the 2009.1.1 release.