SAN JOSE, USA: CoWare, the leading supplier of Electronic System Virtualization software and services, and EVE, a leader in hardware/software co-verification, announced the first fully-integrated, high-performance solution combining virtualization and emulation to enable pre-silicon software development and hardware/software co-verification for multicore ARM AXI-based system-on-chip (SoC) designs.
CoWare Virtual Platform and EVE’s ZeBu (for zero bugs) emulation uses CoWare’s fast untimed emulation adapters and EVE’s Synthesizable AXI Transactors. This bridges the gap between the virtualized, transaction-level representation of the system for software development and the register transfer level (RTL) implementation of subsystem hardware in emulation.
The hybrid, off-the-shelf solution enables fast and efficient development of hardware-dependent software and hardware/software co-verification ahead of first silicon. By enabling transaction-based communication of RTL design blocks with an electronic system level (ESL) environment at 100,000s transactions/second, it accelerates the development cycle for SoC designs while increasing verification productivity.
“With the challenges of multicore system design, software developers must start their work earlier with efficient debugging and analysis capabilities adapted to multicore platforms,” remarks Patrick Sheridan, CoWare’s marketing director. “This joint solution enables exactly that by allowing CoWare Virtual Platforms to be created sooner by leveraging AXI application subsystem RTL in emulation, while still providing the debug visibility and simulation speed they need for the entire system.”
“When designing new application subsystems or integrating existing subsystems into SoC architectures, it is critical to perform hardware/software co-verification and pre-silicon software validation as early as possible,” adds Lauro Rizzatti, general manager of EVE USA.
“The off-the-shelf integration of our Synthesizable AXI Transactors for ZeBu with the CoWare Virtual Platform environment enables this work to start before the entire system RTL code is available, while reusing the software-driven tests developed with the virtual platform.”
Showing posts with label emulation platform. Show all posts
Showing posts with label emulation platform. Show all posts
Sunday, June 21, 2009
Wednesday, May 6, 2009
EVE integrates Xilinx ISE Design Suite into emulation platforms
SAN JOSE, USA: EVE, the leader in hardware/software co-verification, today announced that it has integrated the latest version of the Xilinx's ISE Design Suite to its ZeBu (for Zero Bugs) emulation platforms.
Working in close partnership with Xilinx over several months, EVE’s R&D team tested the ISE Design Suite 11.1 on large system-on-chip (SoC) and application specific integrated circuit (ASIC) designs. The team used designs of several billion transistors that required hundreds of interconnected Virtex devices to ensure a high degree of success when placing and routing high-density Xilinx field programmable gate arrays (FPGAs).
Notes Ludovic Larzul, EVE’s vice president of engineering: “The integration of ISE Design Suite 11 into the ZeBu compiler significantly accelerates long compilation runs. We are seeing runtime drop by as much as 2X, allowing more turns per day. This is a huge feat since design teams worldwide use ZeBu to compile thousands of Virtex FPGAs everyday.”
“The relationship developed between EVE and Xilinx to advance the compilation capabilities of ISE Design Suite 11 could be a case book study on how companies can work together on problem solving,” says Tom Feist, senior marketing director for ISE Design Suite at Xilinx. “We are pleased with the results achieved and appreciate the contributions brought to us by EVE’s R&D team.”
The ZeBu emulation platforms are used for SoC hardware verification and software development, to shorten time to tapeout, improve product quality and eliminate costly respins, while accelerating software development ahead of silicon. They leverage the same hardware, design models and engineering resources across the entire design cycle, making it cost effective for every design team.
Working in close partnership with Xilinx over several months, EVE’s R&D team tested the ISE Design Suite 11.1 on large system-on-chip (SoC) and application specific integrated circuit (ASIC) designs. The team used designs of several billion transistors that required hundreds of interconnected Virtex devices to ensure a high degree of success when placing and routing high-density Xilinx field programmable gate arrays (FPGAs).
Notes Ludovic Larzul, EVE’s vice president of engineering: “The integration of ISE Design Suite 11 into the ZeBu compiler significantly accelerates long compilation runs. We are seeing runtime drop by as much as 2X, allowing more turns per day. This is a huge feat since design teams worldwide use ZeBu to compile thousands of Virtex FPGAs everyday.”
“The relationship developed between EVE and Xilinx to advance the compilation capabilities of ISE Design Suite 11 could be a case book study on how companies can work together on problem solving,” says Tom Feist, senior marketing director for ISE Design Suite at Xilinx. “We are pleased with the results achieved and appreciate the contributions brought to us by EVE’s R&D team.”
The ZeBu emulation platforms are used for SoC hardware verification and software development, to shorten time to tapeout, improve product quality and eliminate costly respins, while accelerating software development ahead of silicon. They leverage the same hardware, design models and engineering resources across the entire design cycle, making it cost effective for every design team.
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