Applied Materials awarded key service contract by Fujitsu Microelectronics

SANTA CLARA, USA: Applied Materials, Inc. today announced that it has been awarded an integrated service contract by Fujitsu Microelectronics Ltd. to support its advanced 300mm semiconductor factory in Mie, Japan.

Under the program, Applied will service over 100 Applied chipmaking systems utilizing its innovative Applied Performance Service solution that scales service levels to match factory loading.

In addition, Applied will implement its Applied E3 advanced equipment and process control technology on Fujitsu Microelectronics Mie plant’s entire toolset to increase the efficiency, predictability and profitability of Fujitsu Microelectronics’ system-on-chip (SoC) manufacturing process.

“The SoC market requires a high degree of application-specific customization, resulting in a constantly changing product mix. Maintaining tight process control on every wafer is critical to profitability,” said Kiyoshi Watanabe, corporate vice president, Fujitsu Microelectronics Ltd.

“The Applied Performance Service Program paces service and price to actual utilization rates to provide us with committed uptime performance at a low, predictable cost that tracks factory loading.”

The uniquely flexible Applied Performance Service program can reduce maintenance costs by an average of 15 percent, making it a particularly powerful strategy for chipmakers producing SoC and other cost-sensitive logic devices, especially in times of rapidly changing demand.

Using proprietary fingerprinting algorithms, the Applied E3 solution further raises cost-efficiency by optimizing and tracking the process performance of every tool in the fab.

The E3 system’s fault detection and classification (FDC) technology provides rapid feedback on tool, wafer and lot performance to avoid unexpected excursions that impact productivity and cycle time, while run-to-run control (R2R) adjusts processing parameters in real time to enable more consistent output and higher device yields.

“Applied’s high-tech service approach is a perfect match for a sophisticated and agile fab such as Fujitsu Microelectronics’ Mie plant,” said Charlie Pappis, vice president and general manager of Applied Global Services. “By combining variable service with equipment and process automation, customers can reduce costs and take advantage of the unused potential of their existing assets. The growing momentum of our service business in Asia is a testament to Applied’s unique ability to provide innovative support solutions.”

Fujitsu launches multimode, multiband RF transceiver IC

BANGALORE, INDIA: Fujitsu Microelectronics Asia Pte Ltd (FMAL) today announced the first product in its entry into the mobile phone RF transceiver market, in launching a RF transceiver IC for mobile phones supporting 2G GSM/GPS/EDGE and 3G UMTS/HSPA protocols, that includes a 3G DigRF interface on a single chip.

The compact new transceiver IC also eliminates the need for external SAW filters, and low-noise amplifiers (LNA) and enables mobile phone manufacturers to reduce component count, board space and bill of materials.

While a simplified programming model helps to significantly reduce development time and simplify integration of the RF into a radio platform. Samples of the MB86L01A transceiver IC are available from today.

In today’s global mobile phone markets there are increasing needs for multimode support for the various 2G and 3G communications protocols in use, as well as multiband support for the various frequency bands used in different regions, and allotted to different carriers.

Mobile phone manufacturers are faced with trying to supply not only the multitude of combinations of these modes and frequencies, but also have to deal with the demands of ever-shortening product lifecycles and smaller form-factors. This new MB86L01A RF transceiver IC is designed to help mobile phone manufacturers meet these demands.

The new RF transceiver IC supports all frequency bands for 2G protocols of GSM/GPRS/EDGE, as well as supporting a maximum of four bands simultaneously within the 10 frequency bands of the 3G protocols -- UMTS/HSPA.

The MB86L01A transceiver also embeds LNAs on-chip, so external LNAs are not required as they were previously. Also, an architecture is employed that eliminates the need for external SAW filters, thus reducing total component count. Enclosed in a small form-factor 142-pin LGA package of 7.1x5.9mm, the reduced space of the RF system helps realize smaller form-factor mobile phones.

Fujitsu's USB 3.0 SATA bridge IC for PC peripherals

BANGALORE, INDIA: Fujitsu Microelectronics Asia Pte Ltd (FMAL) announced the new USB 3.0 - SATA bridge ICs, built with Fujitsu’s leading-edge proprietary physical layer device (PHY).

It supports SuperSpeed USB, the USB 3.0 specification, and enables data transfer rates of 5Gbps maximum between external storage devices –- such as hard disk drives (HDDs) -- and PCs.

The new IC, MB86C30A, is the first in the MB86C30 Series of USB 3.0-SATA bridge ICs, and when embedded in PC peripheral devices, enables over 10-fold faster data transfer rates in comparison to the USB 2.0 specification.

In addition to the bridge functionality, the new IC also features a high-speed data encryption/decryption engine, offering high security without impairing the high-speed performance of USB 3.0. Samples of the new MB86C30A IC are available from July 27, 2009.

Today, PCs and digital audio-visual equipment handle an ever-growing volume of data such as digital photos, audio and video files. These market needs are driving storage devices, such as hard disk drives, to have ever-increasing data volumes and speeds.

The ubiquitous USB interface, used widely in external hard drives and USB memory sticks, has had a slow maximum data transfer rate of 480Mbps under the USB 2.0 specification, too slow to meet current strong demand for the ability to read and write high volumes of data in shorter time.

The USB 3.0 specification (SuperSpeed USB) ratified in November 2008 resolves this issue by providing a maximum data transfer rate that is over 10 times faster than that of USB 2.0. In addition, this revolutionary next-generation specification includes greater protocol efficiency as well as improved power management techniques, which enable lower power consumption.

As this IC series enables 5Gbps high-speed data transfer between the PC and external HDDs, for the case of 3.5-HDDs, copying two hours worth of full high-vision video can be reduced from 12 minutes to approximately 3 minutes 30 seconds to 4 minutes in comparison to USB 2.0

The MB86C30A IC also contains an embedded AES (*4) encryption engine that makes it possible to store encrypted data on HDDs, thus protecting confidential information from threats when portable devices are lost or stolen –- a well-publicized problem in recent years -- or to prevent data leaks when storage devices are disposed of.

In addition, compared to software encryption, this hardware encryption does not burden the CPU of the host PC while providing more secure protection of user’s data.

This series of ICs is being co-developed with Fujitsu Laboratories Limited, utilizing their high-speed serial interface technologies, and Fujitsu LSI Solution Ltd. Going forward, Fujitsu Microelectronics will strengthen and expand its line-up of USB3.0-standard bridge IC products.

Synopsys' Eclypse enables Fujitsu to cut design cycle by 30 percent

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Fujitsu Microelectronics Ltd (FML) has deployed Synopsys' Galaxy Implementation Platform, for use with its low power digital electronics and mobile application ICs.

Fujitsu Microelectronics engineers used IEEE 1801 (UPF) to describe the power intent and drive the design, static verification and sign-off of several low power designs.

Utilizing the best-in-class optimization engines and complete low power capabilities in the Galaxy Implementation Platform, Fujitsu Microelectronics' designers were able to cut the traditional RTL-to-GDSII design cycle by 30 percent while meeting all design goals. Fujitsu Microelectronics is now ready to deploy this flow with their customers on 90 nanometer (nm), 65nm and 40nm digital consumer electronics designs.

"Deploying advanced power management techniques within very tight design schedules is among the key challenges for us and our customers," said Noboru Yokota, general manager of the Technology Development Division, Common IP and Technology Development Unit, Fujitsu Microelectronics. "With Synopsys' UPF-enabled Eclypse Low Power Solution, we met our stringent power, speed and area goals while saving 30 percent of the overall traditional design cycle. We are looking forward to helping our customers deploy this flow and get more competitive low power designs to market, faster."

Part of Synopsys' Eclypse Low Power Solution, the Galaxy Implementation Platform delivers the lowest power consumption, highest design performance and highest productivity through a complete low-power design portfolio.

DC Ultra synthesis and IC Compiler physical implementation automate the most advanced low-power techniques, such as multi-voltage and MTCMOS power gating, as well as more commonly used techniques such as clock gating and multi-threshold libraries. In addition, they perform comprehensive dynamic and leakage power optimization throughout the RTL-to-GDSII implementation, while concurrently optimizing timing, area, testability, congestion and other design goals.

The UPF-enabled implementation solution also includes PrimeTime PX accurate power analysis, PrimeTime SI noise analysis for sign-off, MVRC voltage-aware static checking and Formality power aware equivalence checking.

"Chip designers today need to meet stringent power specs within very tight schedules to be competitive in the marketplace, and the advanced low power capabilities in the Galaxy Implementation Platform are driving their success," said Bijan Kiani, vice president of Product Marketing at Synopsys. "Fujitsu Microelectronics has seen significant productivity gains with Synopsys' UPF enabled implementation flow and are now supporting it for our mutual customers".

Silicon results validate design for eBeam methodology at 65nm

SAN JOSE, USA: The eBeam Initiative, a forum dedicated to the education and promotion of a new design-to-manufacturing approach known as design for e-beam (DFEB), announced that steering group members D2S, Inc., e-Shuttle, Inc. and Fujitsu Microelectronics have validated the DFEB methodology for low-volume, 65-nm system-on-chip applications, without sacrificing performance, area or power.

DFEB combines software and design technologies that enable today’s most advanced character projection (CP) e-beam direct-write (EbDW) equipment to reduce shot count, thus making EbDW throughput feasible for low-volume designs. The announcement marks a significant milestone as it demonstrates early progress on the three-year roadmap.

The final estimated shot count for the test chip using DFEB represented a more than 10X reduction over conventional EbDW technologies, while also meeting the required performance, power and area goals. The collaborative effort drew from a number of companies involved in the eBeam Initiative.

Specifically, D2S and Fujitsu Microelectronics worked on the design while e-Shuttle manufactured the test chip to confirm the DFEB technology for the 65-nm node. D2S designed the DFEB library overlay with Fujitsu Microelectronics and also partnered closely with e-Shuttle and Advantest Corporation on the stencil mask used in the fab’s EbDW machine. Prototyping is a target application for DFEB, and with e-Shuttle’s experience in these services, they were able to validate the applicability of DFEB for prototyping.

According to Yoji Hino, corporate executive vice president of Fujitsu Microelectronics Limited and member of the eBeam Initiative steering group, “With this test chip, we now have tangible results that DFEB is enabling us to meet the necessary shot count requirements without sacrificing the quality of design results. DFEB makes maskless prototypes practical now.”

A related paper jointly authored by Advantest, D2S, e-Shuttle and Fujitsu Microelectronics Limited will be presented by e-Shuttle at the session of Electron Beam Lithography Tools during the 53rd International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), taking place May 26-29 in Marco Island, Fla.

The article, titled: “DFEB, a novel approach to EbDW throughput enhancement for volume production,” will be available online after May 29 at www.ebeam.org.

Fujitsu Microelectronics adopts Mentor's Calibre design-to-silicon platform

WILSONVILLE, USA: Mentor Graphics Corp. announced that Fujitsu Microelectronics Ltd has qualified and adopted the Calibre design-to-silicon platform for physical verification and design-for-manufacturing (DFM) of advanced IC products.

Fujitsu Microelectronics’ Mentor-based flow includes the sign-off standard Calibre verification platform with Calibre nmDRC, LVS, and xRC tools, and Mentor’s comprehensive DFM solution for manufacturing variability, an integrated tool suite for critical area analysis, litho-friendly design, and 3D variability.

The 3D variability solution provides improved planarity by enabling highly optimized fill based on either complex geometry-based rules, or full thickness (CMP) simulation.

“Fujitsu Microelectronics' leading-edge technologies require tight control over thickness variation. Density-based fill is a starting point and an improvement over traditional dummy fill, but at smaller features sizes our analysis shows that we need to consider more than just density,” said Noboru Yokota, General Manager of the Technology Development Division at Fujitsu Microelectronics. “The Mentor solution is unique because it can handle complex equations combining all the factors required to compute an optimum fill that achieves our planarity goals with as few added shapes as possible.”

“Our long-term partnership with Fujitsu Microelectronics has resulted in a complete solution that meets Fujitsu Microelectronics’ verification and DFM requirements for their latest IC designs regardless of which process offering is being targeted,” said Joseph Sawicki, Vice President and General Manager of the Design-to-Silicon division at Mentor Graphics.

“Our customers are moving to all-Mentor flows because we offer both the best-in-class technology for each design task, as well as the ease of integration and use that can only be achieved with a single integrated platform and tools built from the ground up to work together seamlessly,” he added.

Mentor’s DFM solution
The Calibre nm platform, with the Calibre nmDRC and Calibre LVS tools, has become the golden standard for verification of advanced ICs. Mentor’s comprehensive DFM solution is tightly integrated with the Calibre platform and supports the highest performance designs at advanced nodes with better control of manufacturing variability for cell libraries as well as full-chip layouts.

The Calibre DFM solution includes the Calibre LFDproduct, which provides accurate modeling of lithographic process and etch characteristics, and is the standard sign-off flow for litho hotspot and variability analysis for IP and full-chip applications.

It is fully integrated with the Calibre nmDRC, Calibre LVS (Layout vs. Schematic) and Calibre xRC products, allowing critical device and interconnect characteristics to be extracted based on accurately-modeled, “as-built” contour geometries. The resulting physical data can be plugged into a SPICE simulator to produce an accurate timing simulation of how physical blocks will actually perform.

The Calibre DFM solution includes the Calibre YieldAnalyzer and Calibre YieldEnhancer products for automated CAA analysis and fixing. The YieldEnhancer tool includes a SmartFill intelligent fill capability, which performs metal fills based on metal density and density gradients.

The Calibre CMPAnalyzer tool enables CMP planarity analysis and fill enhancement based on comprehensive, foundry-specific thickness models. Together, these products comprehensively address the variability issues of manufacturing at 65nm and below by making the physical design flow more process-aware and robust, reducing yield surprises late in the development cycle.

Fujitsu launches world’s first 125°C spec. low power memory for SiPs

BANGALORE, INDIA: Fujitsu Microelectronics Asia Pte Ltd (FMAL) today launched two new consumer FCRAM memory chips featuring an operating temperature range that has been extended to a high-temperature of 125°C for the first time in memory with a DDR SDRAM interface.

Sample shipment of the two new FCRAM products, the 512Mbit (MB81EDS516545), and 256Mbit (MB81EDS256545), will begin from today. These products are low power consumption memory optimized for use in system-in-packages (SiPs) in digital consumer products such as digital TVs and digital video camcorders.

Customers will benefit from using these new FCRAM chips combined with a System-on-Chip (SoC) in a SiP configuration, in that as the temperature of the SiP rises with the increase of operating speed, the operation is not impaired or limited by the memory. Further, there are benefits of reduced development effort needed for product design, reduced board space, as well as a reduction in the number of components.

Today’s digital consumer products continue to demand higher performance and faster speeds as well as low costs. To satisfy such needs, the use of SiPs, that combine for example a memory chip with a SoC, has been increasing. The use of SiPs also reduces the number of necessary components as well as reducing board space, thus helping to lower system costs. SiPs also make design easier, such as for the development of high-speed memory interfaces or for noise reduction measures.

Fig. 1: Options for thermal design in memory SiPs show the superiority of the new FCRAMs

As illustrated in Fig. 1, up until now conventional memory has given limitations to SiP usage that are resolved with the new FCRAM products. Fig. 1(a) shows a SiP configuration where a high-performance SoC has a large power consumption that generates heat such that the SiP temperature becomes 105°C. The SoC is specified to a maximum of 125°C so its operation is fine, however a conventional memory is used that can only operate up to 95°C so this SiP configuration is not usable.

To use such a conventional memory in the SiP, another option is to add some kind of heat disperser like a heat-sink. As shown in Fig. 1(b), this would reduce the SiP temperature to 90°C so operating is feasible, however there is increased cost and increases size. Subsequently, many customers who have been investigating using SiPs have wished for memory with an extended operating temperature range.

Fujitsu Microelectronics has responded to those needs by developing these 512Mbit and 256Mbit Consumer FCRAM products with a maximum operating temperature of 125°C. As shown in Fig. 1(c), using the 125°C rated FCRAM, the SiP operates fine even with an SoC with high power consumption, and without the need to add a heat-sink. This solves the problem of increased costs for thermal measures encountered when trying to use 95°C-rated conventional memory.

Furthermore, even for operating temperatures of 125°C, these FCRAM products can provide data transfer rates that are more than two times the data rate of conventional DDR SDRAM memory, while keeping power consumption low.

In fact, the new 512Mbit FCRAM for example can provide a reduction in power consumption of up to 50 percent compared to the equivalent conventional DDR2 SDRAM memory. Therefore, these new FCRAMs also contribute to a 50 percent reduction of CO2 emissions from the memory in digital consumer products.

Fujitsu Microelectronics will continue to develop products with the necessary performance and functionality for SiPs in order to provide solutions for digital consumer products with optimal value and cost.