Ubixum achieves product-ready design at First Silicon with Synopsys Galaxy Custom Designer solution

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Ubixum has used Synopsys' Galaxy Custom Designer implementation solution to successfully design its latest advanced image sensor chip.

The chip has been verified to be product-ready with first silicon. Custom Designer is a modern-era custom implementation solution that delivers superior ease-of-use and leverages Synopsys' Galaxy Implementation Platform to provide a unified solution for custom and digital designs. The Custom Designer tool set enabled Ubixum to achieve higher productivity and better integration with their optimized design process.

"Synopsys' comprehensive custom implementation and simulation solutions, methodologies and support played a critical role in helping us to achieve first-silicon success," said Keith Fife, cofounder of Ubixum.

"The use of Custom Designer running natively on the OpenAccess database allowed us to easily integrate our own tools and to access the design through our own API. Custom Designer can handle very large designs with many complex polygon shapes found in our custom devices. Its ability to properly handle and display large arrays has been important to our productivity. We have already started to use Custom Designer for our next product."

Ubixum turned to Custom Designer for its modern architecture and completeness that delivers productivity with a familiar user interface while integrating a common use model for simulation, analysis, parasitic extraction and physical verification.

Custom Designer is built natively on the OpenAccess database for legacy designs and offers unprecedented openness and interoperability with process design kits (PDKs) from leading foundries. Key modules include a schematic editor featuring on-canvas editing and dynamic net highlighting.

The simulation environment provides a common use model allowing access to Synopsys simulators, including the HSPICE, CustomSim and Custom WaveView simulators. In addition, the results from Hercules DRC/LVS and Star-RCXT parasitic extraction are dynamically available within Custom Designer.

"Galaxy Custom Designer continues to meet the demands of our customers as design challenges continue to increase. Ubixum's successful design underscores Synopsys' commitment to deliver solutions that address our customers' design challenges and meet their productivity needs," said Bijan Kiani, vice president of Product Marketing for Design and Manufacturing Tools at Synopsys.

"We congratulate Ubixum on their first-pass silicon success, and we plan to continue working closely with them for the mutual benefit of both companies by extending the advanced design capabilities of Galaxy Custom Designer."

NetLogic Microsystems selects Synopsys as primary EDA partner

MOUNTAIN VIEW, USA: Synopsys Inc. today announced that NetLogic Microsystems, a leader in the design and development of knowledge-based processors and high-speed integrated circuits, has signed an expanded business agreement to establish Synopsys as its primary EDA partner.

NetLogic Microsystems chose Synopsys because of its technology leadership and its ability to help NetLogic Microsystems meet its aggressive product schedules.

"Our continued success is driven by our leadership in technology innovation, our successful delivery of highly complex silicon products in advanced process nodes and our track record of first-silicon successes," said Dr. Dimitrios Dimitrelis, vice president of engineering for NetLogic Microsystems.

"The design tool efficiency, accuracy and robustness of Synopsys technology have helped us achieve this combination of product and technical excellence. We look forward to our continued collaboration with Synopsys as we develop next-generation knowledge-based processors and physical layer products for advanced telecommunications, enterprise, data center and storage networks."

With this latest agreement, NetLogic Microsystems is consolidating on Synopsys' Galaxy Implementation and Discovery Verification Platforms. The expanded set of selected products include Design Compiler synthesis, PrimeTime timing analysis and PrimeTime SI signal integrity analysis, Star-RCXT parasitic extraction, the VCS, ESP-CV, HSPICE and HSIM simulators for analog and digital verification, NanoTime transistor-level static timing analysis, and DesignWare® Library's portfolio of synthesizable and verification IP.

"Today's economic realities require leading fabless companies to seek design partners who can help them reduce their total cost of design and accelerate the deployment of new designs implemented in the latest process technologies," said John Chilton, senior vice president of marketing and business development at Synopsys.

"By extending our collaboration with NetLogic Microsystems, we can leverage our mutual strengths and the efficiencies of a fully integrated Synopsys flow to help them deliver products that significantly enhance the performance and functionality of next-generation networks."

Synopsys continues Galaxy Custom Designer momentum with rel 2009.06

MOUNTAIN VIEW, USA: Synopsys Inc. has announced availability of advanced analog simulation and layout capabilities in its Galaxy Custom Designer implementation solution.

The new features in the 2009.06 release deliver productivity advances to aid analog circuit designers and layout engineers, enabling Synopsys to further extend its reach in the custom implementation segment.

The Custom Designer 2009.06 release adds significant new capabilities, including high-capacity, high-performance schematic-driven layout (SDL) designed for today's large analog blocks. The SDL capability features robust schematic and layout synchronization technology and a streamlined engineering change order (ECO) flow.

Also included in the 2009.06 release is an easy-to-use analog simulation and analysis environment featuring high-performance waveform display and processing, mixed text/schematic integration and Tcl scripting for batch verification.

"Designer productivity should quickly improve with Custom Designer's new capabilities. Additionally, the open environment and support for interoperable process design kits should enhance design reuse and portability," said Anand Valavi, group head and manager, Analog Mixed Signal Group at Wipro.

"The 2009.06 release of Custom Designer continues Synopsys' established record of delivering differentiated capabilities with the same high quality, ease-of-use and enhanced productivity that we have come to expect."

Introduced in September 2008, Custom Designer is a modern-era custom implementation solution that delivers superior ease-of-use and leverages Synopsys' Galaxy Implementation Platform to provide a unified solution for custom and digital designs. Built natively on the OpenAccess database, it offers unprecedented support for legacy designs and interoperable process design kits (PDKs).

"Our vision is to deliver the industry's most productive and open custom implementation solution," said Paul Lo, senior vice president and general manager of the Analog/Mixed-Signal Group at Synopsys. "We are breaking new ground and delivering innovative capabilities previously not available in existing products. This release represents a major step in our mission to deliver advanced technologies to enhance designers' productivity through automation."

TSMC selects Synopsys Galaxy for integrated sign-off flow

MOUNTAIN VIEW, USA: Synopsys Inc. announced that TSMC selected Synopsys' Galaxy Implementation Platform for its new Integrated Sign-Off Flow.

The RTL-to-GDSII design flow deploys the advanced optimization technologies of Synopsys' Design Compiler synthesis and IC Compiler physical implementation solutions, and the PrimeTime sign-off and Star-RCXT extraction solutions -- the industry yardsticks for IC design sign-off. The new flow is now available for 65nm designs with planned extensions into other process technology nodes.

"Integrated Sign-Off flow leverages technology-leading EDA tools to provide our customers a faster, proven path to TSMC silicon," said ST Juang, senior director of Design Infrastructure Marketing at TSMC. "We based Integrated Sign-Off Flow on the Synopsys IC implementation toolset that we use ourselves for our advanced designs, and now make it available for our customers."

Design companies face the critical challenge of allocating expensive internal resources to validate libraries, EDA tools and design flows for a specific process node. Recognizing the importance and need for production-quality design flows, TSMC and Synopsys are addressing the needs of these mutual customers while achieving high quality of results and fast cycle time.

This flow seamlessly integrates proven Synopsys tools to provide mutual customers with an automated solution for implementing their chips in TSMC technologies.

"We are pleased that TSMC uses the Galaxy implementation and analysis tools for their own designs and now for the Integrated Sign-Off Flow the company recently introduced," said Bijan Kiani, vice president of Product Marketing at Synopsys. "With the Galaxy Implementation Platform fully encapsulated in TSMC's Integrated Sign-Off Flow, we are helping mutual customers deploy Synopsys' proven optimization and sign-off technologies, resulting in lower overall design cost, lower power, improved manufacturing and faster chip completion."

Synopsys' Eclypse enables Fujitsu to cut design cycle by 30 percent

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Fujitsu Microelectronics Ltd (FML) has deployed Synopsys' Galaxy Implementation Platform, for use with its low power digital electronics and mobile application ICs.

Fujitsu Microelectronics engineers used IEEE 1801 (UPF) to describe the power intent and drive the design, static verification and sign-off of several low power designs.

Utilizing the best-in-class optimization engines and complete low power capabilities in the Galaxy Implementation Platform, Fujitsu Microelectronics' designers were able to cut the traditional RTL-to-GDSII design cycle by 30 percent while meeting all design goals. Fujitsu Microelectronics is now ready to deploy this flow with their customers on 90 nanometer (nm), 65nm and 40nm digital consumer electronics designs.

"Deploying advanced power management techniques within very tight design schedules is among the key challenges for us and our customers," said Noboru Yokota, general manager of the Technology Development Division, Common IP and Technology Development Unit, Fujitsu Microelectronics. "With Synopsys' UPF-enabled Eclypse Low Power Solution, we met our stringent power, speed and area goals while saving 30 percent of the overall traditional design cycle. We are looking forward to helping our customers deploy this flow and get more competitive low power designs to market, faster."

Part of Synopsys' Eclypse Low Power Solution, the Galaxy Implementation Platform delivers the lowest power consumption, highest design performance and highest productivity through a complete low-power design portfolio.

DC Ultra synthesis and IC Compiler physical implementation automate the most advanced low-power techniques, such as multi-voltage and MTCMOS power gating, as well as more commonly used techniques such as clock gating and multi-threshold libraries. In addition, they perform comprehensive dynamic and leakage power optimization throughout the RTL-to-GDSII implementation, while concurrently optimizing timing, area, testability, congestion and other design goals.

The UPF-enabled implementation solution also includes PrimeTime PX accurate power analysis, PrimeTime SI noise analysis for sign-off, MVRC voltage-aware static checking and Formality power aware equivalence checking.

"Chip designers today need to meet stringent power specs within very tight schedules to be competitive in the marketplace, and the advanced low power capabilities in the Galaxy Implementation Platform are driving their success," said Bijan Kiani, vice president of Product Marketing at Synopsys. "Fujitsu Microelectronics has seen significant productivity gains with Synopsys' UPF enabled implementation flow and are now supporting it for our mutual customers".

Exar selects Synopsys as leading EDA partner

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Exar Corp., a leading provider of analog and mixed-signal solutions for connectivity and power management, has signed an expanded business agreement to establish Synopsys as its leading EDA partner.

As a result of the new multi-year agreement, the Synopsys' Galaxy Implementation and Discovery Verification platforms will be Exar's key design environment for designs at 65nm and below.

"We conducted an extensive evaluation process to select an EDA partner to not only support our current project needs, but our future design horizon as well, and Synopsys was the clear choice," said George Apostol, senior vice president and CTO, Exar.

"Over the years, Synopsys has demonstrated the technology leadership and outstanding technical support that is vital to helping us deliver highly differentiated silicon solutions to our customers. Synopsys tools, especially for mixed-signal designs, are ideal for our forthcoming data communications, storage, interface and power management products."

With the most recent agreement, Exar has chosen products that span Synopsys' broad portfolio. These products include Synopsys' Galaxy implementation platform featuring IC Compiler place-and-route technology, Design Compiler Graphical synthesis, PrimeTime PX timing and power analysis, PrimeRail power network analysis, Star-RCXT parasitic extraction, Hercules physical verification, TetraMAX automatic test pattern generation, and DFT MAX adaptive scan compression; Synopsys' Discovery verification platform featuring the VCS, HSPICE, HSPICE RF and CustomSim simulators for analog and digital verification, MVRC static voltage-aware verification, and MVSIM voltage-aware simulation; and DesignWare Library IP.

"Companies like Exar succeed through their ability to create highly differentiated designs and are justifiably selective when it comes to the partners with whom they entrust their design flows," said John Chilton, senior vice president of Marketing and Strategic Development at Synopsys. "Synopsys welcomes the opportunity for a long-term partnership with Exar, and we look forward to helping them further distinguish their products through technical innovation and rapid market introduction."

Toshiba selects Synopsys as key EDA partner

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Toshiba Corp. has signed a multi-year business agreement to establish Synopsys as its key EDA partner across the Toshiba semiconductor design flow.

As a result of the expanded relationship, Toshiba Corporation plans to expand use of Synopsys' verification and implementation design flow while partnering to reduce design cycle time.

"For longer than five years we have continued to build a successful relationship with Synopsys by collaborating across a broad set of next-generation EDA, commercial IP, and manufacturing technologies," said Tomotaka Saito, senior general manager of System LSI Division, Semiconductor Company, Toshiba Corp.

"The resulting products and design flow have enabled Toshiba to tape-out a number of chips across multiple technologies. Our existing Synopsys relationship helps solve current and future SoC design needs," he added.

The latest agreement between the two companies expands Toshiba's use of solutions across Synopsys' comprehensive portfolio. These products include Synopsys' Galaxy design platform featuring IC Compiler place-and-route technology, Design Compiler synthesis, DFT MAX test synthesis, TetraMAX automatic test pattern generation, PrimeTime timing analysis, Star-RCXT parasitic extraction, and IC Validator physical verification; Synopsys' Discovery™ verification platform featuring the VCS, HSPICE and CustomSim simulators for analog and digital verification; DesignWare Library; the Synplicity FPGA design solution; and the Eclypse Low Power Solution.

"Toshiba and Synopsys share many common goals, including pioneering high technology to develop products that create excitement," said Aart de Geus, chairman and CEO of Synopsys. "Synopsys greatly appreciates the long-standing collaboration with Toshiba that has resulted in numerous technology innovations deployed across consumer applications from digital TVs and mobile handsets to CMOS image sensors. By deepening our partnership, Synopsys intends to help advance Toshiba's technology strengths and increase R&D efficiency by reducing their design cycle time."

Toshiba exceeds quality goals for 65nm multimedia chips using Synopsys test solution

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Toshiba Corp. deployed Synopsys' test solution to exceed the rigorous quality demands for its 65-nanometer (nm) multimedia chips. Toshiba engineers employed Synopsys' TetraMAX automatic test pattern generation (ATPG) solution to achieve ultra-high test quality.

The designs benefited from new test automation that fully utilizes on-chip clocking circuitry to improve defect testing without impacting pattern count or test time. To lower test costs, Toshiba's design engineers also used Synopsys' DFT MAX compression technology to reduce both test time and test data volume by 50-100X. Toshiba's success in meeting its test goals is now driving deployment of the Synopsys test solution for 40-nm designs, which require advanced timing-driven ATPG to achieve very low defective parts per million (DPPM).

"Our design team needed to ensure the multimedia chips could be thoroughly tested without imposing costly changes to our test infrastructure," said Takashi Yoshimori, Assistant Chief Technology Executive of SoC Design, Semiconductor Company, Toshiba. "Using DFT MAX compression and TetraMAX ATPG allowed us to achieve all of our quality and cost goals on schedule."

Most systems-on-chip (SoC) designs today rely on many internally-derived clocks operating at different frequencies. To achieve very high defect coverage during test, these internal clocks must be properly synchronized to account for inter-domain fault effects -- a time-consuming process that requires substantial design resources.

New automation in TetraMAX ATPG utilizes existing on-chip clocking logic to improve test quality for SoCs containing multiple clock domains, making it feasible for designers to generate high-quality at-speed tests quickly and cost-effectively. Designers also benefit from using timing information generated by Synopsys' industry-leading PrimeTime static timing analysis solution. Integration of the Synopsys test solution in the Galaxy Implementation Platform is designed to ensure predictable quality-of-results that help eliminate costly, time-consuming design iterations between synthesis and physical implementation.

"Synopsys' continued investment in advanced test technologies, such as timing-driven pattern generation, is helping companies like Toshiba deliver products with higher reliability than was previously possible," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "Moreover, Toshiba's success in meeting its high-quality test goals cost-effectively and on-time reflects the benefits our customers derive from having DFT fully encapsulated in the Galaxy Implementation Platform."

Wolfson Microelectronics selects Synopsys as primary EDA partner

Wolfson Microelectronics selects Synopsys as primary EDA partner

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Wolfson Microelectronics plc, a leading supplier of mixed-signal semiconductors for consumer electronic products, has signed an expanded business agreement to establish Synopsys as its primary EDA partner.

Under the multi-year agreement, Wolfson plans to consolidate on Synopsys' Discovery verification platform, especially analog mixed-signal, and its Galaxy design platform in order to improve engineering productivity as the company focuses on broadening its product portfolio. Wolfson based its decision on Synopsys' ability to adapt to changing needs and offer outstanding support while delivering products that are proven to increase productivity.

"Wolfson and Synopsys have maintained a successful relationship for a number of years, resulting in a number of innovative products for the consumer electronics market," said Mike Hickey, chief executive officer for Wolfson Microelectronics. "As a key partner, Synopsys provides us with a portfolio of technology that is essential to our designers and enables them to continue to develop high-quality mixed-signal products. I see our continued cooperation leading to exciting opportunities for both companies as we focus on increasing our market reach by developing new products."

The latest agreement between the two companies expands Wolfson's use of solutions and services across Synopsys' comprehensive portfolio. Wolfson Microelectronics has also adopted Synopsys' SpiceExplorer transistor-level debugging environment as the basis for its new analog/mixed-signal (AMS) design analysis and debug flow, enabling Wolfson designers to automatically screen a vast array of simulation runs and find and fix design problems quickly.

Cadence's Encounter and how it matches up to Synopsys' Galaxy!

Early December 2008, Cadence Design Systems launched the Cadence Encounter Digital Implementation System, said to be a configurable digital implementation platform that delivers an incredible scalability with complete support for parallel processing across the design flow. Will it change the fortunes of the struggling EDA industry? EDA industry stats for Q3-08 given at the end of this post!

My first thoughts immediately went to Synopsys' Galaxy Custom Designer solution. This is the industry’s first modern-era mixed-signal implementation solution. Is the Cadence Encounter an answer to Synopsys' Galaxy? This is worth a shot!

Obviously, why has Cadence released Encounter now? How will the Encounter take on Synopsys' Galaxy? I managed to engage Rahul Deokar, Product Marketing Director, Cadence, to find out more.

The Encounter Digital Implementation System is a next generation high-performance, high-capacity RTL-GDS-II design closure solution with the industry's first end-to-end parallel processing flow that enables all steps of the design flow to be multi-CPU enabled -- from floorplanning, placement, routing, extraction to timing and signal integrity sign-off. He said, "At its core is a new memory management architecture and end to end multi-CPU backplane that provides scalability with increased performance and capacity to reduce design time and time-to-market."

Does it intend to take on Synopsys' Galaxy? Well, Deokar said: "Yes, it surpasses the other solutions available in the marketplace based on the following capabilities and features, which are:
* Ultra-scalable RTL-to-GDS-II system with superior design closure and signoff analysis for low-power, mixed-signal, advanced node designs.
* End-to-end multi-core infrastructure and advanced memory architecture for unparalleled scalability of capacity, design turnaround time, and throughput.
* Robust design exploration and automated floorplan synthesis and ranking solution.
* Embedded signoff-qualified variation analysis and optimization across design flow.
* Integrated diagnostic tools for rapid global timing, clock and power analysis/debug

Here’s a list of benefits that it provides designers:
* Significantly reduces design time, schedule and development risk.
* Increased productivity through automation; superior quality of results.
* Configurable and extensible platform that ensures maximum utilization and ROI -- upgrades proven design flow and amplifies existing expertise.
* Interoperability across package, logic, custom IC design, and manufacturability.

Harnessing power of multicore computing
According to Cadence, it provides complete support for parallel processing across the design flow. Does this mean that designers can fully harness the power of multicore computing? It would also mean that today's EDA tools capable enough to meet the multi-core challenge.

Deokar added: "Yes, the end-to-end parallel processing flow is supported across the entire design flow and consequently. Also, designers can fully harness the power of multicore computing. Today's designers commonly have dual CPU or even quad CPU machines on their desktop. The Encounter Digital Implementation System allows the designers to leverage their multi-CPU hardware and gain significant TAT improvements on the design cycle time and overall development schedule."

The Encounter end-to-end multi-CPU backplane delivers ultra-scale performance gains up to 16X in key areas such as routing and timing closure. All steps of the design flow are multi-CPU enabled. For instance, on a production design, when the Encounter is run on four CPUs, the user can get a 3.2X performance boost across the entire, end-to-end design flow.

Encounter deployed by over 15 customers?
Designers are said to be reporting dramatically improved design time, design closure, and faster time-to-market for advanced digital and mixed-signal devices. By what factors, and against which other tool(s) has Encounter been rated?

Deokar said that the Encounter Digital Implementation System has been developed in close collaboration with over 15 customer partners who have extensively used, validated and now, deployed it.

"Customers are already seeing overall design cycles significantly shorted by 25-30 percent, which translates to multiple weeks or even months. These significant improvements are against competitive tool flows in their current methodology," he added.

Encounter is also said to be offering new technologies for silicon virtual prototyping, die-size exploration and RTL and physical synthesis, providing improved predictability and optimization in early stages of the design flow.

Regarding this aspect, he pointed out that large scale design complexities (increased functionality, predictability, productivity, etc.,) pose some of the biggest challenges. Designs are getting huge at 100M+ gates, 100+ macros in the design, putting significant requirements on design tools, particularly, floorplanning of these macros, and the whole design becomes a huge challenge.

"The new Silicon Virtual Prototyping capabilities of Automated Floorplan Synthesis and Die Size Exploration help out exactly on that front. These can quickly provide floorplanning for that large 100M+ gates, 100+ macro design.

"And not just one floorplan, but designers can provide multiple criteria (say, along the lines of timing or power or area or congestion) and you will get multiple floorplans with their rankings…-- all this in a matter of minutes! Essentially, you could finish your breakfast or lunch (depending upon how fast you eat!) and be back to have multiple floorplans that you can then pick and choose from, and then proceed to implementation."

Addressing new problems at 45nm/40nm/32nm
Obviously, targeted at 45nm/40nm/32nm, etc., how can or how does Encounter anticipate and address the majority of the new problems associated with these geometries across the entire flow?

Deokar noted that its main customers include semiconductor companies working on 45nm and 32nm designs, with aggressive design specifications including 100 million or more instances, 1,000-plus macros, operating speeds exceeding 1GHz, ultra-low power budgets, and large amounts of mixed-signal content.

"The challenges facing these designs comprise of an increasing demand for design tool performance/capacity and design features for challenging ultra-large scale designs in the areas of low power, mixed signal, advanced node and signoff analysis. In addition, small market windows and product life-cycles and the cost pressures further exacerbate the situation," he noted.

The Encounter Digital Implementation System’s core design closure capabilities, plus the new advanced node technologies, including litho-, CMP-, thermal, and statistical-aware optimization provide comprehensive manufacturing- and variation-aware implementation, and an end-to-end multi-core infrastructure for fast, predictable design closure even on the most challenging designs.

Reducing memory footprints
It will be interesting to learn about the kind of work that has gone into reducing the memory footprint of the most memory-retentive applications.

Deokar said that an innovative memory architecture is at the core of the Encounter System that enables capacity and performance gains of 30-40 percent for full flat and hierarchical designs, even if you are running on a single-CPU machine.

Cadence's R&D team has developed an advanced memory defragmentation algorithm that allows the applications to be extremely memory-frugal …and that memory-efficiency enables designers to handle their biggest 100M+ instance designs.

Parallels with Synopsys' Galaxy Custom Designer?
There seem to be parallels with Synopsys' Galaxy Custom Designer for AMS. Also, there could be some chance of Cadence's Virtuoso and Encounter coming together in future.

According to Deokar, Synopsys’ Custom Designer for AMS is its entry into the full-custom/analog design marketplace, where the Cadence Virtuoso platform is a strong incumbent.

He said: "The biggest challenge for mixed signal designers is the efforts/resources involved in taking design data from the full-custom/analog tools to the digital implementation tools, and back and forth…in never-ending iterations.

"Now, with the Encounter Digital Implementation System, designers get the seamless full-custom/analog and digital design implementation interoperability…with unified constraints handling, mixed-signal floorplanning and ECO. It executes off a common design database (OpenAccess), enabling edits made in one design environment (e.g. Virtuoso) to be easily seen in the other design environment (e.g. Encounter). It also enables the design team to easily transfer the design data, to determine the optimal floorplan based on analog and digital constraints."

For example, the analog design team moves pins on the analog block, when the design is opened in Encounter, the modified pin locations are easily seen and the digital design team can execute a pin optimization to re-align the pins at the top-level.

In addition, the user can enter routing constraints in either Encounter or Virtuoso, and implement mixed signal routing in either environment. Top-level routing constraints could be defined within Virtuoso, then the top-level routing completed using the mixed signal routing functionality within Encounter.

Customers are already seeing their overall design schedules significantly reduced, added Deokar.

Postscript: Well, as expected, the EDA industry has taken a hit again. As per the EDA Consortium (EDAC) Market Statistics Service (MSS), the EDA industry revenue for Q3 2008 declined 10.9 percent to $1,258.6 million compared to $1,412.1 million in Q3 2007. The four-quarter moving average declined 2.8 percent.

Now, does Cadence's Encounter have the ability to turn around the EDA industry's fortunes? I don't think so! Much more needs to be done by Cadence and all of the other EDA companies!

Top 10 captivating moments in Indian semicon during 2008

Yes, the time has come for all of us to say goodbye to this year. It has been a very captivating year for the Indian semiconductor industry. Some consider it to be a year the industry came of age, while some others would look at the year as one where fab promises failed India.

Nevertheless, as I've maintained, having or not having a fab won't affect India very much as its traditional strengths have been in embedded and design services.

There have been several moments during the year that I personally savor. In fact, I have either witnessed most of those or written/blogged about them.

The top 10 captivating moments in Indian semiconductors during 2008, according to me, are:

1. S. Janakiraman, former chairman, ISA, declared before the world, in May at Dubai, during the IEF 2008, about India's growing strength in global telecom.

2. Growing interest in the solar photovoltaic industry in India, and subsequent proposals made by various companies, including Reliance.

3. EDA companies, such as Magma and also Synopsys, making their entry, or at least, intentions known, in the solar/PV industry.

4. Intel's new chip, designed largely in Bangalore, and of course, the Intel Developer Forum in Taipei, Taiwan.

5. Visit of a strong Japanese delegation to Bangalore, which showed remarkable keenness regarding possible investments in India.

6. BV Naidu quitting SemIndia, and putting in doubt India's fab story. Well, that's a different story, and one person's exit would not mean much to such a large industry.

7. ISA Excite, and the minister announcing that Karnataka could have its own semiconductor policy. The policy should be out in the new year, hopefully.

8. AMD's new chip, the Shanghai, which again, had a lot of involvement from AMD's Bangalore team.

9. NXP India achieving RF CMOS in a single chip. The entire analog and RF work was done in Bangalore, India.

10. Go parallel or perish, said James Reinders, of Intel! Parallelism or parallel computing involves the simultaneous use of more than one computer or processor to execute a program.

I was also present during the launch of Synopsys' Galaxy Custom Designer, which tackles the analog mixed-signal (AMS) challenges. It would occupy a joint 10th position.

There may have been some other moments as well! Would like to hear from all of you what are those other great times in India semiconductor industry during 2008!

Cadence's Virtuoso vs. Synopsys' Galaxy Custom Designer!

Synopsys recently introduced the Galaxy Custom Designer, which provides a unified solution for custom and digital designs, thereby enhancing designer efficiency.

Well, this solution invariably draws a comparison with Cadence's Virtuoso platform within the EDA industry!

That prompted me to engage Sandeep Mehndiratta, Product Marketing Group Director, Cadence Design Systems, in this discussion. We discussed a range of issues, such as how the Synopsys' Galaxy Custom Designer matches up with the Virtuoso, and whether designers can now design what they wish, including concepts and flows, as well as the relevance of open architectures.

For the record, a few years ago, Cadence introduced the next-generation Virtuoso custom design IC 6.1 platform, which had a major upgrade recently with the IC 6.1.3 release. This release has been production-proven with tapeouts from many customers. However, as I said, it is Synopsys' Galaxy Custom Designer doing the rounds in the EDA circles as of now!

Galaxy Custom Designer vs. Virtuoso
It is well known that Cadence has been the established leader in custom IC design space for decades, and has been constantly improving and upgrading technology to ensure it is providing best-in-class platform for designing today's complex custom chips.

Mehndiratta said: "A couple of years ago we introduced the next-generation Virtuoso custom design IC 6.1 platform. This release has been production-proven with tapeouts from many customers. Some of the leading customers that have adopted the Virtuoso platform include Ricoh, National Semiconductor, Cambridge Analog Technologies Inc., Matsushita, etc.

"Synopsys has recently launched Galaxy Designer and it is unproven as yet. From what we've read and heard from some of our mutual customers, the competitive introduction may be attempting to replicate older custom IC technology. While the jury will probably be out for some time on this unproven tool, Cadence continues to provide a complete solution for design, verification and implementation of complex analog and mixed-signal designs, differentiated by the tight integration between the underlying technologies."

With the advent of Galaxy, is it now safe to say that designers can finally design what they wish, including concepts and flows? Well, the answer's not yet there! However, Mehndiratta did touch upon Cadence's solution that is built upon decades of experience in this area and a strong eco-system made up of partners, third-party providers and foundries. Virtuoso, he added, is the most complete eco-system for designing ICs; not only with its inherent flow, but also because of its linkages to multiple tools inside and outside of Cadence.

"For many years, we have provided a consistent front-to-back flow, and over that time we have learned much about what customers need to do their designs efficiently. It is that knowledge base that we leveraged to accelerate productivity with 6.1 release couple of years back," he added.

If that is the case, why has it taken so long for a first modern-era mixed-signal implementation solution to be in place?

He referred to Cadence's next generation Virtuoso 6.1 introduced in November 2006, said to be the first modern, and most complete custom design solution released natively on the OA database. Productivity benefits are significant. RFIC Solutions Inc., a third-party intellectual property and design service provider, is said to have increased productivity two-fold by adopting the Cadence Virtuoso custom design platform.

Likewise, INSIDE Contactless, a fabless company and leader in contactless technology providing high-performance chipsets for secure, fast and reliable transactions with electronic identification, saved 20 percent in development time by adopting Cadence Virtuoso UltraSim Full-Chip Simulator, a component of Virtuoso Multi-Mode Simulation with a high-performance digital-solver technology, for the verification of its current and next-generation contactless and Near Field Communication (NFC) system-on-chip (SoC) designs.

He noted: "Specifically, mixed-signal design is evolutionary, not revolutionary. The concept of mixed-signal design isn't new. People have been designing in this manner for 15+ years. What is new is the more holistic approach being taken by designers developing mixed-signal circuits. The once clear lines between analog and digital design are blurring, and now the idea of "mixed-signal" is being architected in right from the beginning.

"That is why Cadence's AMS Designer covers transistor to system level design with a single simulation solution for complete verification. It is why Cadence has combined the power of its leading implementation platforms (Virtuoso and Encounter) to handle the implementation of mixed-signal designs."

Given that Synopsys' Galaxy Custom Designer can provide a unified solution for custom and digital designs, thereby enhancing designer efficiency, how will it change/affect designing, and the EDA landscape?

Mehndiratta pointed out that Cadence had defined a unified solution long ago. "Our industry leadership in this area, and Synopsys mimicking of that solution are testaments of Cadence's vision. Competition is good for all industries, the end-customer usually benefits. You can count on Cadence to not only remain competitive, but also retain our industry leadership in custom/mixed-signal design."

Importance of open architecture
Let us also look at the importance of open architecture that natively supports interoperable PDKs.

Cadence also believes in open architectures. Its Design Framework II was built as an open architecture, and that's the reason, why there are many companies that have connected (30+) to form a larger ecosystem. Whereas, the Industry Standard Framework has been tried and failed, the company maintains.

Mehndiratta said: The reason it was a failure is the same as interoperable PDKs. Building frameworks and PDKs that are based on a "lowest common denominator" principle do not provide the most optimized design flow. Instead, you are left with systems that try to please everyone and in the end are rejected as bloated beasts retarding the progress of design."

Finally, how does Cadence propose to address the Galaxy challenge?

As expected, Cadence hopes to continue to provide customers and partners with a framework in which they can build their tools into the Virtuoso design flow in the most optimized way possible.

Also, by providing its proven and industry standard Pcell technology that takes advantage of the key features in Cadence's design flow, thereby allowing for fast and productive design today and in the future.

Synopsys' Galaxy Custom Designer tackles analog mixed signal (AMS) challenges

Synopsys Inc. recently unveiled its Galaxy Custom Designer solution, the industry’s first modern-era mixed-signal implementation solution. Architected for productivity, the Galaxy Custom Designer leverages Synopsys’ Galaxy Design Platform to provide a unified solution for custom and digital designs, thereby enhancing designer efficiency.

Galaxy Custom Designer delivers a familiar user interface while integrating a common use model for simulation, analysis, parasitic extraction and physical verification. It is the first-ever implementation solution built natively on the OpenAccess database for legacy designs as well as a new componentized infrastructure offering unprecedented openness and interoperability with process design kits (PDKs) from leading foundries.

Subhash Bal, Country Director, Synopsys (India) EDA Software Pvt. Ltd, highlighted three key features: One, it is architected for productivity. Two, it is a complete custom design solution. And three, it is based on an open environment.

The key question: why the Galaxy Custom Designer, and why now? Simple! The modern AMS era is characterized by interdependent custom and digital functions; analog IP is now mainstream; and there is the phenomena of an increased embedded memory. Current solutions are said to possess limited horizon. Hence, Galaxy!

A new solution is said to be the need of the hour, which is complete -- verification and implementation, with common models, extraction, analysis. Re-spin is not an option. Next, unified implementation, which addresses both custom and cell based needs. Custom and cell based functions are highly interdependent. Also, close to 100 percent of designs today are AMS.

Finally, the solution has to be open and portable. This accelerates the design cycle and IP portability. Also, quicker access to process details is a must! Architected for productivity, Galaxy Custom Designer has a similar look and feel, and works using fewer clicks -- three as against six!

Galaxy Custom Designer's Schematic Editor has productivity enhancers such as real-time connectivity, on-canvas editing and smart connect. Similarly, productivity enhancers for its Layout Editor include push button DRC and Extract, standard TCL and Python PCells, and auto via and guard ring generation. The WaveView Analyzer has features such as highest capacity and performance, complex analysis toolbox, and an automated TCL verification scripting.

A unified platform for cell and custom means superior ease of use, performance, capacity and data integrity. Open and portable, it facilitates plug-and-Play IP as well as standards based PDK, which means one PDK for all tools, added Synopsys' Bal.

The IPL (Interoperable PDK Libraries) is an industry alliance established on April 2007 to collaborate on the creation and promotion of interoperable process design kit (PDK) standards.

Wipro Technologies has been among the early users of the Galaxy Custom Designer. I also managed to speak with Anand Valavi, Group Head, Analog Mixed-Signal Group, Wipro Technologies.

Valavi said: "From an EDA tool perspective, in AMS area, the amount of productivity is a lot less than in the digital area. The per transistor productivity for a digital designer is several magnitudes higher than an analog designer."

The methodology is definitely not as evolved as in the digital area. According to him, 'This productivity will now increase for analog and AMS areas, and people can do a lot more complex designs in a shorter period of time. There has been a lot of integration."

On the salient features or enhancements, he said there have been reasonably good improvement in several areas. One, there is an alternative, now, and that brings a lot of advantages. Two, when you take it down to next level, there are several other technical reasons.

Valavi added that an integrated environment definitely improved the productivity. There are other minor things. When you start using it, there are things that helps technical users -- for example, an on-canvas editing. Also, the usage or collaborative results in the iPDK libraries will improve the effectiveness in chips designs that are churned out. "It will surely give people working in analog design area a choice," he noted.