BANGALORE, INDIA: Magma Design Automation Inc. announced that Quartz DRC and Quartz LVS now support TSMC’s interoperable design rule check (iDRC) and layout-versus-schematic (iLVS).
With the two unified electronic design automation (EDA) data formats and scalable Quartz physical verification solution, Magma and TSMC are working to make their mutual customers’ adoption of TSMC’s 40nm process technology faster, easier and less costly.
"TSMC has taken a leadership role in defining an interoperable, common language for all DRC and LVS tools," said ST Juang, senior director of Design Infrastructure Marketing at TSMC.
“The unified iDRC and iLVS files eliminate the need to develop and maintain multiple custom runsets, improve data accuracy and consistency, and enables designers to choose the EDA tool that best meets their requirements. Ultimately, our customers can adopt our advanced process technologies early for their designs.”
Quartz DRC and Quartz LVS are architected to process integrated circuit (IC) designs of any size, at any technology node, in the least amount of time. Magma's is the first truly scalable physical verification solution, able to provide turnaround time that is up to an order of magnitude faster than existing solutions by leveraging existing compute resources.
The Quartz tools are fully compatible with third-party IC implementation flows and can read file formats used by traditional physical verification tools.
“The scalable architecture of Quartz DRC and Quartz LVS was designed specifically to provide fast, efficient physical verification of large, complex designs,” said Anirudh Devgan, general manager of Magma’s Custom Design Business Unit.
“That scalability and native support for the Tcl procedural language used by the TSMC iDRC and iLVS formats make Quartz DRC and Quartz LVS the ideal solution for designs targeting TSMC’s processes.”
Showing posts with label iLVS. Show all posts
Showing posts with label iLVS. Show all posts
Thursday, July 30, 2009
Sunday, July 26, 2009
TSMC, Synopsys ally on interoperable unified physical verification formats
MOUNTAIN VIEW, USA: Synopsys Inc. announced that its recently launched IC Validator DRC/LVS product now fully supports interoperable Design Rule Checking (iDRC) and Layout-Versus-Schematic (iLVS), the new TSMC unified physical verification formats.
Synopsys was one of the first EDA suppliers to collaborate with TSMC to create and develop the unified formats, transitioning from a vendor-specific to an interoperable specification of technology files, which not only enables consistent interpretation across all tools, but also assures timely access to all Synopsys customers.
"Working with advanced node customers, TSMC and Synopsys concluded that a unified specification for Physical Verification tools was key to accelerating time to market, a primary benefit of TSMC's Open Innovation Platform," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.
"We benefited from the close cooperation with Synopsys, using IC Validator as the development and validation platform and a catalyst for the timely introduction of these formats."
IC Validator was used from early on as one of the reference platforms for prototype development and final qualification of the unified formats. Architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use, IC Validator provides a step up in physical designer productivity.
IC Validator delivers speed-up through multicore processors by efficiently parsing iDRC/iLVS generic rules into atomic instructions suitable for highly distributed execution.
In addition, with its advanced and near linear scalar hybrid signoff engine, IC Validator provides an efficient platform for coding and validating complex polygon and edge based rules needed for emerging process nodes.
As part of the Galaxy Implementation Platform, IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tape-out and improve manufacturability by performing physical verification within the implementation flow.
It is production-ready and has been successfully used for tape-outs at leading fabless customers and chip manufacturers. Synopsys will showcase iDRC- and iLVS-enabled flows with IC Validator at the 46th Design Automation Conference in San Francisco, California.
"By eliminating qualification and consistency barriers and assuring timely access to technology files, this close collaboration between TSMC and Synopsys, with participation from other EDA vendors, clears the way for designers to easily select amongst available physical verification tools," said Bijan Kiani, vice president of product marketing, design and manufacturing products at Synopsys.
"This puts Synopsys in a strong position to efficiently bring In-Design physical verification to our common customers."
Synopsys was one of the first EDA suppliers to collaborate with TSMC to create and develop the unified formats, transitioning from a vendor-specific to an interoperable specification of technology files, which not only enables consistent interpretation across all tools, but also assures timely access to all Synopsys customers.
"Working with advanced node customers, TSMC and Synopsys concluded that a unified specification for Physical Verification tools was key to accelerating time to market, a primary benefit of TSMC's Open Innovation Platform," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.
"We benefited from the close cooperation with Synopsys, using IC Validator as the development and validation platform and a catalyst for the timely introduction of these formats."
IC Validator was used from early on as one of the reference platforms for prototype development and final qualification of the unified formats. Architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use, IC Validator provides a step up in physical designer productivity.
IC Validator delivers speed-up through multicore processors by efficiently parsing iDRC/iLVS generic rules into atomic instructions suitable for highly distributed execution.
In addition, with its advanced and near linear scalar hybrid signoff engine, IC Validator provides an efficient platform for coding and validating complex polygon and edge based rules needed for emerging process nodes.
As part of the Galaxy Implementation Platform, IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tape-out and improve manufacturability by performing physical verification within the implementation flow.
It is production-ready and has been successfully used for tape-outs at leading fabless customers and chip manufacturers. Synopsys will showcase iDRC- and iLVS-enabled flows with IC Validator at the 46th Design Automation Conference in San Francisco, California.
"By eliminating qualification and consistency barriers and assuring timely access to technology files, this close collaboration between TSMC and Synopsys, with participation from other EDA vendors, clears the way for designers to easily select amongst available physical verification tools," said Bijan Kiani, vice president of product marketing, design and manufacturing products at Synopsys.
"This puts Synopsys in a strong position to efficiently bring In-Design physical verification to our common customers."
Subscribe to:
Posts (Atom)
