Sigrity takes high-speed chip-to-chip analysis to next level with SystemSI

DAC 2011, CAMPBELL, USA: Sigrity Inc., the market leader in signal and power integrity solutions, announced the SystemSI family of signal integrity analysis solutions – the industry’s first comprehensive environment for end-to-end simulations of high-speed signal interfaces.

Unlike previous approaches that analyze timing margin phenomena in an isolated, piecemeal manner to predict overall margins, Sigrity’s SystemSI family brings everything together within a single environment to streamline the development of high-speed products. It includes a block-based editor, support for standard modeling formats, automated model connections and highly accurate simulation, resulting in the most realistic assessment of actual system behavior.

The SystemSI family of solutions can be used at the pre-layout stage, post-layout stage, or anywhere in-between. SystemSI will be featured in Sigrity’s booth (#2525) at this year’s Design Automation Conference in San Diego, Calif., June 5-10, 2011 and in a webcast scheduled for June 16, 2011.

SystemSI is available in two configurations: SystemSI – Serial Link Analysis, and SystemSI – Parallel Bus Analysis.

SystemSI – Serial Link Analysis builds on Sigrity’s capabilities introduced in the company’s award-winning Channel Designer software to fully analyze high-speed SerDes designs.

SystemSI – Parallel Bus Analysis brings the same level of automation and accuracy to the design of high-speed bus interfaces such as DDRx (Dual Data Rate) memory interfaces. It enables users to quickly and comprehensively analyze timing margins for DDRx memory interfaces.

SystemSI – Parallel Bus Analysis considers multiple effects concurrently, including dielectric/conductor loss, reflections, crosstalk, inter-symbol interference (ISI) and simultaneous switching noise (SSN). End-to-end simulation that accounts for combined signal and power interactions results in a reliable, accurate assessment of system behavior.

“Brocade became an early adopter of Sigrity’s SystemSI – Parallel Bus Analysis software, which we use to perform rapid DDR3 simulations that accurately incorporate crucial power delivery system impacts to ensure we can meet our tight timing margins,” said Shahriar Mokhatarzad, a hardware engineering manager at Brocade. “We use a variety of models in our simulations. It has been very helpful to have a way to convert detailed transistor-level models to power-aware behavioral models. This enables us to efficiently complete simulations that would have been impossible otherwise.”

“With timing margins in the picosecond range, the traditional divide-and-conquer approach for phenomena such as reflections, crosstalk and non-ideal power effects such as SSN fails to support timing closure,” said Ken Willis, marketing manager at Sigrity. “Each effect impacts others in fairly unpredictable ways. Simulation of these effects together emulates actual hardware behavior to give a more realistic picture of timing margins.”