MOUNTAIN VIEW, USA: Analog Bits, the Integrated Clocking and Interface IP leader, announced the commercial availability of the industry's lowest power 40nm, high-speed Serializer/Deserializer (SerDes) IP. The breakthrough macro is programmable to support multiple protocols and small enough to be used in embedded SoCs.
The Analog Bits 40nm SerDes supports more than 100 lanes, from 1 to 12.5 Gb per lane, on single IC with a mere 5mw per gigabit per second per lane power consumption. It is currently in production in multiple applications and is validated in over 30 industry standard protocols including PCI Express, SATA, XAUI, XFI, SGMII, and delivers the lowest chip-to-chip communications latency.
"The new 40nm SerDes is ideal for high speed processors and consumer electronics devices in high definition TVs, set top boxes and game consoles. The IP's programmable features allow designers to use licensable IP to create highly differentiated SoC products while reducing design risk and speeding time-to-market," explains Mahesh Tirupattur, Executive Vice President, Analog Bits.
Path to the future
SerDes technology converts between parallel and serial communications protocols and is of increasing importance in embedded SoC applications.
"SerDes interfaces are becoming the norm across the SoC market," according to Rich Wawrzyniak, senior market analyst, Semico Research. Over the next several years, we project that more and more IP Subsystems will appear featuring SerDes interfaces to move data quickly to other on-chip subsystems and for high speed communications to the outside world. This will be especially true in applications that need to move large amounts of data at high speeds – like the spread of HD Video capability into portable consumer devices."