Aldec releases RTL simulator with enhanced assertions and Xilinx SecureIP support

HENDERSON, USA: Aldec Corp., a leader in RTL Simulation and Electronic Design Automation (EDA), has released its latest RTL and gate-level simulator, Active-HDL 8.2 sp1, for FPGA design and verification engineers.

Active-HDL 8.2 sp1 includes full support for Xilinx SecureIP, IEEE VHDL/Verilog encrypted IP and an enhanced Assertions bundle option. The new Assertion bundle supports three Assertion types: IEEE 1800 SystemVerilog Assertions (SVA), Property Description Language (PSL) and Open Vera Assertions (OVA) for legacy designs.

The bundle also supports a dedicated Assertions Viewer, Assertion debugging and complete visibility of Assertions, properties and Functional Coverage statements through the simulator.

Active-HDL 8.2 sp1 is available today and is sold directly from Aldec and its authorized world-wide distributors. To download a free 20 day evaluation copy today, visit http://www.aldec.com/Downloads/default.aspx.

Active-HDL
Active-HDL is a brand-leading Windows FPGA design and simulation solution. The product includes: an HDL Design tool suite, high-performance mixed-language simulator and a multi-vendor FPGA flow manager that controls Simulation, Synthesis and Implementation for Actel, Altera, Lattice, Quicklogic and Xilinx FPGAs, and more than 80 popular EDA tools, in a single environment.

Active-HDL supports Windows 7, Vista, XP and 2003, 32-bit and 64-bit operating systems.