Atmel's SiliconCity for low-cost custom defined SoCs

SAN JOSE, USA: Atmel Corp. announced a new custom architecture for 90nm SiliconCity ASIC development, providing up to 350K gates/mm2, offering customers gate densities in the range of a standard cell ASIC.

SiliconCity Flexible Architecture allows designers to create their own unique base wafer architecture for multiple product variations while generously reducing customer design time, lowering the NRE and reducing risk through design reuse.

ASIC development based on the architecture allows for lower mask fees and faster time to market. "Consider the fabless semiconductor company that has multiple products defined, all with slightly different features," said Jay Johnson, Marketing Director for Atmel's NA ASIC Business.

"Creating a new ASIC for each one is too costly and time consuming. The old trick of multiple products on the same die with different bond options has run out of gas. That's the real value of SiliconCity Flexible Architecture."

The architecture relies on the breadth of Atmel's standard microcontroller solutions, to create SoCs including the reusability and proven IP that Atmel offers through its AVR and AT91SAM standard products.

Metal Programmable Cell Fabric (MPCF) at the heart of the technology: MPCF is Atmel's patented ASIC technology that makes the CAP (customizable microcontroller) family of products, and SiliconCity Flexible Architecture, possible.

In the case of CAP, Atmel defines the platform with ARM cores and bus subsystems, peripherals and memories. SiliconCity Flexible Architecture leaves the definition of the platform up to the user.

By predefining the common embedded core and bus, memory and peripheral mix, the customer has the ability to implement unique IP for multiple products. The architecture gives the customer complete control, while MPCF gives it the flexibility.

MPCF offers a smaller core cell with better routing. The key to the MPCF technology is a 6 transistor core cell that is less than 3.2 square microns. In the 90nm process, a SiliconCity Flexible Architecture ASIC yields between 300,000 and 350,000 gates per square millimeter.

A novel routing scheme provides two layers of metal for interconnect, increasing gate utilization up to 90 percent. The combination of the higher gate density and better routability of MPCF-based SoC results in die sizes that are about half those of previous 130nm generations.

Routing and transistor geometry alignment: With MPCF, the cell size is matched perfectly to the integer multiple of the routing grid and transistor pitch, which results in no wasted silicon.

In addition, contacts and vias are also the same size as metal trace, which eliminates any potential overlap and provides the most effective vertical use of silicon in the design.

These aspects of MPCF make targeting the exact gate size required for the design much easier and more cost effective than the typical sea-of-gates architecture common with gate arrays and some early structured ASIC products.

In addition, MPCF metal-programmable cells and standard cells can be placed in separate regions on the die or freely mixed without any die size penalty. Therefore the fixed platform part of the design can be implemented in standard cell technology, while the flexible portion of the die with MPCF for quick derivative spins.

Easy migration from existing processor-plus-FPGA designs: Many existing designs based on an industry standard microcontroller and an FPGA may be directly migrated to a SiliconCity Flexible ASIC in as little as 20 weeks from final gate-level netlist with minimal re-engineering and low initial NRE mask charges.

Future iterations of designs can be implemented in just 8-12 weeks with even lower single metal mask NRE charges.

Products based on the 90nm SiliconCity Flexible Architecture are available now. It is also available in 130nm.