SAN JOSE, USA: Real Intent Inc., the innovator in automating the intelligence of formal techniques for design verification, announced today that it is shipping PureTime 3.2 with new product options-- PureTime Constraints and PureTime Exceptions.
The PureTime product family helps designers prevent faulty circuits and avoid expensive re-spins. It offers best in class, high-performance constraints validation and timing exceptions verification tools designed to provide users with ultimate confidence in the timing constraints employed across all phases of implementation flow.
PureTime Constraints checks for correctness and completeness of design constraints. PureTime Exceptions uses state of the art formal technologies to verify false and multi-cycle path exceptions.
PureTime 3.2 includes many new capabilities, can be easily integrated with Real Intent’s other families of products, and plugs straight into standard EDA flows. Features include:
* Smart built-in checks to validate constraints (SDC/TCL) against RTL as well as gate-level design sources.
* Formal verification and reporting at the exception-level as well as the exception’s path-level.
* Glitch-aware, combinational and sequential high performance formal verification engines with high completion rates.
* Fast and powerful debugging capabilities with cross probing to TCL/SDC, schematic and design sources.
* Automatic incremental analysis for shorter run times.
“Design constraints are important throughout the whole implementation flow,” said Prakash Narain, President and CEO at Real Intent. “Ensuring the correctness of design constraints and timing exceptions is critical for design and verification teams. Real Intent is dedicated to customers’ success by offering automatic verification solutions employing innovative formal technology in an easy to use methodology. The new functionalities added in PureTime 3.2 represent a significant technological enhancement of the product.”
The PureTime 3.2 is available now.
Tuesday, August 25, 2009
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