Si2 announces member demos at DAC 2011

AUSTIN, USA: Six companies will be demonstrating significant progress advancing design flow interoperability in the Silicon Integration Initiative (Si2) Booth #1631 at the Design Automation Conference on June 5-9, at the San Diego Convention Center in San Diego, CA.

These companies will be showing how Si2 standards developed by the OpenAccess Coalition, the Low Power Coalition, the Open Modeling TAB and the Design for Manufacturability Coalition can provide innovative approaches to critical IC design flow issues. Following are descriptions of each company’s demonstrations, as provided by them.

Analog Rails: Will demonstrate its complete OA analog expert fully integrated design system based on automation. Reduce your design time from months to days. Optimization, sensitivity, simulation, synchronized schematic<=>layout (correct by construction layout), automatic placers and routers, Mr. Fixit (better then DRC/LVS), real parasitic extraction on the fly, EM, IR, and 100 percent crossprobing at all times. The usage is a paradigm shift and is several generations beyond what is out in the market.

Cadence Design Systems: Will demonstrate its Silicon Realization flows, which use an OpenAccess infrastructure and leverage proven Virtuoso and Encounter technologies to maximize productivity and predictability in today's complex design projects.

Witness the seamless integration of analog and digital domains with a mixed-signal design, implementation, and verification solution. Learn more about a robust and advanced low-power solution, proven to dramatically reduce overall power consumption in customer silicon and total turnaround time of chip design. Finally, see the industry’s only co-design environment for analog, digital, and package domains to realize your 3D-IC designs.

IBM: Will demonstrate a fast memory analysis tool capable of rapidly assessing the performance and yield of complex arrays. The tool is targeted at enabling memory design (SRAM, embedded DRAM) in today's advanced technology nodes, which requires accurate device variation modeling and spice-level simulation, as well as accelerated statistical analysis techniques. The tool has been in wide-spread internal use at IBM for many years, and has been extensively proven against hardware. The Si2 Open Modeling Characterization Interface can be used to develop the device models. The demo will show the tool in actual operation on real designs.

Magma Design Automation: Will demonstrate Quartz DRC/LVS, the fastest physical verification tool on the market. Quartz DRC/LVS fully supports the OpenDFM physical verification runset language developed by Si2. Magma directly participated in the development of this language and has demonstrated its support by running a full OpenDFM runset on a 28-nm design for a partner company in under 4 hours. Magma also provides OpenAccess support for its unified digital and analog IC design system, Talus and Titan. Talus is a 28-nm tapeout-proven digital IC implementation system and Titan is the most automated analog design platform. The Titan platform is a full OpenPDK partner.

Pulsic: Will be demonstrating the new Pulsic Planning Solution, the only complete integrated hierarchical planning solution for custom designs. See how the Pulsic Planning Solution solves today’s toughest design challenges with intelligent, signal aware pin placement and optimization; interactive guide driven bus and repeater planning and insertion; top level signal planning with matched topology for multiple nets; guide driven, easy to use, hierarchical power planning technologies. Whether you are designing custom digital, custom ASIC, FPGA, microprocessors, Memory, LCD/LED, or other ASSP designs, Pulsic can help you get predictable designs to tape out faster and more efficiently than ever before.

Synopsys: Will demonstrate Custom Designer, which is built natively on OpenAccess to provide the industry’s most open, standards-based custom design solution. Learn about Custom Designer's advanced custom IC layout capabilities. The demo will showcase SmartDRD technology for design-rule-driven layout with automated DRC violation repair and interactive routing technology for fast DRC and LVS correct net creation.