Mentor Graphics provides Calibre verification and Tessent test solutions for 3D-IC in TSMC Reference Flow 12

WILSONVILLE, USA: Mentor Graphics Corp. announced support for 3D-IC in TSMC’s Reference Flow 12.0 (RF12). Solutions for both silicon interposer and through silicon via (TSV) stacked die configurations are now supported by the Calibre physical verification and extraction platform and the Tessent IC test solution.

“We’re very pleased that Mentor has not only provided a comprehensive 3D-IC design- to -silicon solution, but one that is straightforward and compatible with our customers’ existing design flows,” said Suk Lee, director of design infrastructure marketing at TSMC. “This is extremely important to enable customers to adopt 3D with the least amount of disruption so they can realize all its potential benefits.”

“IC designers are looking at 3D-IC as another degree of freedom to meet specific application requirements and to optimize performance, power, and footprint,” said Joseph Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor graphics. “We are providing a solution that builds on their existing design flows and experience to help them achieve faster time to market.”

Mentor 3D-IC solution
Mentor introduced support for 3D design rule checking (DRC), layout versus schematic (LVS) checking and extraction of back side metal in the Calibre platform last year with TSMC. RF12 adds specialized support for silicon interposer extraction and netlisting, new Calibre 3D rule decks for DRC and LVS, and enhanced debugging support enabling cross-probing across multiple die.

The Calibre tools automatically generate separate GDS data for the interface layers, and perform DRC and connectivity checks based on stack information, such as die order, x-y position, rotation and orientation, etc., provided in a Calibre 3D assembly deck. The Mentor solution also performs parasitic extraction of the backside redistribution layers often used in advanced 3D and silicon interposer SoC designs.

Very high defect coverage during wafer test is critical to achieving acceptable package yield in 3D-IC designs. The Tessent solution for 3D-IC test provides a combination of ATPG and BIST capabilities that work together to deliver the highest test quality while reducing development time and manufacturing test costs. In multi-die configurations Tessent tools allow test patterns to be routed from the bottom die, to the die above via “test elevator” TSVs, automatically re-sequencing patterns and creating control data to ensure correct pattern distribution across multiple die. For logic-memory stacks, the Tessent MemoryBIST product creates logic to fully test stacked DRAMs with at-speed testing of memory bus logic and connecting TSVs, including shared memory bus configurations.

The Tessent platform also supports post-silicon reprogramming of BIST patterns to accommodate changes in memory die, or variant stacks using different memory designs. To fully test TSV connections, the Tessent SoCScan and Tessent FastScan products work together to use scan chain test patterns on one die to provide stimuli and capture results from another die, thereby testing the integrity of interface logic and TSV connections. All test data is applied through package connections on the bottom die—no connections to upper stacked die are required.