ATopTech’s Aprisa physical design solution included in TSMC Reference Flow 12.0 for 28nm designs

SAN JOSE, USA: ATopTech, the leader in next generation physical design solutions, announced that Aprisa, the company’s place and route solution, is included in TSMC Reference Flow 12.0.

TSMC and ATopTech collaborated in the development of Reference Flow 12.0 to address the increasing design challenges for 28nm. Many new technologies -- including 28nm design enablement, timing, reliability, low power and design for manufacturing (DFM) capability -- have been implemented in Aprisa to enable customer design successes in smaller geometries.

“We are pleased to add ATopTech’s Aprisa P&R tool into TSMC Reference Flow 12.0,” said Suk Lee, director of design infrastructure marketing at TSMC. “The close collaboration between the two companies strengthens TSMC’s 28nm design infrastructure and will help enable smooth and successful 28nm projects for our joint customers.”

“As part of the process of qualification by TSMC for 28nm design enablement, we have undertaken extensive new algorithm developments to ensure minimum runtime impact to the router as a result of expanded design rules at lower geometries,” said Jue-Hsien Chern, CEO of ATopTech. “Inclusion in TSMC Reference Flow 12.0 continues our commitment to providing customers with cutting-edge physical design tools for advanced process nodes.”

ATopTech's physical design tools are architected specifically to meet the challenges of designing integrated circuits (ICs) at the most advanced technology nodes. Aprisa is the company’s complete place and route (P&R) solution, including placement, clock tree synthesis, optimization, global routing, and detailed routing. Aprisa’s latest release supports TSMC’s 28nm design rules in Reference Flow 12.0.

TSMC Reference Flow 12.0 enhancements
28nm Design Enablement
* The Aprisa place-and-route engine has been qualified to support TSMC 28nm design rules.

Reliability
* EM-aware clock-tree synthesis (CTS) placement has been implemented to mitigate electro-migration problems on the power and ground rails due to very thin metal wires and cell architecture. Power-budget information is used by CTS to spread out high-current buffers for desired EM quality.

Timing
a. Critical-path-aware GDSII output: Uses GDSII marker layers to ensure critical-path timing is not disturbed by post-route processes.

b. Timing optimization for resistance: Resolves timing/SI issues caused by higher wire resistance in advanced process nodes.

c. Add-on OCV derating for SBOCV: Optimization with SBOCV for process variation and add-on OCV for other design variations, such as temperature and voltage variations.

d. Cell-based setup/hold uncertainty – Reduces timing pessimism by setting clock uncertainty to cell masters individually, instead of using a global clock uncertainty.

Low power
a. Leakage power optimization under MCMM: Optimizes leakage power with Multi-Vt and gate-bias libraries in post-route stage without impacting timing under MCMM.

b. Low clock power flop placement: Improves dynamic power of clock tree by placing flops closely.

c. Library pin with non-default rule attributes: Ensures cell-based voltage-dependent routing rules are observed for low-power designs.