SEMATECH researchers to present breakthrough innovations in III-V MOSFETs, FinFETs and resistive RAMs at IEDM

AUSTIN & ALBANY, USA: Revealing research breakthroughs, engineers from SEMATECH’s Front End Processes (FEP) program will present technical papers at the 56th annual IEEE International Electron Devices Meeting (IEDM) from December 6-8, 2010, at the Hilton in San Francisco, CA.

SEMATECH experts will report on resistive RAM (RRAM) memory technologies, advanced Fin and nanowire FETs for scaled CMOS devices, high mobility III-V channel materials on 200mm silicon wafers in an industry standard MOSFET flow, and future ultra-low power tunneling FET devices — highlighting significant breakthroughs that address the growing need for higher performance and low power devices.

Additionally, SEMATECH will host invitational pre-conference workshops on December 5. The workshops will focus on technical and manufacturing gaps affecting promising emerging memory technologies and III-V channels on silicon. Co-sponsored by Tokyo Electron and Aixtron, these workshops will feature experts from industry and academia debating the challenges and opportunities in these areas in a series of presentations and panel discussions.