CATANIA, ITALY: The partners in a new publicly-funded European research project have announced details of the multinational/multidisciplinary program called LAST POWER ('Large Area silicon carbide Substrates and heTeroepitaxial GaN for POWER device applications).
The aim of this important 42-month ENIAC (European Nanoelectronics Initiative Advisory Council) project is to provide Europe with strategic independence in the field of wide band gap (WBG) semiconductors.
This field is of major strategic importance as it involves the development of highly energy-efficient systems for all applications that need power, from telecom to automotive, from consumer electronics to electrical household appliances, and from industrial applications to home automation.
The consortium will develop European technology for the complete production chain for semiconductor devices built with SiC (Silicon Carbide) and heteroepitaxial GaN (Gallium Nitride on silicon wafers). These two semiconductor materials offer higher speed, current capability, breakdown voltage and thermal capability compared to conventional silicon technologies.
"The power semiconductor market, which represents approximately 30 percent of the overall semiconductor market, is set to change significantly in response to the ever-increasing demand for more energy-efficient devices," said project coordinator Salvatore Coffa, Group VP and R&D GM, Industrial and Multisegment Sector, STMicroelectronics. "This key project, which targets secure strategic independence in the emerging field of SiC and GaN technologies, will place Europe at the forefront of energy-efficient devices."
The overall objective of the project is to develop a cost-effective and reliable integration of advanced SiC and GaN semiconductors in the European power microelectronics industry. This will be achieved via five specific objectives:
* Growth of large area (150mm) SiC and high quality heteroepitaxial GaN on 150mm Si wafers, beyond the current worldwide state-of-the-art for substrates, epitaxy and surface preparation;
* Development of new dedicated equipments for material growth, characterization and processing;
* Processing of reliable and efficient SiC and GaN devices on 150mm wafers;
* To demonstrate high-performance devices with properties that cannot be obtained on Si, including a 1200V/100A SiC MOSFET, SiC JFET capable of operating up to 250 degrees C, and GaN HEMT devices for power switching;
* To develop advanced packages for high-temperatures devices and improve device reliability.
The partners in the LAST POWER consortium are:
STMicroelectronics S.r.l. (Italy) – project coordinator
LPE S.p.A. (Italy)
Consiglio Nazionale delle Ricerche, Istituto per la Microelettronica e Microsistemi (Italy)
Epitaxial Technology Center S.r.l. (Italy)
Foundation for Research & Technology-Hellas (Greece)
NOVASiC S.A. (France)
Consorzio Catania Ricerche (Italy)
Institute of High Pressure Physics UNIPRESS (Poland)
Universita della Calabria (Italy)
SiCrystal AG (Germany)
SEPS Technologies AB (Sweden)
SenSiC AB (Sweden)
Acreo AB (Sweden)
Aristotle University of Thessaloniki (Greece).
Sunday, October 31, 2010
ST's MEMS accelerometer monitors and tracks motion and tilt around the car
GENEVA, SWITZERLAND: STMicroelectronics has expanded its sensor portfolio with a new automotive-grade 3-axis low-g accelerometer.
Combining low power consumption and small footprint with high precision and robust performance, ST's new accelerometer targets a wide range of automotive applications, including vehicle tracking, event recording, abuse monitoring, and dead-reckoning for enhanced navigation capabilities.
ST's AIS328DQ senses acceleration along all three axes and converts the motion and tilt information into a high-resolution digital signal that it transmits to a microcontroller through a standard SPI or I2C interface. The accelerometer provides extremely accurate output across user-selectable full-scale ranges of plus or minus 2g/plus or minus 4g/plus or minus 8g, boasting excellent stability over time and temperature.
Robust and resistant to shock and electromagnetic interference, ST's AIS328DQ is qualified to AEC-Q100, a critical stress-test qualification for automotive integrated circuits established by the Automotive Electronics Council (AEC).
With an extended temperature range from -40 to 105 degrees C, the sensor can be used inside the cabin or inside modules that have self-heating components, like power stages. An embedded routine can be activated at any time to verify correct functioning of the device.
ST's newest automotive-grade accelerometer has been designed and produced using the same manufacturing-process technology that ST has successfully applied to more than 850 million motion sensors sold in the market.
Samples of ST's AIS328DQ automotive accelerometer are available and volume production is scheduled for Q3 2011. Unit pricing is below $3 for volumes in the range of 100,000 pieces.
Combining low power consumption and small footprint with high precision and robust performance, ST's new accelerometer targets a wide range of automotive applications, including vehicle tracking, event recording, abuse monitoring, and dead-reckoning for enhanced navigation capabilities.
ST's AIS328DQ senses acceleration along all three axes and converts the motion and tilt information into a high-resolution digital signal that it transmits to a microcontroller through a standard SPI or I2C interface. The accelerometer provides extremely accurate output across user-selectable full-scale ranges of plus or minus 2g/plus or minus 4g/plus or minus 8g, boasting excellent stability over time and temperature.
Robust and resistant to shock and electromagnetic interference, ST's AIS328DQ is qualified to AEC-Q100, a critical stress-test qualification for automotive integrated circuits established by the Automotive Electronics Council (AEC).
With an extended temperature range from -40 to 105 degrees C, the sensor can be used inside the cabin or inside modules that have self-heating components, like power stages. An embedded routine can be activated at any time to verify correct functioning of the device.
ST's newest automotive-grade accelerometer has been designed and produced using the same manufacturing-process technology that ST has successfully applied to more than 850 million motion sensors sold in the market.
Samples of ST's AIS328DQ automotive accelerometer are available and volume production is scheduled for Q3 2011. Unit pricing is below $3 for volumes in the range of 100,000 pieces.
Looking to the future
Michelle Prunty, Semico Spin
PHOENIX, USA: It seems everywhere we turn, there is hype about how low 2011 will go. Our own opinion is that 2011 will be an above average growth year, rising 9.5 percent over 2010. Considering an average growth year for the semiconductor industry is 8 percent growth, 9.5 percent is pretty good.
Our forecast is based on our IPI (Inflection Point Indicator) which has been an accurate indicator of the industry’s ups and downs for 15 years.
For example:
The IPI declined throughout 2000 indicating the slowdown for 2001.
Beginning in the second half of 2002, the IPI increased significantly, pointing to strong growth starting in the second half of 2003.
In 2004, when the market was booming ,the IPI started to turn down, indicating a correction year in 2005.
In 2006, we saw the IPI, again, on an upward trend, which matched 2007 as a peak year.
For most of 2007 the IPI declined, pointing to a decline in the semiconductor market in 2008.
The 2008 IPI hit bottom in February 2008, which pointed to the beginning of the V-shaped recovery starting in February 2009.
Source: Semico Researh.
So how is the IPI predicting 2011 and beyond? Take a look at the blue line in the graph above, which predicts the pink and green line about four quarters in advance.
Extrapolating the IPI out to 2014, and we start to see that:
2010 is UP
2011 is UP
2012 is UP with 2nd half declining
2013 is DOWN
2014 is UP
This current growth will continue into 2012. The future for the next few years is bright for the semiconductor industry.
PHOENIX, USA: It seems everywhere we turn, there is hype about how low 2011 will go. Our own opinion is that 2011 will be an above average growth year, rising 9.5 percent over 2010. Considering an average growth year for the semiconductor industry is 8 percent growth, 9.5 percent is pretty good.
Our forecast is based on our IPI (Inflection Point Indicator) which has been an accurate indicator of the industry’s ups and downs for 15 years.
For example:
The IPI declined throughout 2000 indicating the slowdown for 2001.
Beginning in the second half of 2002, the IPI increased significantly, pointing to strong growth starting in the second half of 2003.
In 2004, when the market was booming ,the IPI started to turn down, indicating a correction year in 2005.
In 2006, we saw the IPI, again, on an upward trend, which matched 2007 as a peak year.
For most of 2007 the IPI declined, pointing to a decline in the semiconductor market in 2008.
The 2008 IPI hit bottom in February 2008, which pointed to the beginning of the V-shaped recovery starting in February 2009.
Source: Semico Researh.So how is the IPI predicting 2011 and beyond? Take a look at the blue line in the graph above, which predicts the pink and green line about four quarters in advance.
Extrapolating the IPI out to 2014, and we start to see that:
2010 is UP
2011 is UP
2012 is UP with 2nd half declining
2013 is DOWN
2014 is UP
This current growth will continue into 2012. The future for the next few years is bright for the semiconductor industry.
Cadence reports Q3 2010 financial results
SAN JOSE, USA: Cadence Design Systems Inc. announced results for the third quarter of fiscal year 2010.
Cadence reported third quarter 2010 revenue of $238 million, compared to revenue of $216 million reported for the same period in 2009. On a GAAP basis, Cadence recognized net income of $127 million, or $0.48 per share on a diluted basis in the third quarter of 2010, compared to a net loss of $14 million, or $(0.05) per share on a diluted basis, in the same period in 2009.
Cadence’s third quarter 2010 net income includes a $148 million income tax benefit related to the settlement of an Internal Revenue Service examination of Cadence’s federal income tax returns for the tax years 2000 through 2002.
Using Cadence’s non-GAAP measure, net income in the third quarter of 2010 was $11 million, or $0.04 per share on a diluted basis, as compared to net income of $7 million, or $0.03 per share on a diluted basis, in the same period in 2009.
Lip-Bu Tan, president and CEO, said: "Cadence had a successful third quarter. Momentum for Cadence solutions is building at our key customers, driven by the combination of leading and competitive technology and solid performance from the Cadence team. Revenue and operating margin continue to grow. There is still more work to do, but I am pleased with our results to date."
Business outlook
For the fourth quarter of 2010, the company expects total revenue in the range of $230 million to $240 million. Fourth quarter GAAP net loss per diluted share is expected to be in the range of $(0.06) to $(0.04). Net income per diluted share using the non-GAAP measure defined below is expected to be in the range of $0.03 to $0.05.
For the full year 2010, the company expects total revenue in the range of $917 million to $927 million. On a GAAP basis, net income per diluted share for fiscal 2010 is expected to be in the range of $0.55 to $0.57. Using the non-GAAP measure defined below, net income per diluted share for fiscal 2010 is expected to be in the range of $0.16 to $0.18.
Cadence reported third quarter 2010 revenue of $238 million, compared to revenue of $216 million reported for the same period in 2009. On a GAAP basis, Cadence recognized net income of $127 million, or $0.48 per share on a diluted basis in the third quarter of 2010, compared to a net loss of $14 million, or $(0.05) per share on a diluted basis, in the same period in 2009.
Cadence’s third quarter 2010 net income includes a $148 million income tax benefit related to the settlement of an Internal Revenue Service examination of Cadence’s federal income tax returns for the tax years 2000 through 2002.
Using Cadence’s non-GAAP measure, net income in the third quarter of 2010 was $11 million, or $0.04 per share on a diluted basis, as compared to net income of $7 million, or $0.03 per share on a diluted basis, in the same period in 2009.
Lip-Bu Tan, president and CEO, said: "Cadence had a successful third quarter. Momentum for Cadence solutions is building at our key customers, driven by the combination of leading and competitive technology and solid performance from the Cadence team. Revenue and operating margin continue to grow. There is still more work to do, but I am pleased with our results to date."
Business outlook
For the fourth quarter of 2010, the company expects total revenue in the range of $230 million to $240 million. Fourth quarter GAAP net loss per diluted share is expected to be in the range of $(0.06) to $(0.04). Net income per diluted share using the non-GAAP measure defined below is expected to be in the range of $0.03 to $0.05.
For the full year 2010, the company expects total revenue in the range of $917 million to $927 million. On a GAAP basis, net income per diluted share for fiscal 2010 is expected to be in the range of $0.55 to $0.57. Using the non-GAAP measure defined below, net income per diluted share for fiscal 2010 is expected to be in the range of $0.16 to $0.18.
Power IC market makes a full recovery in 2010
ENGLAND: Following a decline of over 14 percent in 2009, the world market for power management and driver ICs is forecast to recover fully in 2010, growing by 20 percent to over $12 billion. Strong annual growth is projected for the next four years. This is according to the latest analysis from IMS Research.
All 16 of the power IC markets analyzed in 2010 have outperformed previous growth predictions. Strong growth is projected to continue into 2011 and for most products through to 2014, driven by strong forecast demand in applications such as lighting, PC notebooks, servers and cellular infrastructure. It has however been questioned by some involved in the industry as to whether growth is being driven by real underlying demand.
Ryan Sanderson, senior market analyst for IMS Research’s Power and Energy group, commented: “Growth in the first half of 2010 was much stronger than many power semiconductor suppliers had predicted and has continued into the second half of the year. Whilst demand for end equipment certainly accelerated in 2010, there is also an element of over-spending; which has been driven by low capacity causing the lead times for many components to be extended. This has inflated revenue growth and also helped to stabilize average selling prices.”
He added: “IMS Research predicts increasing demand in 2011, another year when revenues will increase more than the historical average. Demand for consumer appliances such as notebooks and flat panel TVs remains high; whilst the industrial market continues to recover, driving further demand. Ten percent growth a year is projected for 2012 to 2014.”
Further findings from “The World Market for Power Management & Driver ICs – 2010” identified Texas Instruments as the leading supplier, with over 10 percent of the 2009 world market. Of the top five suppliers in the market, which account for almost 40 percent of the world total, three lost market share from 2008 to 2009.
All 16 of the power IC markets analyzed in 2010 have outperformed previous growth predictions. Strong growth is projected to continue into 2011 and for most products through to 2014, driven by strong forecast demand in applications such as lighting, PC notebooks, servers and cellular infrastructure. It has however been questioned by some involved in the industry as to whether growth is being driven by real underlying demand.
Ryan Sanderson, senior market analyst for IMS Research’s Power and Energy group, commented: “Growth in the first half of 2010 was much stronger than many power semiconductor suppliers had predicted and has continued into the second half of the year. Whilst demand for end equipment certainly accelerated in 2010, there is also an element of over-spending; which has been driven by low capacity causing the lead times for many components to be extended. This has inflated revenue growth and also helped to stabilize average selling prices.”
He added: “IMS Research predicts increasing demand in 2011, another year when revenues will increase more than the historical average. Demand for consumer appliances such as notebooks and flat panel TVs remains high; whilst the industrial market continues to recover, driving further demand. Ten percent growth a year is projected for 2012 to 2014.”
Further findings from “The World Market for Power Management & Driver ICs – 2010” identified Texas Instruments as the leading supplier, with over 10 percent of the 2009 world market. Of the top five suppliers in the market, which account for almost 40 percent of the world total, three lost market share from 2008 to 2009.
Analog Devices intros digital isolator with integrated transformer driver and PWM controller
BANGALORE, INDIA: Analog Devices Inc. has introduced the industry’s first digital isolator with an integrated transformer driver and PWM (pulse-width modulation) controller in a single package.
The integration of these components into a small, surface mount 20-lead SSOP (shrink small outline package) enables the new four-channel digital isolator to reduce board space by up to 30 percent and achieve cost reductions of 10 percent while simplifying the development of systems requiring isolated data and power.
The product enables designers to implement an isolated dc-to-dc converter that provides up to 2 watts of regulated, isolated power at 3.3 V to 30 V from a 5.0-V input supply or 3.3-V supply. Analog Devices’ new ADuM347x digital isolators are ideal for applications that require isolated data and isolated power, including data acquisition, industrial process control using Fieldbus, and building control. Watch a video on the ADuM347x digital isolators.
The new devices expand ADI’s iCoupler digital isolation portfolio, which provides the most extensive range of isolation technology in the industry. The ADuM347x isolators, along with other products in the portfolio, enable designers to implement isolation in their designs without the cost, size, power, performance, and reliability constraints found with traditional isolation products, such as optocouplers.
The integration of these components into a small, surface mount 20-lead SSOP (shrink small outline package) enables the new four-channel digital isolator to reduce board space by up to 30 percent and achieve cost reductions of 10 percent while simplifying the development of systems requiring isolated data and power.
The product enables designers to implement an isolated dc-to-dc converter that provides up to 2 watts of regulated, isolated power at 3.3 V to 30 V from a 5.0-V input supply or 3.3-V supply. Analog Devices’ new ADuM347x digital isolators are ideal for applications that require isolated data and isolated power, including data acquisition, industrial process control using Fieldbus, and building control. Watch a video on the ADuM347x digital isolators.
The new devices expand ADI’s iCoupler digital isolation portfolio, which provides the most extensive range of isolation technology in the industry. The ADuM347x isolators, along with other products in the portfolio, enable designers to implement isolation in their designs without the cost, size, power, performance, and reliability constraints found with traditional isolation products, such as optocouplers.
Gaming market reveals changes in the MEMS gyroscope competitive landscape
LYON, FRANCE: As the use of motion sensors in various consumer electronic devices is expanding quickly, the industry competitive landscape is significantly changing. In particular concerning MEMS gyroscopes.
The battle to introduce the 3-axis gyroscopes on smartphones has just started, but the major market for MEMS gyroscopes is still gaming. In a $418 million consumer gyroscope market in 2010, gaming represents a market segment of $162 million according to Yole Développement.
Yole Développement will release next month, its new report dedicated to worldwide consumer electronics industry. This market and technological analysis will include competitive landscape, market data, technological challenges analysis.
Source: Yole Développement, France.
More than 50 million Motion Plus controllers (which integrates InvenSense and Epson gyroscopes) have been sold out since their launch in June 2009. However this is just a start, since new motion sensing solutions with MEMS gyroscope are now being released on the market.
In September 2010 the Sony Move game controller was launched. It integrates 9 degrees of freedom with the use of accelerometers, gyroscopes and compass. It uses complex sensor fusion algorithms creating more precise gestures recognition, and more immersive gaming experiences. And now, Nintendo is planning to add motion sensing features in portable game stations, by integrating accelerometers and gyroscopes in 3DS, to be released in February 2011.
Yole Développement believes two gyroscope industry providers will benefit from these changes:
* According to Yole Développement’s information, the 2-axis gyro in the Move controller is from Sony. Sony is a newcomer in the MEMS gyroscope landscape: Sony has developed a 2-axis solution that is now integrated in all its DSCs except high-end products since end 2009.
Those parts are also sold to a few other DSC manufacturers in Japan, and are now integrated in the PS3 Move game controller, which means that Sony now has a very large gyro market share! Sony Computer Entertainment may have a second source for this 2-axis gyroscope but Yole Développement believes that Sony gyroscopes are used in majority.
* Panasonic has recently launched its 3-axis gyroscope and is actively promoting it in the gaming and mobile phone industry. Yole Développement expects Panasonic 3-axis gyroscopes to be integrated in the future Nintendo 3DS.
Competition is gaining in intensity as the gaming gyroscope market is becoming increasingly attractive. Established players (ST, Epson Toyocom, InvenSense) are also pushing hard to introduce 3-axis gyroscopes into this market while new large players such as Kionix and Bosch Sensortec are also expected to enter this market. It is possible that a unique 3-axis gyro could replace the 2-axis gryo + single axis gryo of the Motion Plus controller.
Current integrations of several types of sensors opens the way for even more technology or capability. Yole Développement forecasts an increase in market traction for MEMS IMUs within one or two generation of products, provided that the cost of such package becomes more attractive compared to the simple addition of accelerometer and gyroscope discrete sensors.
The battle to introduce the 3-axis gyroscopes on smartphones has just started, but the major market for MEMS gyroscopes is still gaming. In a $418 million consumer gyroscope market in 2010, gaming represents a market segment of $162 million according to Yole Développement.
Yole Développement will release next month, its new report dedicated to worldwide consumer electronics industry. This market and technological analysis will include competitive landscape, market data, technological challenges analysis.
Source: Yole Développement, France.More than 50 million Motion Plus controllers (which integrates InvenSense and Epson gyroscopes) have been sold out since their launch in June 2009. However this is just a start, since new motion sensing solutions with MEMS gyroscope are now being released on the market.
In September 2010 the Sony Move game controller was launched. It integrates 9 degrees of freedom with the use of accelerometers, gyroscopes and compass. It uses complex sensor fusion algorithms creating more precise gestures recognition, and more immersive gaming experiences. And now, Nintendo is planning to add motion sensing features in portable game stations, by integrating accelerometers and gyroscopes in 3DS, to be released in February 2011.
Yole Développement believes two gyroscope industry providers will benefit from these changes:
* According to Yole Développement’s information, the 2-axis gyro in the Move controller is from Sony. Sony is a newcomer in the MEMS gyroscope landscape: Sony has developed a 2-axis solution that is now integrated in all its DSCs except high-end products since end 2009.
Those parts are also sold to a few other DSC manufacturers in Japan, and are now integrated in the PS3 Move game controller, which means that Sony now has a very large gyro market share! Sony Computer Entertainment may have a second source for this 2-axis gyroscope but Yole Développement believes that Sony gyroscopes are used in majority.
* Panasonic has recently launched its 3-axis gyroscope and is actively promoting it in the gaming and mobile phone industry. Yole Développement expects Panasonic 3-axis gyroscopes to be integrated in the future Nintendo 3DS.
Competition is gaining in intensity as the gaming gyroscope market is becoming increasingly attractive. Established players (ST, Epson Toyocom, InvenSense) are also pushing hard to introduce 3-axis gyroscopes into this market while new large players such as Kionix and Bosch Sensortec are also expected to enter this market. It is possible that a unique 3-axis gyro could replace the 2-axis gryo + single axis gryo of the Motion Plus controller.
Current integrations of several types of sensors opens the way for even more technology or capability. Yole Développement forecasts an increase in market traction for MEMS IMUs within one or two generation of products, provided that the cost of such package becomes more attractive compared to the simple addition of accelerometer and gyroscope discrete sensors.
Saturday, October 30, 2010
Mandates boost car safety MEMS sensor market in Korea and Japan
EL SEGUNDO, USA: New mandates set to increase the safety of vehicles in South Korea and Japan will cause market revenue for Microelectromechanical System (MEMS) automotive sensors in those countries to rise dramatically starting in 2012, and will more than double compared to previous expectations by 2014, according to the market research firm iSuppli Corp.
The mandates apply to MEMS sensors needed for Electronic Stability Control (ESC) and Tire Pressure Monitoring Systems (TPMS).
iSuppli research shows that automotive MEMS revenues for ESC and TPMS in those countries will increase at a CAGR of 24.3 percent and reach $122.2 million once the South Korean and Japanese regulations are fully in force by 2014—up from $41.2 million in 2010. iSuppli’s earlier view, based on organic growth alone, would have yielded $54 million by 2014—a CAGR of just 5.5 percent over the same time frame.
The new mandates mean that cars fitted with ESC and TPMS in these regions now account for 16 percent of associated revenues compared to 7 percent without regulation.
The figure shows iSuppli’s forecast of automotive MEMS revenue for ESC and TPMS from 2006 to 2014 in Korea and Japan.
Source: iSuppli, USA.
Korean mandates to kick in; Japan expected to follow suit
With mandates in South Korea expected to take effect on Jan. 1, 2012 for new cars and on Jun. 30, 2014 for existing vehicles, a total about 1.7 million passenger cars weighing less than 4.5 tons will be affected by 2014, according to iSuppli’s Automotive Practice.
The Japanese mandate is not yet public, but multiple iSuppli sources indicate that Japan is likely to follow South Korea’s example, with as many as 5.3 million vehicles impacted during the same time period.
“The mandates underscore the current trend toward international harmonization of automotive safety standards, following those developed for markets in the United States, Europe, Australia and Canada,” said Richard Dixon, senior analyst for MEMS and sensors at iSuppli.
ESC has been recognized in numerous safety studies as highly significant in saving lives by sensing car trajectories and accelerations, computing these against inputs from magnetic sensors that monitor the driver’s intention, and then making the necessary corrections via the brakes if so required. TPMS first began in the United States following the TREAD Act and has been a legal requirement since 2007.
For Japan, a move to ESC will carry significant implications for the country’s small-car segment, which makes up one-third of the market in the region. At present, such vehicles in Japan have a very low ESC penetration of less than 1 percent, compared to 16 percent on average for small cars in Europe.
In comparison, cars in the Japanese luxury segment cars are already fully penetrated, while the much more voluminous mid-range cars exhibit—significantly—fitment rates in common with Europe of more than 80 percent. ESC has the greatest market impact as the contribution to system cost of the MEMS sensor—including accelerometer, gyroscope and one or more pressure sensors—amounts to approximately $21 per vehicle.
As for TPMS, systems based on the most prevalent direct measurement located in the valve of a rim add an average of 4.2 MEMS pressure sensors per vehicle, or around $8 worth of sensors. In such a system, the pressure sensors communicate information wirelessly to an indicator warning light on the dashboard if tire pressure drops below specified limits.
Challenges lie ahead for manufacturers
With the adoption of automotive safety mandates on the increase worldwide, system suppliers and sensor companies find themselves preparing to meet some challenges.
Already, considerable price pressure exists on the components used in these mandated systems. And to remain competitive, manufacturers will need to find ways to produce the critical safety systems for the new markets at the lowest cost possible.
In response, companies like TRW are producing TPMS in the valve with even fewer parts for 2011 models at lower cost. Other major Tier 1 entities, such as Continental and Bosch, are already deploying multi-sensor combo packages containing both gyroscopes and accelerometers to lower package costs and reduce footprint.
For its part, Japanese Tier 1 giant Denso has recently added a gyroscope to its inertial sensor armory and will likely follow suit with a multi-sensor combo package of its own. iSuppli analysis shows that about one-third of all vehicles with ESC will feature this solution in five years’ time.
The mandates apply to MEMS sensors needed for Electronic Stability Control (ESC) and Tire Pressure Monitoring Systems (TPMS).
iSuppli research shows that automotive MEMS revenues for ESC and TPMS in those countries will increase at a CAGR of 24.3 percent and reach $122.2 million once the South Korean and Japanese regulations are fully in force by 2014—up from $41.2 million in 2010. iSuppli’s earlier view, based on organic growth alone, would have yielded $54 million by 2014—a CAGR of just 5.5 percent over the same time frame.
The new mandates mean that cars fitted with ESC and TPMS in these regions now account for 16 percent of associated revenues compared to 7 percent without regulation.
The figure shows iSuppli’s forecast of automotive MEMS revenue for ESC and TPMS from 2006 to 2014 in Korea and Japan.
Source: iSuppli, USA.Korean mandates to kick in; Japan expected to follow suit
With mandates in South Korea expected to take effect on Jan. 1, 2012 for new cars and on Jun. 30, 2014 for existing vehicles, a total about 1.7 million passenger cars weighing less than 4.5 tons will be affected by 2014, according to iSuppli’s Automotive Practice.
The Japanese mandate is not yet public, but multiple iSuppli sources indicate that Japan is likely to follow South Korea’s example, with as many as 5.3 million vehicles impacted during the same time period.
“The mandates underscore the current trend toward international harmonization of automotive safety standards, following those developed for markets in the United States, Europe, Australia and Canada,” said Richard Dixon, senior analyst for MEMS and sensors at iSuppli.
ESC has been recognized in numerous safety studies as highly significant in saving lives by sensing car trajectories and accelerations, computing these against inputs from magnetic sensors that monitor the driver’s intention, and then making the necessary corrections via the brakes if so required. TPMS first began in the United States following the TREAD Act and has been a legal requirement since 2007.
For Japan, a move to ESC will carry significant implications for the country’s small-car segment, which makes up one-third of the market in the region. At present, such vehicles in Japan have a very low ESC penetration of less than 1 percent, compared to 16 percent on average for small cars in Europe.
In comparison, cars in the Japanese luxury segment cars are already fully penetrated, while the much more voluminous mid-range cars exhibit—significantly—fitment rates in common with Europe of more than 80 percent. ESC has the greatest market impact as the contribution to system cost of the MEMS sensor—including accelerometer, gyroscope and one or more pressure sensors—amounts to approximately $21 per vehicle.
As for TPMS, systems based on the most prevalent direct measurement located in the valve of a rim add an average of 4.2 MEMS pressure sensors per vehicle, or around $8 worth of sensors. In such a system, the pressure sensors communicate information wirelessly to an indicator warning light on the dashboard if tire pressure drops below specified limits.
Challenges lie ahead for manufacturers
With the adoption of automotive safety mandates on the increase worldwide, system suppliers and sensor companies find themselves preparing to meet some challenges.
Already, considerable price pressure exists on the components used in these mandated systems. And to remain competitive, manufacturers will need to find ways to produce the critical safety systems for the new markets at the lowest cost possible.
In response, companies like TRW are producing TPMS in the valve with even fewer parts for 2011 models at lower cost. Other major Tier 1 entities, such as Continental and Bosch, are already deploying multi-sensor combo packages containing both gyroscopes and accelerometers to lower package costs and reduce footprint.
For its part, Japanese Tier 1 giant Denso has recently added a gyroscope to its inertial sensor armory and will likely follow suit with a multi-sensor combo package of its own. iSuppli analysis shows that about one-third of all vehicles with ESC will feature this solution in five years’ time.
First AXIe 3.1 standard system module
HOPKINTON, USA: Test Evolution Inc., the leading supplier of OEM test products based on the AXIe 3.1 open standard, has announced its System Module as part of the Evolution© series of test systems focused on the semiconductor test market.
The new System Module brings to the semiconductor industry one of the building blocks of an open hardware and software platform for both device characterization and production test, using common instruments and test programs for lower cost and faster time to volume production.
"The AXIe standard enables high performance instrumentation in an open standard modular solution. This will enable a renaissance in low cost focused test solutions in semiconductor test applications," said Lev Alperovich, president,Test Evolution. "The System Module is the first in a series of products that will give customers the tools to improve productivity, time to market, and ultimately better profitability.”
The System Module is a single slot AXIe 3.1-compliant board. The System Module supports all functionality of AXIe 3.1 standard including robust backplane and front-panel triggering for inter-instrument control, 250 MB/s PCI Express to all slots, in-system calibration support, and controllable load board power supplies. The System Module, with its rear transition connector provides for cable-less connections to semiconductor devices in both characterization and production testing.
"The AXIe 3.1 triggering capabilities allow for Pattern Based Synchronization techniques leading to better test repeatability and fast test times," said David Oka, VP Engineering, Test Evolution. "The routing of test signals through the backplane and rear transition modules provides for cable free test fixtures, a major benefit for test repeatability."
The System Module is compatible with National Instrument’s LabVIEW and TestStand, and the IVI software standard which are all widely used for device characterization, and easily co-exists with PXI and LXI instruments and chassis.
This capability allows for ATE instruments to be used for characterization, and later the same instruments and test programs can be used in production, for both a cost and time savings for semiconductor device vendors.
The System Module is available now.
The new System Module brings to the semiconductor industry one of the building blocks of an open hardware and software platform for both device characterization and production test, using common instruments and test programs for lower cost and faster time to volume production.
"The AXIe standard enables high performance instrumentation in an open standard modular solution. This will enable a renaissance in low cost focused test solutions in semiconductor test applications," said Lev Alperovich, president,Test Evolution. "The System Module is the first in a series of products that will give customers the tools to improve productivity, time to market, and ultimately better profitability.”
The System Module is a single slot AXIe 3.1-compliant board. The System Module supports all functionality of AXIe 3.1 standard including robust backplane and front-panel triggering for inter-instrument control, 250 MB/s PCI Express to all slots, in-system calibration support, and controllable load board power supplies. The System Module, with its rear transition connector provides for cable-less connections to semiconductor devices in both characterization and production testing.
"The AXIe 3.1 triggering capabilities allow for Pattern Based Synchronization techniques leading to better test repeatability and fast test times," said David Oka, VP Engineering, Test Evolution. "The routing of test signals through the backplane and rear transition modules provides for cable free test fixtures, a major benefit for test repeatability."
The System Module is compatible with National Instrument’s LabVIEW and TestStand, and the IVI software standard which are all widely used for device characterization, and easily co-exists with PXI and LXI instruments and chassis.
This capability allows for ATE instruments to be used for characterization, and later the same instruments and test programs can be used in production, for both a cost and time savings for semiconductor device vendors.
The System Module is available now.
Shocking Technologies obtains UL certification
SAN JOSE, USA: Shocking Technologies, Inc. has received notification from Underwriters Laboratories (UL) that it has been awarded 94V-0 certification for its XStaticTM100 product, a voltage switchable dielectric (VSD) material.
Lex Kosowsky, president and CEO of Shocking Technologies, said: “The UL certification is an important milestone that opens the market for us and gives our customers the added confidence to quickly implement our solution. This is well aligned with our high volume manufacturing roll-out in Q1, 2011.”
Shocking Technologies is a privately held company developing Voltage Switchable Dielectric (VSD) materials for electrostatic discharge (ESD) protection in consumer electronic devices.
A VSD material is a polymer nano-composite that behaves as an insulator (dielectric) during normal operation, and becomes conductive in the presence of ESD events. This unique capability enables comprehensive ESD protection at a fraction of the cost of competing, less effective methods.
The company is currently delivering embedded ESD protection within PCBs and semiconductor packages.
Lex Kosowsky, president and CEO of Shocking Technologies, said: “The UL certification is an important milestone that opens the market for us and gives our customers the added confidence to quickly implement our solution. This is well aligned with our high volume manufacturing roll-out in Q1, 2011.”
Shocking Technologies is a privately held company developing Voltage Switchable Dielectric (VSD) materials for electrostatic discharge (ESD) protection in consumer electronic devices.
A VSD material is a polymer nano-composite that behaves as an insulator (dielectric) during normal operation, and becomes conductive in the presence of ESD events. This unique capability enables comprehensive ESD protection at a fraction of the cost of competing, less effective methods.
The company is currently delivering embedded ESD protection within PCBs and semiconductor packages.
Genmark expands technical service network in South Korea
SAN FRANCISCO, USA: Genmark Automation Inc., a global leader in tool and factory automation solutions for the semiconductor manufacturing equipment industry, announced the expansion of its Service and Sales locations in Asia to include a new service and sales facility in Gyeonggi-Do, South Korea, due to the continuous increase in demand for the company’s products and services worldwide.
“Our new facility in Gyeonggi-Do, South Korea will enable us to respond rapidly to the needs of our customers by providing on-site fab support by trained factory personnel, access to a spare parts depot, direct sales and customer service/support 24 hours a day, seven days a week,” said Greg Liebersbach, Director of Service for USA and Asia markets at Genmark Automation.
“The opening of a direct office in South Korea reflects our on-going commitment to deliver superior customer service, sales and field support, helping customers improve and maintain yields, boost productivity and improve overall equipment efficiency.”
“Our new facility in Gyeonggi-Do, South Korea will enable us to respond rapidly to the needs of our customers by providing on-site fab support by trained factory personnel, access to a spare parts depot, direct sales and customer service/support 24 hours a day, seven days a week,” said Greg Liebersbach, Director of Service for USA and Asia markets at Genmark Automation.
“The opening of a direct office in South Korea reflects our on-going commitment to deliver superior customer service, sales and field support, helping customers improve and maintain yields, boost productivity and improve overall equipment efficiency.”
Silego announces GreenPAK Designer for Mac
SANTA CLARA, USA: Silego Technology has released its new GreenPAK Designer for Mac software.
This version of Silego’s GreenPAK Designer was created to provide Apple Mac users with a graphical schematic design tool for the GreenPAK device (a one-time programmable mixed-signal micro-FPGA).
The GreenPAK Designer for Mac software is extremely intuitive for circuit designers, due to the graphical interface and circuit design requiring no programming language or compiler. GreenPAK Designer works in conjunction with Silego’s GreenPAK Programmer (a USB-based programming stick) to give circuit designers the ability to create custom highly integrated circuit designs.
“The development of GreenPAK Designer for Mac is part of Silego’s focus to bring innovative solutions to all electronic designers. The concepts of GreenPAK Designer and the USB GreenPAK programming stick allow engineers the ability to create, program and test stand alone circuit designs in mere minutes,” said Aron Cooperman, product marketing manager at Silego. “To create a circuit design in GreenPAK Designer for Mac is as simple making a block diagram on a piece of paper for an engineer.”
GreenPAK Designer for Mac is available for download free of charge at Silego’s website.
This version of Silego’s GreenPAK Designer was created to provide Apple Mac users with a graphical schematic design tool for the GreenPAK device (a one-time programmable mixed-signal micro-FPGA).
The GreenPAK Designer for Mac software is extremely intuitive for circuit designers, due to the graphical interface and circuit design requiring no programming language or compiler. GreenPAK Designer works in conjunction with Silego’s GreenPAK Programmer (a USB-based programming stick) to give circuit designers the ability to create custom highly integrated circuit designs.
“The development of GreenPAK Designer for Mac is part of Silego’s focus to bring innovative solutions to all electronic designers. The concepts of GreenPAK Designer and the USB GreenPAK programming stick allow engineers the ability to create, program and test stand alone circuit designs in mere minutes,” said Aron Cooperman, product marketing manager at Silego. “To create a circuit design in GreenPAK Designer for Mac is as simple making a block diagram on a piece of paper for an engineer.”
GreenPAK Designer for Mac is available for download free of charge at Silego’s website.
ST unveils true multi-touch technology for slimmer smartphones
INDIA: The next generations of smartphones are unlikely to become much smaller, but they could be slimmer and smarter using a single-chip widescreen capacitive touchscreen controller announced by STMicroelectronics, a leading provider of ICs for mobile and consumer products.
Complementing ST’s leadership in gyroscopes and accelerometers to provide human interface solutions, the S-Touch FingerTip controller offers true multi-touch capability with unlimited simultaneous touches. The FingerTip also enhances multi-touch actions such as pinch-to-zoom and supports stylus operations, enabling a better user experience.
The FingerTip controller’s patented analog IP provides high signal-to-noise-ratio performance with high scan speed that allows robust and fast touch performance for the user. It also offers the industry’s greatest number of channels, allowing higher touch resolution. Its ultra-low power consumption delivers longer battery life.
Advanced noise cancellation makes this the first device of its kind to support the latest on-cell LCD technology without requiring a ground shielding layer between the display and the touch sensor. This feature allows smartphones to have thinner touchscreen LCD modules with enhanced image quality and reduced assembly costs.
Its high resistance to electrostatic discharge (ESD) makes the S-Touch FingerTip touch controller ideal for use in consumer smartphones. Auto-tuning and self calibration features will reduce external components and support a wide range of touchscreen panels. With a 3x3mm low-profile chip-size package, the FingerTip is the industry’s smallest multi-touch controller.
Main features of S-Touch FingerTip:
* n-cell integrated support for thinner displays.
* High SNR.
* Ultra-low-power consumption in touch-ready mode, saving battery life.
* Industry’s highest number of nodes: 288 (18x16).
* 8kV HBM ESD protection.
* Industry’s smallest package.
FingerTip devices are available in two packages, a QFN 56 (7mm x 7mm) and an ultra-small flip-chip CSP 49 (3x3mm), already available for design-ins and mass-production. Budgetary pricing for S-Touch FingerTip is available to OEM customers on request.
Complementing ST’s leadership in gyroscopes and accelerometers to provide human interface solutions, the S-Touch FingerTip controller offers true multi-touch capability with unlimited simultaneous touches. The FingerTip also enhances multi-touch actions such as pinch-to-zoom and supports stylus operations, enabling a better user experience.
The FingerTip controller’s patented analog IP provides high signal-to-noise-ratio performance with high scan speed that allows robust and fast touch performance for the user. It also offers the industry’s greatest number of channels, allowing higher touch resolution. Its ultra-low power consumption delivers longer battery life.
Advanced noise cancellation makes this the first device of its kind to support the latest on-cell LCD technology without requiring a ground shielding layer between the display and the touch sensor. This feature allows smartphones to have thinner touchscreen LCD modules with enhanced image quality and reduced assembly costs.
Its high resistance to electrostatic discharge (ESD) makes the S-Touch FingerTip touch controller ideal for use in consumer smartphones. Auto-tuning and self calibration features will reduce external components and support a wide range of touchscreen panels. With a 3x3mm low-profile chip-size package, the FingerTip is the industry’s smallest multi-touch controller.
Main features of S-Touch FingerTip:
* n-cell integrated support for thinner displays.
* High SNR.
* Ultra-low-power consumption in touch-ready mode, saving battery life.
* Industry’s highest number of nodes: 288 (18x16).
* 8kV HBM ESD protection.
* Industry’s smallest package.
FingerTip devices are available in two packages, a QFN 56 (7mm x 7mm) and an ultra-small flip-chip CSP 49 (3x3mm), already available for design-ins and mass-production. Budgetary pricing for S-Touch FingerTip is available to OEM customers on request.
Carl Zeiss and Synopsys collaborate on in-die registration metrology for photomask manufacturing
JENA, GERMANY & MOUNTAIN VIEW, USA: Carl Zeiss SMS GmbH, a leading supplier for photomask metrology and repair tools and Synopsys Inc. announced a collaboration to support the ZEISS tool family for in-die metrology solutions for the 32-nanometer (nm) technology node and below.
Synopsys will offer support for ZEISS' PROVE, the next-generation registration metrology tool, through Synopsys' CATS, the technology-leading mask data preparation solution. Using CATS as the data preparation engine, mask engineers using PROVE can benefit from improved efficiency and usability of a registration metrology system that meets stringent overlay accuracy requirements.
Strong optical proximity correction and double patterning techniques, required to extend 193-nm lithography to the next technology nodes, demand greater photomask pattern placement accuracy.
The new PROVE system meets these increased demands with its groundbreaking concept of 193-nm illumination optics. It delivers an in-die metrology capability for measurement of the smallest production features without placing registration marks, enabling mask makers to measure and analyze registration in critical areas on the mask.
The new CATS module, currently in limited customer availability and generally available in March 2011, enables a fast, efficient and fully automated flow for the setup of photomask metrology jobs.
Using the industry standard open formats OASIS.MASK and XML, advanced marking capabilities and the PROVE two-dimensional (2D) correlation method, CATS offers a significant enhancement to conventional image analysis schemes.
The innovative method compares 2D design clips of the mask provided by CATS with images on the mask captured by PROVE, resulting in higher measurement accuracy compared to standard methods using 1D measurements based on edges only.
Dr. Dirk Beyer, product manager for PROVE at Carl Zeiss SMS GmbH, said: "With Synopsys' long-term experience in mask data preparation and Carl Zeiss' know-how in in-die metrology, the new CATS module with its exciting capabilities will significantly help to reduce mask registration errors on arbitrary production features."
Registration errors can now be quantified for each mask with no resolution limitations, giving mask manufacturers a completely new tool for reducing placement errors in double patterning and mask-to-mask overlay.
"Synopsys' collaboration with Carl Zeiss exemplifies our commitment to offering comprehensive lithography, inspection and metrology solutions to the mask manufacturing market," said Fabio Angelillis, vice president of engineering for Synopsys' Silicon Engineering Group. "By extending CATS to support PROVE, we are delivering higher quality metrology solutions to our customers at the 32-nanometer technology node and below."
Synopsys will offer support for ZEISS' PROVE, the next-generation registration metrology tool, through Synopsys' CATS, the technology-leading mask data preparation solution. Using CATS as the data preparation engine, mask engineers using PROVE can benefit from improved efficiency and usability of a registration metrology system that meets stringent overlay accuracy requirements.
Strong optical proximity correction and double patterning techniques, required to extend 193-nm lithography to the next technology nodes, demand greater photomask pattern placement accuracy.
The new PROVE system meets these increased demands with its groundbreaking concept of 193-nm illumination optics. It delivers an in-die metrology capability for measurement of the smallest production features without placing registration marks, enabling mask makers to measure and analyze registration in critical areas on the mask.
The new CATS module, currently in limited customer availability and generally available in March 2011, enables a fast, efficient and fully automated flow for the setup of photomask metrology jobs.
Using the industry standard open formats OASIS.MASK and XML, advanced marking capabilities and the PROVE two-dimensional (2D) correlation method, CATS offers a significant enhancement to conventional image analysis schemes.
The innovative method compares 2D design clips of the mask provided by CATS with images on the mask captured by PROVE, resulting in higher measurement accuracy compared to standard methods using 1D measurements based on edges only.
Dr. Dirk Beyer, product manager for PROVE at Carl Zeiss SMS GmbH, said: "With Synopsys' long-term experience in mask data preparation and Carl Zeiss' know-how in in-die metrology, the new CATS module with its exciting capabilities will significantly help to reduce mask registration errors on arbitrary production features."
Registration errors can now be quantified for each mask with no resolution limitations, giving mask manufacturers a completely new tool for reducing placement errors in double patterning and mask-to-mask overlay.
"Synopsys' collaboration with Carl Zeiss exemplifies our commitment to offering comprehensive lithography, inspection and metrology solutions to the mask manufacturing market," said Fabio Angelillis, vice president of engineering for Synopsys' Silicon Engineering Group. "By extending CATS to support PROVE, we are delivering higher quality metrology solutions to our customers at the 32-nanometer technology node and below."
SMIC to invest in Wuhan Xinxin writing a new chapter in scientific development
WUHAN, CHINA: The Wuhan East Lake Hi-Tech Development Zone Administrative Committee and Semiconductor Manufacturing International Corp. (SMIC) have signed a co-operation framework agreement in Wuhan’s East Lake Hotel. Both parties agreed to co-operate and jointly invest in the 12-inch wafer production facilities of Wuhan Xinxin Semiconductor Manufacturing Corp. (Wuhan Xinxin) through cash injection.
The official signing ceremony was attended by the President of the Chinese Academy of Engineering Zhou Ji; officials from the National Development and Reform Commission, China Development Bank, and Hubei Province; Wuhan City Party Secretary Yang Song; Wuhan Mayor Ruan Chengfa; SMIC Chairman Jiang Shangzhou; SMIC president and C.E.O. David N.K. Wang; and others.
SMIC began its cooperation with Wuhan City in early 2006 when its government funded and constructed Wuhan Xinxin and engaged SMIC to manage it. Wuhan Xinxin commenced production in September 2008, with its fab construction and operations meeting global industry standards.
The signing of this new agreement strengthens the commitment between SMIC’s new management team and the Wuhan government to move towards greater expansion and development.
The co-operation framework agreement proposes a possible joint venture driven by corporate responsibility and profitability, which will focus on 65-40 nanometer integrated circuits with a goal of achieving a production capacity of 45,000 wafers per month within three years of its establishment.
Capacity planning for this new phase will be consistent with industry standards for profitable development, with products and technology driven by market demand.
This co-operation will benefit both parties and serve as a strategic component in SMIC’s expansion plan over the next five years. It also will become a key contributor to the Chinese and global semiconductor industries, as a reliable platform for high-end chip manufacturing.
Through this agreement, SMIC and Wuhan City will collaborate extensively in areas such as talent development, chip design, and supply chain improvement, to promote the economic development of Wuhan’s “Optics Valley” and upgrade Hubei Province’s information and technology industry.
As East Lake High-tech Zone is developing its strategy to build the “National Innovation Model Area” and “China Optical Valley,” this cooperation will become an innovation engine to drive their development.
The official signing ceremony was attended by the President of the Chinese Academy of Engineering Zhou Ji; officials from the National Development and Reform Commission, China Development Bank, and Hubei Province; Wuhan City Party Secretary Yang Song; Wuhan Mayor Ruan Chengfa; SMIC Chairman Jiang Shangzhou; SMIC president and C.E.O. David N.K. Wang; and others.
SMIC began its cooperation with Wuhan City in early 2006 when its government funded and constructed Wuhan Xinxin and engaged SMIC to manage it. Wuhan Xinxin commenced production in September 2008, with its fab construction and operations meeting global industry standards.
The signing of this new agreement strengthens the commitment between SMIC’s new management team and the Wuhan government to move towards greater expansion and development.
The co-operation framework agreement proposes a possible joint venture driven by corporate responsibility and profitability, which will focus on 65-40 nanometer integrated circuits with a goal of achieving a production capacity of 45,000 wafers per month within three years of its establishment.
Capacity planning for this new phase will be consistent with industry standards for profitable development, with products and technology driven by market demand.
This co-operation will benefit both parties and serve as a strategic component in SMIC’s expansion plan over the next five years. It also will become a key contributor to the Chinese and global semiconductor industries, as a reliable platform for high-end chip manufacturing.
Through this agreement, SMIC and Wuhan City will collaborate extensively in areas such as talent development, chip design, and supply chain improvement, to promote the economic development of Wuhan’s “Optics Valley” and upgrade Hubei Province’s information and technology industry.
As East Lake High-tech Zone is developing its strategy to build the “National Innovation Model Area” and “China Optical Valley,” this cooperation will become an innovation engine to drive their development.
Friday, October 29, 2010
Synopsys' silicon-proven DesignWare HDMI 1.4a Tx controller and PHY IP receive HDMI certification
MOUNTAIN VIEW, USA: Synopsys Inc. announced that Synopsys' DesignWare High-Definition Multimedia Interface (HDMI) 1.4a Transmitter (Tx) digital controller and PHY IP solutions in the 40-nanometer (nm) process node have achieved certification from an HDMI Authorized Training Center (ATC).
The DesignWare HDMI PHY IP achieved HDMI 1.4a compliance by passing all process, voltage and temperature variation tests, which are key certification requirements for environmental robustness.
Synopsys' fully compliant HDMI 1.4a Tx solution is now available in more than 10 process technologies, ranging from 90-nm to 40-nm. With support for the latest HDMI 1.4a specification features such as all eight 3D formats, HDMI Ethernet and Audio Return Channel (HEAC) and real-time content signaling, the DesignWare HDMI 1.4a Tx controller and PHY IP enable system-on-chip (SoC) designers and device manufacturers to quickly incorporate advanced functionality into their multimedia source applications with less risk and improved time-to-market.
The DesignWare HDMI 1.4a Tx IP solution includes a comprehensive set of IP deliverables such as baseline software drivers for system development, which help designers quickly embed this complex interface into next-generation multimedia SoCs. It also includes many performance features designers need to create a state-of-the-art viewing experience, including:
* Support for all eight 3D formats, such as side-by-side (full and half) and frame/line/field alternative, providing extended flexibility for system designers.
An integrated HEAC block simplifies the connectivity between internet-enabled digital home devices by enabling the transfer of Ethernet and audio frames through a single HDMI cable.
* Real-time content signaling capability enables televisions to automatically optimize the picture setting with no user intervention.
* Support for 4K x 2K resolution delivers up to four times the resolution of 1080p (Quad HD technology), providing the same resolution as state-of-the-art digital cinema.
"We tested Synopsys DesignWare HDMI 1.4 IP against the stringent physical layer requirements of the HDMI specification and found that it passes with outstanding margin. This demonstrates Synopsys' deep understanding of the HDMI specification," said Quintin Anderson, COO of Granite River Labs.
"Pre-compliance testing gives adopters confidence that their product will pass official compliance testing the first time, avoiding costly product delays and re-testing expenses. Passing compliance gives designers added confidence that the IP is robust and interoperable with existing HDMI products while providing support for the latest functionalities such as HEAC and 3D formatting."
"HDMI is enabled in more than 1.5 billion consumer devices and is now gaining significant traction in delivering 3D functionality in digital home theater systems, gaming consoles and other portable multimedia devices," said John Koeter, VP of Marketing for the Solutions Group at Synopsys. "Synopsys' high-quality, silicon-proven DesignWare HDMI 1.4a IP solution is optimized for small area, low power and high performance, enabling designers to quickly incorporate the latest functionality with less risk."
The DesignWare HDMI 1.4a Tx digital controller and PHY IP solution is available now for 90-nm to 40-nm process nodes.
The DesignWare HDMI PHY IP achieved HDMI 1.4a compliance by passing all process, voltage and temperature variation tests, which are key certification requirements for environmental robustness.
Synopsys' fully compliant HDMI 1.4a Tx solution is now available in more than 10 process technologies, ranging from 90-nm to 40-nm. With support for the latest HDMI 1.4a specification features such as all eight 3D formats, HDMI Ethernet and Audio Return Channel (HEAC) and real-time content signaling, the DesignWare HDMI 1.4a Tx controller and PHY IP enable system-on-chip (SoC) designers and device manufacturers to quickly incorporate advanced functionality into their multimedia source applications with less risk and improved time-to-market.
The DesignWare HDMI 1.4a Tx IP solution includes a comprehensive set of IP deliverables such as baseline software drivers for system development, which help designers quickly embed this complex interface into next-generation multimedia SoCs. It also includes many performance features designers need to create a state-of-the-art viewing experience, including:
* Support for all eight 3D formats, such as side-by-side (full and half) and frame/line/field alternative, providing extended flexibility for system designers.
An integrated HEAC block simplifies the connectivity between internet-enabled digital home devices by enabling the transfer of Ethernet and audio frames through a single HDMI cable.
* Real-time content signaling capability enables televisions to automatically optimize the picture setting with no user intervention.
* Support for 4K x 2K resolution delivers up to four times the resolution of 1080p (Quad HD technology), providing the same resolution as state-of-the-art digital cinema.
"We tested Synopsys DesignWare HDMI 1.4 IP against the stringent physical layer requirements of the HDMI specification and found that it passes with outstanding margin. This demonstrates Synopsys' deep understanding of the HDMI specification," said Quintin Anderson, COO of Granite River Labs.
"Pre-compliance testing gives adopters confidence that their product will pass official compliance testing the first time, avoiding costly product delays and re-testing expenses. Passing compliance gives designers added confidence that the IP is robust and interoperable with existing HDMI products while providing support for the latest functionalities such as HEAC and 3D formatting."
"HDMI is enabled in more than 1.5 billion consumer devices and is now gaining significant traction in delivering 3D functionality in digital home theater systems, gaming consoles and other portable multimedia devices," said John Koeter, VP of Marketing for the Solutions Group at Synopsys. "Synopsys' high-quality, silicon-proven DesignWare HDMI 1.4a IP solution is optimized for small area, low power and high performance, enabling designers to quickly incorporate the latest functionality with less risk."
The DesignWare HDMI 1.4a Tx digital controller and PHY IP solution is available now for 90-nm to 40-nm process nodes.
Icera, Teleca to develop Android RIL for Icera smartphone platform
BRISTOl, UK & MALMO, SWEDEN: Icera Inc., the mobile broadband semiconductor company, and Teleca, a leading supplier of solutions and services to the mobile industry, announced that Teleca has been selected to help develop an Android radio interface layer for Icera’s Espresso 4xx smartphone platform family based on its Livanto ICE806x baseband chips.
Pete Cumming, Icera´s VP Systems Engineering said: “Teleca´s extensive experience in developing Android solutions along with their proven track record for Android RIL, in particular, made them a compelling partner. The Android RIL being developed by Teleca will be a key component in Icera’s plan to launch Android solutions in 2011. We are looking forward to Teleca providing integration and customization support to our customers.”
“With a highly differentiated offering in software defined modems, Icera is emerging as a strong player in the highly competitive semiconductor market,” said Andrew Till, SVP Solutions Marketing, at Teleca.
“We expect this to be the beginning of a long term relationship. Teleca has experienced very strong growth in its Android based solution sales to both the traditional mobile device market and to the consumer electronics and automotive sectors. This latest project adds a new and significant client to Teleca´s customer base and further strengthens Teleca´s leadership in developing Android RIL implementations for new platforms and products.”
Pete Cumming, Icera´s VP Systems Engineering said: “Teleca´s extensive experience in developing Android solutions along with their proven track record for Android RIL, in particular, made them a compelling partner. The Android RIL being developed by Teleca will be a key component in Icera’s plan to launch Android solutions in 2011. We are looking forward to Teleca providing integration and customization support to our customers.”
“With a highly differentiated offering in software defined modems, Icera is emerging as a strong player in the highly competitive semiconductor market,” said Andrew Till, SVP Solutions Marketing, at Teleca.
“We expect this to be the beginning of a long term relationship. Teleca has experienced very strong growth in its Android based solution sales to both the traditional mobile device market and to the consumer electronics and automotive sectors. This latest project adds a new and significant client to Teleca´s customer base and further strengthens Teleca´s leadership in developing Android RIL implementations for new platforms and products.”
Microprocessor trends beyond 2010: Follow the money
PHOENIX, USA: The MPU market is projected to grow 13.6% in 2011, reaching $45.7 billion in revenue. Semico expects to see continued sustained growth into 2011.
The MPU market affects a variety of different end-use segments, and to understand this above-average growth, Semico has examined the technological trends driving the market today.
Semico's new report, Microprocessor Trends Beyond 2010: Follow the Money discusses the MPU market and the applications within it. In particular, this report delves into all of the various computing form factors and non-computing applications that is driving the Micro Logic market.
For example, the majority of the 13.6 percent growth is due to the computing segment, which dominates the MPU Market. Consequently, the 80x86 architecture accounts for the majority of the sales and unit volumes and this report analyzes the roadmaps for both Intel and AMD.
The MPU market affects a variety of different end-use segments, and to understand this above-average growth, Semico has examined the technological trends driving the market today.
Semico's new report, Microprocessor Trends Beyond 2010: Follow the Money discusses the MPU market and the applications within it. In particular, this report delves into all of the various computing form factors and non-computing applications that is driving the Micro Logic market.
For example, the majority of the 13.6 percent growth is due to the computing segment, which dominates the MPU Market. Consequently, the 80x86 architecture accounts for the majority of the sales and unit volumes and this report analyzes the roadmaps for both Intel and AMD.
Strong 2011 SSD shipment growth likely with higher popularity among consumers
TAIWAN: NAND Flash vendors have put strong expectation in SSD (Solid-State Drive) since the unit consumption is several times higher than embedded products as well as memory card and UFD.
That is, SSD has great potential in terms of NAND Flash consumption. From Consumer perspective, SSD transmission speed is twice faster than traditional HDD (Hard-Disk Drive) and featured with better power consumption and anti-shocking design.
With the potential growing demand from High-Definition multimedia and large files, SSD demand will be steadily pulled up given the falling Flash price in coming future.
SSD price did not fall significantly in 2009 and 2010 since NAND Flash has sustained in the stable higher level. Besides the application in higher server market, industrial/military market and high-end commercial notebook, regular consumer SSD is limited to the retail market while average capacity is recorded in 32GB/40GB.
SSD vendors planed their strategy focus by leveraging SSD as the main system drive and implementing traditional HDD as the data storage device. With the 2xnm technology migration in 4Q10 among NAND Flash vendors, we expect the cost advantage from technology migration can reflect in the SSD price. Since SSD product feature is quite attractive to consumers, the falling SSD price will effectively trigger the purchase willingness.
Given the consideration of higher penetration rate in system product and demand from retail market, DRAMeXchange forecast 2011 SSD shipment will increase 150 percent YoY to near 15 million units.
That is, SSD has great potential in terms of NAND Flash consumption. From Consumer perspective, SSD transmission speed is twice faster than traditional HDD (Hard-Disk Drive) and featured with better power consumption and anti-shocking design.
With the potential growing demand from High-Definition multimedia and large files, SSD demand will be steadily pulled up given the falling Flash price in coming future.
SSD price did not fall significantly in 2009 and 2010 since NAND Flash has sustained in the stable higher level. Besides the application in higher server market, industrial/military market and high-end commercial notebook, regular consumer SSD is limited to the retail market while average capacity is recorded in 32GB/40GB.
SSD vendors planed their strategy focus by leveraging SSD as the main system drive and implementing traditional HDD as the data storage device. With the 2xnm technology migration in 4Q10 among NAND Flash vendors, we expect the cost advantage from technology migration can reflect in the SSD price. Since SSD product feature is quite attractive to consumers, the falling SSD price will effectively trigger the purchase willingness.
Given the consideration of higher penetration rate in system product and demand from retail market, DRAMeXchange forecast 2011 SSD shipment will increase 150 percent YoY to near 15 million units.
Gennum delivers world’s fastest crosspoint switch
BURLINGTON, CANADA: Gennum Corp., a leading supplier of high-speed optical, analog and mixed-signal semiconductor solutions, has introduced the industry’s first 2x2 crosspoint switch capable of supporting data rates in excess of 14 gigabits per second (Gbps) per port.
In addition, the new GX4002 crosspoint is the first to integrate a CDR (clock and data recovery), providing a single-chip solution that satisfies the high-speed signal integrity requirements of next-generation equipment used in data center, enterprise and telecommunications networks. The crosspoint is ideal for use as a redundancy switch, repeater or high-speed loop-back monitor.
“Gennum has applied its rich heritage in advanced signal integrity technology to achieve data rates never before possible on a crosspoint switch,” said Martin Rofheart, senior VP and GM of Analog & Mixed-Signal Products at Gennum.
“We have also advanced crosspoint functionality with the integration of our proven CDR technology, applying innovative signal conditioning techniques to ensure high quality, long distance signal transmission at these breakthrough speeds. Our integrated solution reduces chip count and complexity, saving both BOM cost and board space—all the while delivering the world’s fastest crosspoint.”
The device provides the speed, bandwidth and signal integrity required to support network equipment based on standards like 10 Gbps SONET (OC-192); 10 Gbps Ethernet; 16 Gbps Fibre Channel; and Infiniband DDR (double data rate), QDR (quad data rate) and FDR (fourteen data rate).
With an integrated CDR that uses input equalization and output de-emphasis for signal conditioning, the GX4002 reduces jitter and allows high-speed signal transmission across longer distances. Used to restore and clean digital signals at extremely high speeds, the integrated CDR “resets” the jitter budget, effectively erasing the signal distortion that can occur during transmission across “lossy” media such as copper cables and backplanes. The GX4002 provides unprecedented output jitter of 7 picoseconds, peak-to-peak (ps p-p).
In redundancy switching applications, the two-port switch allows designers to create two identical 14 Gbps paths and use one channel for protection switching in the event of a network failure. An alternate traffic path can be switched over and operational within 100 microseconds for OC-192/OTU2 data rates.
The GX4002 can also be used as a “redriver” or “repeater” to extend the distance that a signal can be reliably carried across a backplane or I/O card. Finally, the device can be used for high-speed loop-back support, enabling designers to monitor signal quality and diagnose potential network problems.
As an asynchronous switch, the GX4002 can support different data rates or protocols on each port. A non-blocking design allows connection of any input to any output for maximum design flexibility.
In addition, the new GX4002 crosspoint is the first to integrate a CDR (clock and data recovery), providing a single-chip solution that satisfies the high-speed signal integrity requirements of next-generation equipment used in data center, enterprise and telecommunications networks. The crosspoint is ideal for use as a redundancy switch, repeater or high-speed loop-back monitor.
“Gennum has applied its rich heritage in advanced signal integrity technology to achieve data rates never before possible on a crosspoint switch,” said Martin Rofheart, senior VP and GM of Analog & Mixed-Signal Products at Gennum.
“We have also advanced crosspoint functionality with the integration of our proven CDR technology, applying innovative signal conditioning techniques to ensure high quality, long distance signal transmission at these breakthrough speeds. Our integrated solution reduces chip count and complexity, saving both BOM cost and board space—all the while delivering the world’s fastest crosspoint.”
The device provides the speed, bandwidth and signal integrity required to support network equipment based on standards like 10 Gbps SONET (OC-192); 10 Gbps Ethernet; 16 Gbps Fibre Channel; and Infiniband DDR (double data rate), QDR (quad data rate) and FDR (fourteen data rate).
With an integrated CDR that uses input equalization and output de-emphasis for signal conditioning, the GX4002 reduces jitter and allows high-speed signal transmission across longer distances. Used to restore and clean digital signals at extremely high speeds, the integrated CDR “resets” the jitter budget, effectively erasing the signal distortion that can occur during transmission across “lossy” media such as copper cables and backplanes. The GX4002 provides unprecedented output jitter of 7 picoseconds, peak-to-peak (ps p-p).
In redundancy switching applications, the two-port switch allows designers to create two identical 14 Gbps paths and use one channel for protection switching in the event of a network failure. An alternate traffic path can be switched over and operational within 100 microseconds for OC-192/OTU2 data rates.
The GX4002 can also be used as a “redriver” or “repeater” to extend the distance that a signal can be reliably carried across a backplane or I/O card. Finally, the device can be used for high-speed loop-back support, enabling designers to monitor signal quality and diagnose potential network problems.
As an asynchronous switch, the GX4002 can support different data rates or protocols on each port. A non-blocking design allows connection of any input to any output for maximum design flexibility.
IXYS intros DMA150 – new generation of compact, efficient three-phase rectifier bridges
BIEL, SWITZERLAND: IXYS Corp. has announced an addition to the three-phase bridge rectifier module range with a combination of two MINIBLOC (JEDEC: SOT-227B) packages.
“Traditional input power rectification solutions that convert three-phase alternating current (AC) power to direct current (DC) are bulky and do not necessarily make the most efficient use of space and materials and can be expensive,” commented Bradley Green, Vice President of International Sales for IXYS. “With this innovation, IXYS can propose a lower profile, lower cost dual MINIBLOC solution which replaces the need for the historic single large module design.”
The split of a three-phase rectifier bridge into a low-side - DMA150YA1600NA - and a high-side - DMA150YA1600NA - configuration facilitates an output current rating of 150A minimum. When comparing to the existing single module solution of a VUO160-16N07, the 2xDMA system provides a smaller footprint offering which allows a reduction in system size both in height and real estate.
The robustness of the established MINIBLOC package with its screw terminals supports the new compact design for high current rectification. The height of 12 mm allows the engineer to arrange a lower parasitic inductance design. An optimized DCB-substrate fulfils the needs of an improved thermal management with a reliable isolation performance. Required ruggedness against current surge events is guaranteed by an optimized layout and improved contact area for the diode die array.
With the highly sophisticated diode technology of IXYS, the 2xDMA provides an optimized three-phase rectifier module combination for every application where mains rectification is needed such as motor drive, welding and high power conversion.
With the release of the DMA range customers can now utilise the rugged MINIBLOCTM package as a basic building block for many topologies. For example, the DMA in combination with IXA60IF1200NA (XPTTM IGBT with free-wheeling diode) and DSEP2x61-12A (dual HiPerFREDTM fast diodes) can be arranged in a compact design for a converter brake inverter (CBI) system for motor drive applications thereby totally removing the need for soldered connections and the environment impact of such a process.
The DMA range of rectifiers provides high efficiency and high power density at a competitive cost.
“Traditional input power rectification solutions that convert three-phase alternating current (AC) power to direct current (DC) are bulky and do not necessarily make the most efficient use of space and materials and can be expensive,” commented Bradley Green, Vice President of International Sales for IXYS. “With this innovation, IXYS can propose a lower profile, lower cost dual MINIBLOC solution which replaces the need for the historic single large module design.”
The split of a three-phase rectifier bridge into a low-side - DMA150YA1600NA - and a high-side - DMA150YA1600NA - configuration facilitates an output current rating of 150A minimum. When comparing to the existing single module solution of a VUO160-16N07, the 2xDMA system provides a smaller footprint offering which allows a reduction in system size both in height and real estate.
The robustness of the established MINIBLOC package with its screw terminals supports the new compact design for high current rectification. The height of 12 mm allows the engineer to arrange a lower parasitic inductance design. An optimized DCB-substrate fulfils the needs of an improved thermal management with a reliable isolation performance. Required ruggedness against current surge events is guaranteed by an optimized layout and improved contact area for the diode die array.
With the highly sophisticated diode technology of IXYS, the 2xDMA provides an optimized three-phase rectifier module combination for every application where mains rectification is needed such as motor drive, welding and high power conversion.
With the release of the DMA range customers can now utilise the rugged MINIBLOCTM package as a basic building block for many topologies. For example, the DMA in combination with IXA60IF1200NA (XPTTM IGBT with free-wheeling diode) and DSEP2x61-12A (dual HiPerFREDTM fast diodes) can be arranged in a compact design for a converter brake inverter (CBI) system for motor drive applications thereby totally removing the need for soldered connections and the environment impact of such a process.
The DMA range of rectifiers provides high efficiency and high power density at a competitive cost.
Cavium Networks extends MIPS architecture license
SUNNYVALE, USA: MIPS Technologies Inc., a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, announced that long-time MIPS licensee Cavium Networks has reaffirmed its commitment to the MIPS architecture by renewing its license of the high-performance MIPS64 architecture.
Rajiv Khemani, VP and GM, Networking and Communications, Cavium Networks, said: "We are pleased to reaffirm our commitment to the ultra-high performance MIPS64 architecture for future generations of our groundbreaking OCTEON products. As Cavium's solutions gain increasing traction for a wide range of networking and communications applications, we will continue to leverage the MIPS architecture, which delivers high performance, energy efficiency and an unsurpassed ecosystem for networking and communications."
Art Swift, vice president of marketing and business development, MIPS Technologies, added: "Cavium Networks takes full advantage of the flexibility afforded by a MIPS architecture license, developing some of the industry's highest performance and most advanced multicore processors for networking, wireless and storage. The efficient and high-performance MIPS architecture is increasingly the architecture of choice for these applications, especially as data and video traffic increases across wired and mobile networks. We look forward to working closely with Cavium as its MIPS-Based solutions gain even stronger market traction."
The MIPS64 architecture provides a high level of performance for applications including networking and computing. Incorporating powerful features, standardizing privileged mode instructions, supporting past ISAs and providing an upgrade path from the MIPS32 architecture, the MIPS64 architecture provides a solid high-performance foundation for future MIPS processor-based development.
Cavium's OCTEON multi-core processor family, based on the MIPS64 architecture, offers a scalable, high-performance, low-power solution for intelligent networking applications ranging from 100Mbps to 40Gbps.
The OCTEON processors have been widely adopted in mainstream and leading-performance routers, switches, storage networking equipment, security appliances, data-center equipment, and a broad range of 3G, WiMAX and LTE infrastructure equipment including base stations, radio network controllers, aggregation systems, mobile subscriber gateways and deep packet inspection (DPI) equipment.
Rajiv Khemani, VP and GM, Networking and Communications, Cavium Networks, said: "We are pleased to reaffirm our commitment to the ultra-high performance MIPS64 architecture for future generations of our groundbreaking OCTEON products. As Cavium's solutions gain increasing traction for a wide range of networking and communications applications, we will continue to leverage the MIPS architecture, which delivers high performance, energy efficiency and an unsurpassed ecosystem for networking and communications."
Art Swift, vice president of marketing and business development, MIPS Technologies, added: "Cavium Networks takes full advantage of the flexibility afforded by a MIPS architecture license, developing some of the industry's highest performance and most advanced multicore processors for networking, wireless and storage. The efficient and high-performance MIPS architecture is increasingly the architecture of choice for these applications, especially as data and video traffic increases across wired and mobile networks. We look forward to working closely with Cavium as its MIPS-Based solutions gain even stronger market traction."
The MIPS64 architecture provides a high level of performance for applications including networking and computing. Incorporating powerful features, standardizing privileged mode instructions, supporting past ISAs and providing an upgrade path from the MIPS32 architecture, the MIPS64 architecture provides a solid high-performance foundation for future MIPS processor-based development.
Cavium's OCTEON multi-core processor family, based on the MIPS64 architecture, offers a scalable, high-performance, low-power solution for intelligent networking applications ranging from 100Mbps to 40Gbps.
The OCTEON processors have been widely adopted in mainstream and leading-performance routers, switches, storage networking equipment, security appliances, data-center equipment, and a broad range of 3G, WiMAX and LTE infrastructure equipment including base stations, radio network controllers, aggregation systems, mobile subscriber gateways and deep packet inspection (DPI) equipment.
Advantest's CMOS image sensor test solution lowers test costs with industry-leading 64-DUT parallelism
TOKYO, JAPAN: Advantest Corp. announced that its new CMOS image sensor test solution for its flagship SoC test system, the T2000, will be available beginning November 2010. The new solution enables highly accurate and massively parallel testing for CMOS image sensor devices to help customers lower their test cost.
CMOS image sensors are utilized in consumer electronics such as cellular phones, digital cameras, and video cameras, as well as automotive and other applications. As the widespread adoption of digital lifestyles in emerging economies continues to boom, CMOS image sensor demand is keeping pace.
Rapid improvements in performance, speed, and resolution, as well as the diversification of multifunctional devices integrating CMOS image sensors, has led to increasing downward pressure on production costs. Advantest’s new CMOS image sensor test solution provides customers with 64-DUT parallel test capability – the highest in the industry – to significantly lower the cost of test.
Advantest’s new T2000 CMOS image sensor test solution incorporates a test head configured with a large optical source, and a new CMOS image sensor test module, providing illumination to an area greater than 10x that of Advantest’s previous product.
Most significantly, the solution offers the industry’s first 64-DUT parallel test capability for testing image sensor devices – 8x higher than the previous product – which results in dramatically higher throughput, contributing to significant reductions in test costs.
The large CMOS image sensor measurement area enables customers add custom circuitry for their applications, without compromising parallelism. At 208mm x 252mm, the area of the new test head permits great flexibility in layout creation and device test.
CMOS image sensors are utilized in consumer electronics such as cellular phones, digital cameras, and video cameras, as well as automotive and other applications. As the widespread adoption of digital lifestyles in emerging economies continues to boom, CMOS image sensor demand is keeping pace.
Rapid improvements in performance, speed, and resolution, as well as the diversification of multifunctional devices integrating CMOS image sensors, has led to increasing downward pressure on production costs. Advantest’s new CMOS image sensor test solution provides customers with 64-DUT parallel test capability – the highest in the industry – to significantly lower the cost of test.
Advantest’s new T2000 CMOS image sensor test solution incorporates a test head configured with a large optical source, and a new CMOS image sensor test module, providing illumination to an area greater than 10x that of Advantest’s previous product.
Most significantly, the solution offers the industry’s first 64-DUT parallel test capability for testing image sensor devices – 8x higher than the previous product – which results in dramatically higher throughput, contributing to significant reductions in test costs.
The large CMOS image sensor measurement area enables customers add custom circuitry for their applications, without compromising parallelism. At 208mm x 252mm, the area of the new test head permits great flexibility in layout creation and device test.
Microchip licenses MIPS32 M14K cores for next-gen 32-bit PIC32 MCUs
CHANDLER & SUNNYVALE, USA: Microchip Technology Inc. and MIPS Technologies Inc. announced that Microchip is building on its successful 32-bit PIC32 microcontroller family, which is currently based on the MIPS32 M4K core, by licensing the MIPS32 M14K family of cores from MIPS.
The M14K cores will enable Microchip to further expand its presence in the competitive 32-bit microcontroller market by delivering uncompromised levels of performance and improved code density—critical factors in embedded applications. Additionally, the M14K cores provide cost and performance scalability, while maintaining 100% code compatibility with PIC32 MCUs based on the M4K core.
The higher code density in the M14K core family was achieved through MIPS Technologies’ new microMIPS instruction set architecture (ISA). Executing the microMIPS ISA results in at least a 30 percent code-size reduction with little or no compromise in performance. Additional features of the M14K cores that will be beneficial in the next generation of PIC32 microcontrollers include interrupt-latency improvements and low power consumption.
“Since the successful launch of the rapidly expanding PIC32 family, Microchip has continued to strengthen its strategic partnership with MIPS Technologies,” said Sumit Mitra, vice president of Microchip’s High Performance Microcontroller Division. “In fact, the microcontroller-specific enhancements to the new M14K core were heavily influenced by Microchip’s extensive experience in the embedded market and with the M4K core.”
Art Swift, vice president of marketing and business development, MIPS, said: “We were pleased to work closely with Microchip, our flagship MCU licensee, on the definition of our M14K product line, which includes features and enhancements specifically for MCUs. Because of its clear value proposition, the M14K core is rapidly gaining traction in the market, with more than 17 licenses in the short six months that it has been generally available. We are pleased that Microchip is reaffirming its commitment to the MIPS architecture, which offers superior performance, lower power and more advanced features for MCUs than the competition.”
The M14K cores will enable Microchip to further expand its presence in the competitive 32-bit microcontroller market by delivering uncompromised levels of performance and improved code density—critical factors in embedded applications. Additionally, the M14K cores provide cost and performance scalability, while maintaining 100% code compatibility with PIC32 MCUs based on the M4K core.
The higher code density in the M14K core family was achieved through MIPS Technologies’ new microMIPS instruction set architecture (ISA). Executing the microMIPS ISA results in at least a 30 percent code-size reduction with little or no compromise in performance. Additional features of the M14K cores that will be beneficial in the next generation of PIC32 microcontrollers include interrupt-latency improvements and low power consumption.
“Since the successful launch of the rapidly expanding PIC32 family, Microchip has continued to strengthen its strategic partnership with MIPS Technologies,” said Sumit Mitra, vice president of Microchip’s High Performance Microcontroller Division. “In fact, the microcontroller-specific enhancements to the new M14K core were heavily influenced by Microchip’s extensive experience in the embedded market and with the M4K core.”
Art Swift, vice president of marketing and business development, MIPS, said: “We were pleased to work closely with Microchip, our flagship MCU licensee, on the definition of our M14K product line, which includes features and enhancements specifically for MCUs. Because of its clear value proposition, the M14K core is rapidly gaining traction in the market, with more than 17 licenses in the short six months that it has been generally available. We are pleased that Microchip is reaffirming its commitment to the MIPS architecture, which offers superior performance, lower power and more advanced features for MCUs than the competition.”
Thursday, October 28, 2010
Advantest announces high-speed interface test solution for T2000 test platform
TOKYO, JAPAN: Advantest Corp. has announced the availability of its new high-speed interface test solution for its flagship SoC test system, the T2000.
The new solution is capable of measurement at speeds up to 12.5Gbps and is enabled by the N6010A Serial Port Parametric Test Module manufactured by Agilent Technologies Inc., an industry leader in test and measurement.
Newer versions of interfaces such as PCI Express Gen3 and Ethernet boost data transfer rates many times faster than previous architectures, creating an urgent need for efficient high-speed interface test solutions.
Advantest’s T2000, a flexible, user-configurable test system, in conjunction with the N6010A Serial Port Parametric Test Module from Agilent, integrates rich functionality and a broad toolset, to deliver highly accurate, simultaneous multi-lane testing and characterization at data rates up to 12.5Gbps.
While measurement instruments such as oscilloscopes and Bit Error Rate Testers (BERT) have typically been deployed for characteristics evaluation of high-speed interfaces, the shift to gigabit data rates, multi-lane architectures, and the increasing integration of SoC devices has created significant measurement challenges.
The new high-speed interface test solution from Advantest, combining the widely-accepted performance of the T2000 test system with Agilent’s N6010A module, addresses these challenges by offering parallel test of high-speed, multi-lane interfaces. Synchronous operation comparable to the performance of Advantest’s own T2000 modules delivers best-in-class throughput.
The new solution facilitates system-level evaluation of complex SoC devices with integrated high-speed interfaces.
The new solution is capable of measurement at speeds up to 12.5Gbps and is enabled by the N6010A Serial Port Parametric Test Module manufactured by Agilent Technologies Inc., an industry leader in test and measurement.
Newer versions of interfaces such as PCI Express Gen3 and Ethernet boost data transfer rates many times faster than previous architectures, creating an urgent need for efficient high-speed interface test solutions.
Advantest’s T2000, a flexible, user-configurable test system, in conjunction with the N6010A Serial Port Parametric Test Module from Agilent, integrates rich functionality and a broad toolset, to deliver highly accurate, simultaneous multi-lane testing and characterization at data rates up to 12.5Gbps.
While measurement instruments such as oscilloscopes and Bit Error Rate Testers (BERT) have typically been deployed for characteristics evaluation of high-speed interfaces, the shift to gigabit data rates, multi-lane architectures, and the increasing integration of SoC devices has created significant measurement challenges.
The new high-speed interface test solution from Advantest, combining the widely-accepted performance of the T2000 test system with Agilent’s N6010A module, addresses these challenges by offering parallel test of high-speed, multi-lane interfaces. Synchronous operation comparable to the performance of Advantest’s own T2000 modules delivers best-in-class throughput.
The new solution facilitates system-level evaluation of complex SoC devices with integrated high-speed interfaces.
IR intros radiation hardened solid state relay
EL SEGUNDO, USA: International Rectifier (IR) has introduced a new RAD-Hard solid state relay (SSR) for power bus switching, heater control circuits and battery charging used in high reliability (hi-rel) space-qualified applications.
The RDHA701CD10A2N radiation-hardened DC single pole, single throw-type SSR is designed to improve reliability by replacing traditional electro-mechanical relays that are vulnerable to vibration and shock. The new SSR features very low on-state resistance (RDS (on)) to improve thermal efficiency and is offered in a low profile, hermetically sealed 8-lead ceramic package. Weighing only 0.8 g this surface mountable device uses just 0.37 inches by 0.47 inches of board space.
“IR’s RDHA701CD10A2N SSR improves reliability, reduces footprint and eliminates the need for additional filtering making it an attractive replacement to less reliable, heavier electro-mechanical relays,” said Fred Farris, VP of Sales and Marketing for IR’s HiRel Business Unit.
The new 100 V device is characterized for total dose levels up to 100 krad (Si). Neutron and TID test data are available in the radiation report section on the IR website. The RDHA701CD10A2N is a dual channel device rated at 100 V and 1 A with 1,000 V input to output and channel-to-channel isolation.
Qualification in accordance with space level MIL-PRF-38534 Class “K” is complete and pending DLA approval for a fully compliant device. To support the reliability, MTBF has been calculated according to the space flight method at room temperature per MIL-HDBK-217F and has resulted in a minimum of 22.5 million hour per channel.
Pricing for the RDHA701CD10A2N begins at $831 each in 250-unit quantities. Production orders are available immediately. Prices are subject to change. This product is subject to US export control laws and regulations.
The RDHA701CD10A2N radiation-hardened DC single pole, single throw-type SSR is designed to improve reliability by replacing traditional electro-mechanical relays that are vulnerable to vibration and shock. The new SSR features very low on-state resistance (RDS (on)) to improve thermal efficiency and is offered in a low profile, hermetically sealed 8-lead ceramic package. Weighing only 0.8 g this surface mountable device uses just 0.37 inches by 0.47 inches of board space.
“IR’s RDHA701CD10A2N SSR improves reliability, reduces footprint and eliminates the need for additional filtering making it an attractive replacement to less reliable, heavier electro-mechanical relays,” said Fred Farris, VP of Sales and Marketing for IR’s HiRel Business Unit.
The new 100 V device is characterized for total dose levels up to 100 krad (Si). Neutron and TID test data are available in the radiation report section on the IR website. The RDHA701CD10A2N is a dual channel device rated at 100 V and 1 A with 1,000 V input to output and channel-to-channel isolation.
Qualification in accordance with space level MIL-PRF-38534 Class “K” is complete and pending DLA approval for a fully compliant device. To support the reliability, MTBF has been calculated according to the space flight method at room temperature per MIL-HDBK-217F and has resulted in a minimum of 22.5 million hour per channel.
Pricing for the RDHA701CD10A2N begins at $831 each in 250-unit quantities. Production orders are available immediately. Prices are subject to change. This product is subject to US export control laws and regulations.
Advantest expands market coverage of T2000 test platform with two new power device test solutions
TOKYO, JAPAN: Advantest Corp. announced that two new power device test solutions for its flagship SoC test system, the T2000, will be available from January 2011.
The new Integrated Power Device Test Solution (IPS) incorporates a high-power module, a Matrix Module and a High-Voltage Mixed-Signal Module that deliver a comprehensive, configurable solution for “one-stop” test of multifunctional power ICs such as those used in automotive and consumer electronics.
The solution is supported by a dedicated set of software-tools developed to serve the specific test requirements of this industry. The new IGBT (insulated gate bipolar transistor) test solution is an integrated solution enabling users to force and measure very high currents and voltages for reliability test of the IGBT power devices widely used in automotive and other applications.
Bolstered by the increasing popularity of hybrid and electric automobiles, mixed-signal devices and power management ICs now account for an expanding percentage of the semiconductor market, playing a key role in building greater intelligence and lower power consumption into the process of vehicle development.
Likewise, emerging economies such as BRICs and VISTA, now make up a growing market for electronics and household appliances, adding to the increase in demand for power switches and other widely used types of power ICs. Advantest’s new integrated power device test solutions ( IPS ) meet an urgent need for cost-effective power device reliability test.
Integrated Power Device Test Solution (IPS): features
Advantest’s new integrated power device test solution (IPS) builds upon analog technology inherited during the company’s 2008 acquisition of Credence Systems GmbH (CSG), then a trusted provider of automotive IC test systems. Synergizing this technology with the highly reliable test technology Advantest developed for its own T7700 series mixed-signal testers, the new solution provides easier, more efficient multisite testing of power devices within the open-architecture T2000 environment.
Previous test systems for automotive mixed signal devices and power management ICs required users to configure dedicated modules for each test type, such as DC test, functional test, and time measurement, leading to longer debug times, limitations on multisite test capability, and the proliferation of peripheral circuits on test boards.
The new integrated power device test solution from Advantest combines multiple test functions on one module, enabling multisite test capability 4x greater than previously achieved. This level of functionality becomes more critical as the number of pins on a given device increase in proportion to the number of chips incorporated into automobiles to improve passenger safety, convenience and in-car entertainment.
With Advantest’s new power device test solutions, manufacturers can now customize their test systems with a High-Power Module, a High-Voltage Mixed Signal Module and a Matrix Module to enable devices with a range of pin counts to be tested with an optimal configuration.
IGBT Test Solution: features
With the growing demand for IGBT devices used in power switches and other applications, there is a clear need for the ability to flexibly test varying types of modules in a single platform configuration.
IGBTs, manufactured largely in Japan and the EU, were previously tested with electronic measuring instruments. However, the diversification of IGBT products, including smaller and higher voltage devices, increases the need for a test system capable of easy programming and module changes, while lowering test cost.
Advantest’s new IGBT test solution takes advantage of the flexibility of the T2000 platform to provide the optimal solution for IGBT chip and IPM (integrated power module) test, incorporating a high-power unit and a high-voltage module. It further lowers test cost by enabling parallel test of multiple medium- and low-power devices.
The new Integrated Power Device Test Solution (IPS) incorporates a high-power module, a Matrix Module and a High-Voltage Mixed-Signal Module that deliver a comprehensive, configurable solution for “one-stop” test of multifunctional power ICs such as those used in automotive and consumer electronics.
The solution is supported by a dedicated set of software-tools developed to serve the specific test requirements of this industry. The new IGBT (insulated gate bipolar transistor) test solution is an integrated solution enabling users to force and measure very high currents and voltages for reliability test of the IGBT power devices widely used in automotive and other applications.
Bolstered by the increasing popularity of hybrid and electric automobiles, mixed-signal devices and power management ICs now account for an expanding percentage of the semiconductor market, playing a key role in building greater intelligence and lower power consumption into the process of vehicle development.
Likewise, emerging economies such as BRICs and VISTA, now make up a growing market for electronics and household appliances, adding to the increase in demand for power switches and other widely used types of power ICs. Advantest’s new integrated power device test solutions ( IPS ) meet an urgent need for cost-effective power device reliability test.
Integrated Power Device Test Solution (IPS): features
Advantest’s new integrated power device test solution (IPS) builds upon analog technology inherited during the company’s 2008 acquisition of Credence Systems GmbH (CSG), then a trusted provider of automotive IC test systems. Synergizing this technology with the highly reliable test technology Advantest developed for its own T7700 series mixed-signal testers, the new solution provides easier, more efficient multisite testing of power devices within the open-architecture T2000 environment.
Previous test systems for automotive mixed signal devices and power management ICs required users to configure dedicated modules for each test type, such as DC test, functional test, and time measurement, leading to longer debug times, limitations on multisite test capability, and the proliferation of peripheral circuits on test boards.
The new integrated power device test solution from Advantest combines multiple test functions on one module, enabling multisite test capability 4x greater than previously achieved. This level of functionality becomes more critical as the number of pins on a given device increase in proportion to the number of chips incorporated into automobiles to improve passenger safety, convenience and in-car entertainment.
With Advantest’s new power device test solutions, manufacturers can now customize their test systems with a High-Power Module, a High-Voltage Mixed Signal Module and a Matrix Module to enable devices with a range of pin counts to be tested with an optimal configuration.
IGBT Test Solution: features
With the growing demand for IGBT devices used in power switches and other applications, there is a clear need for the ability to flexibly test varying types of modules in a single platform configuration.
IGBTs, manufactured largely in Japan and the EU, were previously tested with electronic measuring instruments. However, the diversification of IGBT products, including smaller and higher voltage devices, increases the need for a test system capable of easy programming and module changes, while lowering test cost.
Advantest’s new IGBT test solution takes advantage of the flexibility of the T2000 platform to provide the optimal solution for IGBT chip and IPM (integrated power module) test, incorporating a high-power unit and a high-voltage module. It further lowers test cost by enabling parallel test of multiple medium- and low-power devices.
NetLogic announces comprehensive XLP multi-core processor hardware and software development kit
SANTA CLARA, USA: NetLogic Microsystems Inc. announced the availability of the XLP Multi-Core Processor Development Kit that includes comprehensive hardware and software tools, libraries, drivers and reference solutions to help accelerate time-to-market and reduce development effort for Tier One original equipment manufacturers (OEMs) who are developing next-generation systems using the industry-leading XLP multi-core, multi-threaded processor.
NetLogic Microsystems’ best-in-class XLP processor family is the first and only embedded communications processor that features quad-issue, quad-threaded and superscalar out-of-order capabilities with up to 128 NXCPUs™ operating at 2.0GHz. The XLP multi-core processor was recently rated “an exceptional CPU” which delivers “two to four times the performance of competing CPUs” by the Microprocessor Report.
NetLogic Microsystems’ production-ready XLP Multi-Core Processor Development Kit integrates everything needed to create and deploy control- and data-plane applications for product developers to quickly and easily design, test and debug next-generation network infrastructure systems, while leveraging the superior and highly differentiated features and compute power of the XLP multi-core processors.
Using the XLP Multi-Core Development Kit unleashes the massive performance and throughput benefits of NetLogic Microsystems’ XLP processors, and helps customers enhance product differentiation, reduce time-to-market and lower development risks.
The XLP Multi-Core Processor Development Kit includes:
* Production-ready development board.
* Reference schematics, models and guidelines to enable rapid hardware development.
* Board design and layout guidelines and reference Allegro layout files.
* Programmer’s reference manual and datasheets.
* Full board support package, including Linux 2.6 64-bit operating system and NetOS data plane environment.
* Full tool chain and debug environment.
* Bootloader/BSP and diagnostics.
* Libraries for accelerating compression/decompression, encryption/decryption, packet ordering, and support of the extensive I/O functions of the processor.
* Rich set of software for demonstrating and evaluation as well as sample code to ease the process application development.
* Options for high-speed connectivity, including Interlaken, XAUI, and SGMII, including a highly optimized interface to NetLogic Microsystems’ industry-leading knowledge-based processors.
“We are pleased to deliver a comprehensive hardware and software development kit that allows our customers to quickly go to market with our breakthrough XLP multi-core processor,” said Chris O’Reilly, vice president of marketing at NetLogic Microsystems. “The combination of the industry’s most advanced and highly differentiated multi-core processor along with a turnkey development kit gives us a strong leadership position in high-end multi-core communications processing well ahead of our competition.”
The industry-leading XLP multi-core, multi-threaded processor family integrates up to 128 NXCPUs that operate at up to 2.0 GHz and are based on a highly innovative superscalar engine with out-of-order execution capabilities to deliver unparalleled data plane and control plane performance, as well as the ability to support billions of in-flight messages and packet descriptors.
The XLP cores are quad-threaded to effectively minimize bottlenecks and memory latencies that are inherent in network data plane processing applications. Furthermore, the 128 NXCPUs are equipped with a tri-level cache architecture with over 50 Mbytes of fully coherent on-chip cache which delivers 160 Terabits/sec of extremely high-speed on-chip memory bandwidth.
The XLP processor also includes over 160 fully-autonomous programmable processing engines that provide independent and complete offload of additional network functions, including IPSec/SSL security encryption/decryption/authentication, packet parsing, packet queuing, packet management, compression/decompression, packet ordering, storage de-duplication, RAID5/RAID6, TCP segmentation and IEEE1588 hardware time stamping.
The XLP processor is designed on Taiwan Semiconductor Manufacturing Co.'s (TSMC) high performance 40nm process, providing for the smallest die size, highest clocking speeds and industry-leading power profile.
NetLogic Microsystems’ best-in-class XLP processor family is the first and only embedded communications processor that features quad-issue, quad-threaded and superscalar out-of-order capabilities with up to 128 NXCPUs™ operating at 2.0GHz. The XLP multi-core processor was recently rated “an exceptional CPU” which delivers “two to four times the performance of competing CPUs” by the Microprocessor Report.
NetLogic Microsystems’ production-ready XLP Multi-Core Processor Development Kit integrates everything needed to create and deploy control- and data-plane applications for product developers to quickly and easily design, test and debug next-generation network infrastructure systems, while leveraging the superior and highly differentiated features and compute power of the XLP multi-core processors.
Using the XLP Multi-Core Development Kit unleashes the massive performance and throughput benefits of NetLogic Microsystems’ XLP processors, and helps customers enhance product differentiation, reduce time-to-market and lower development risks.
The XLP Multi-Core Processor Development Kit includes:
* Production-ready development board.
* Reference schematics, models and guidelines to enable rapid hardware development.
* Board design and layout guidelines and reference Allegro layout files.
* Programmer’s reference manual and datasheets.
* Full board support package, including Linux 2.6 64-bit operating system and NetOS data plane environment.
* Full tool chain and debug environment.
* Bootloader/BSP and diagnostics.
* Libraries for accelerating compression/decompression, encryption/decryption, packet ordering, and support of the extensive I/O functions of the processor.
* Rich set of software for demonstrating and evaluation as well as sample code to ease the process application development.
* Options for high-speed connectivity, including Interlaken, XAUI, and SGMII, including a highly optimized interface to NetLogic Microsystems’ industry-leading knowledge-based processors.
“We are pleased to deliver a comprehensive hardware and software development kit that allows our customers to quickly go to market with our breakthrough XLP multi-core processor,” said Chris O’Reilly, vice president of marketing at NetLogic Microsystems. “The combination of the industry’s most advanced and highly differentiated multi-core processor along with a turnkey development kit gives us a strong leadership position in high-end multi-core communications processing well ahead of our competition.”
The industry-leading XLP multi-core, multi-threaded processor family integrates up to 128 NXCPUs that operate at up to 2.0 GHz and are based on a highly innovative superscalar engine with out-of-order execution capabilities to deliver unparalleled data plane and control plane performance, as well as the ability to support billions of in-flight messages and packet descriptors.
The XLP cores are quad-threaded to effectively minimize bottlenecks and memory latencies that are inherent in network data plane processing applications. Furthermore, the 128 NXCPUs are equipped with a tri-level cache architecture with over 50 Mbytes of fully coherent on-chip cache which delivers 160 Terabits/sec of extremely high-speed on-chip memory bandwidth.
The XLP processor also includes over 160 fully-autonomous programmable processing engines that provide independent and complete offload of additional network functions, including IPSec/SSL security encryption/decryption/authentication, packet parsing, packet queuing, packet management, compression/decompression, packet ordering, storage de-duplication, RAID5/RAID6, TCP segmentation and IEEE1588 hardware time stamping.
The XLP processor is designed on Taiwan Semiconductor Manufacturing Co.'s (TSMC) high performance 40nm process, providing for the smallest die size, highest clocking speeds and industry-leading power profile.
NXP announces first leadless package with tin-plated, solderable side pads
SINGAPORE: NXP Semiconductors N.V. has announced the availability of SOD882D, the industry’s first leadless package with solderable, tin-plated side pads.
The SOD882D is a 2-pin plastic package measuring only 1mm x 0.6mm and is ideal for small and thin devices. With a height of only 0.37 mm (typical), it is also one of the flattest packages in the 1006-size (0402 inch) and is available in various ESD protection and switching diodes.
The NXP SOD882D package has two tin-plated, solderable bottom pads that are exposed and are also Sn-plated on the sides. This innovative pad design provides soldering of the bottom and side pads and allows for easy visual inspection.
The new package enables mechanically robust designs as it is optimized for maximum shear forces, board bending and reduces the package tilting angle. The thermal, electrical, mounting and footprint characteristics of SOD882D are fully compatible with other available 2-pin, leadless 1006-packages.
“Leveraging our expertise in discrete leadless package technologies, NXP has developed the SOD882D package’s new pad design as an upgraded version of the successful SOD882. As one of the industry leaders in small-signal discretes, we believe that the SOD882D is a solution to a gap in the packaging market for highly space-constrained devices such as mobile phones, tablet PCs and small handheld devices requiring special mounting and robustness,” said Ralf Euler, Director of product management for small-signal discretes at NXP Semiconductors.
“The SOD882D is a great new addition to NXP’s leadless packaging portfolio, which is already very broad and offers almost every discrete functionality.”
The first products to be available in the SOD882D package are a 100V single high-speed switching diode (BAS16LD) and three 5V and 24V ESD protection diodes (PESD*LD) that are designed to protect one signal line up to 30 kV (IEC 61000-4-2; level 4).
All products are AEC-Q101 qualified and values for line capacitance range between 23 and 152 pF (typical). Two 5V ESD protection diodes with only 1.05 pF and 11 pF (typical) will be launched later this year.
The portfolio will also include Schottky and low capacitance ESD protection diodes which will be introduced later this year and in early 2011.
The SOD882D is free of halogens and antimony oxides and complies with non-flammability classification UL 94V-O and RoHS standards.
Three new ESD protection diodes (PESD5V0S1BLD, PESD5V0S1ULD, PESD24V0S1ULD) and the switching diode (BAS16LD) in SOD882D have been released.
The 1.05 pF and 11 pF ESD protection diodes (PESD5V0X1ULB, PESD5V0V1BLD) will be launched in December 2010.
The SOD882D is a 2-pin plastic package measuring only 1mm x 0.6mm and is ideal for small and thin devices. With a height of only 0.37 mm (typical), it is also one of the flattest packages in the 1006-size (0402 inch) and is available in various ESD protection and switching diodes.
The NXP SOD882D package has two tin-plated, solderable bottom pads that are exposed and are also Sn-plated on the sides. This innovative pad design provides soldering of the bottom and side pads and allows for easy visual inspection.
The new package enables mechanically robust designs as it is optimized for maximum shear forces, board bending and reduces the package tilting angle. The thermal, electrical, mounting and footprint characteristics of SOD882D are fully compatible with other available 2-pin, leadless 1006-packages.
“Leveraging our expertise in discrete leadless package technologies, NXP has developed the SOD882D package’s new pad design as an upgraded version of the successful SOD882. As one of the industry leaders in small-signal discretes, we believe that the SOD882D is a solution to a gap in the packaging market for highly space-constrained devices such as mobile phones, tablet PCs and small handheld devices requiring special mounting and robustness,” said Ralf Euler, Director of product management for small-signal discretes at NXP Semiconductors.
“The SOD882D is a great new addition to NXP’s leadless packaging portfolio, which is already very broad and offers almost every discrete functionality.”
The first products to be available in the SOD882D package are a 100V single high-speed switching diode (BAS16LD) and three 5V and 24V ESD protection diodes (PESD*LD) that are designed to protect one signal line up to 30 kV (IEC 61000-4-2; level 4).
All products are AEC-Q101 qualified and values for line capacitance range between 23 and 152 pF (typical). Two 5V ESD protection diodes with only 1.05 pF and 11 pF (typical) will be launched later this year.
The portfolio will also include Schottky and low capacitance ESD protection diodes which will be introduced later this year and in early 2011.
The SOD882D is free of halogens and antimony oxides and complies with non-flammability classification UL 94V-O and RoHS standards.
Three new ESD protection diodes (PESD5V0S1BLD, PESD5V0S1ULD, PESD24V0S1ULD) and the switching diode (BAS16LD) in SOD882D have been released.
The 1.05 pF and 11 pF ESD protection diodes (PESD5V0X1ULB, PESD5V0V1BLD) will be launched in December 2010.
Xilinx stacked silicon interconnect extends FPGA technology to deliver 'More than Moore' density, bandwidth and power efficiency
TAIPEI, TAIWAN: Xilinx Inc. has announced the industry's first stacked silicon interconnect technology for delivering breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance.
By embracing 3D packaging technologies and through-silicon vias (TSV) for its 28nm 7 series FPGAs, Xilinx's Targeted Design Platforms can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs. This innovative platform approach enables Xilinx to overcome the boundaries of Moore's Law and offer electronics manufacturers unparalleled power, bandwidth and density optimization for the large-scale-integration of their systems.
"One of the ways the 28nm Xilinx 7 series FPGAs extend the range of applications programmable logic can address is by offering industry-leading capacity of up to 2 million logic cells. Our stacked silicon interconnect packaging approach makes this remarkable achievement possible," said Vincent Tong, Xilinx senior VP.
"Five years of Xilinx research and development coupled with industry leading technology from TSMC and our assembly suppliers has made possible our efforts to provide an innovative solution for enabling electronic systems developers to take the benefits of FPGAs further into their manufacturing flow."
With software support available in ISE Design Suite 13.1, which is currently available to beta customers, the 28nm Virtex-7 LX2000T device will be the world's first multi-die FPGA and provide more than 3.5X the logic capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8X the logic capacity of the largest competing 28nm FPGA with serial transceivers.
The device is made possible by industry-leading micro-bump assembly, patented FPGA architectural innovations from Xilinx, and advanced technology from TSMC that deliver lower levels of power consumption, system cost and circuit board complexity compared to using multiple FPGAs, each in their own package, for the same application.
"Compared with traditional monolithic FPGAs, multi-chip packaging approach is an innovative way to deliver large-scale programmability with favorable yield, reliability, thermal gradient, and stress tolerance characteristics," said Shang-yi Chiang, senior VP of R&D at TSMC.
"By using through-silicon via technology and silicon interposer to implement a stacked silicon interconnect approach, Xilinx expects to reduce risks and is on the way to volume production with well-designed test vehicle runs that meet the company's criteria for design enablement, manufacturability validation, and reliability assessment."
Within the Xilinx stacked silicon interconnect structure, data flows between a set of adjacent FPGA die across more than 10,000 routing connections. Compared with having to use standard I/O connections to integrate two FPGAs together on a circuit board, stacked silicon interconnect technology provides over 100X the die-to-die connectivity bandwidth per watt, at one-fifth the latency, without consuming any high-speed serial or parallel I/O resources.
By having die sit adjacent to each other and interfaced to the ball-grid-array, Xilinx can avoid the thermal flux and design tool flow issues that would be introduced had a purely vertical die-stacking approach been taken. Xilinx's choice of 28nm HPL (high-performance, low-power) process technology for the base FPGA device provides a comfortable power budget in the package for integrating FPGA die.
Xilinx stacked silicon interconnect technology serves the most demanding FPGA applications at the heart of next generation electronic systems. The technology's ultra high-bandwidth, low-latency and low-power interconnect allows customers to implement applications applying the same approaches used for large monolithic FPGA devices, using the software's built-in auto partitioning capabilities for push-button ease-of use, or hierarchical and team-based design techniques for the highest performance and productivity.
"The Virtex-7 2000T FPGA using stacked silicon interconnect technology is a significant step in FPGA evolution and will enable ARM to implement the latest cores and platform solutions within a single FPGA. This will reduce our development effort, reduce power, and improve performance compared to a multi-FPGA approach," said John Cornish, EVP and general manager, System Design Division, ARM. "We have been a long time user of the Virtex FPGA technology in the ARM Versatile Express SoC prototyping solutions and this will surely extend our strong position."
"The availability of proven TSV technology along with low-latency interposer structures is being used effectively by Xilinx to expand the capabilities of their FPGA products," said Dr. Handel H. Jones founder and CEO of IBS Inc.
"The technologies used by Xilinx have been used in the high-volume manufacturing environment, with the expectation that the quality and reliability of the finished products will be high, where customer risks are very low."
Aligned with silicon progress is a robust supply chain that is in place with leading foundry and outsourced assembly and test partners, including TSMC. Software support will be available in ISE Design Suite 13.1, which is currently available to beta customers. Initial devices will be available in the 2nd half of 2011.
By embracing 3D packaging technologies and through-silicon vias (TSV) for its 28nm 7 series FPGAs, Xilinx's Targeted Design Platforms can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs. This innovative platform approach enables Xilinx to overcome the boundaries of Moore's Law and offer electronics manufacturers unparalleled power, bandwidth and density optimization for the large-scale-integration of their systems.
"One of the ways the 28nm Xilinx 7 series FPGAs extend the range of applications programmable logic can address is by offering industry-leading capacity of up to 2 million logic cells. Our stacked silicon interconnect packaging approach makes this remarkable achievement possible," said Vincent Tong, Xilinx senior VP.
"Five years of Xilinx research and development coupled with industry leading technology from TSMC and our assembly suppliers has made possible our efforts to provide an innovative solution for enabling electronic systems developers to take the benefits of FPGAs further into their manufacturing flow."
With software support available in ISE Design Suite 13.1, which is currently available to beta customers, the 28nm Virtex-7 LX2000T device will be the world's first multi-die FPGA and provide more than 3.5X the logic capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8X the logic capacity of the largest competing 28nm FPGA with serial transceivers.
The device is made possible by industry-leading micro-bump assembly, patented FPGA architectural innovations from Xilinx, and advanced technology from TSMC that deliver lower levels of power consumption, system cost and circuit board complexity compared to using multiple FPGAs, each in their own package, for the same application.
"Compared with traditional monolithic FPGAs, multi-chip packaging approach is an innovative way to deliver large-scale programmability with favorable yield, reliability, thermal gradient, and stress tolerance characteristics," said Shang-yi Chiang, senior VP of R&D at TSMC.
"By using through-silicon via technology and silicon interposer to implement a stacked silicon interconnect approach, Xilinx expects to reduce risks and is on the way to volume production with well-designed test vehicle runs that meet the company's criteria for design enablement, manufacturability validation, and reliability assessment."
Within the Xilinx stacked silicon interconnect structure, data flows between a set of adjacent FPGA die across more than 10,000 routing connections. Compared with having to use standard I/O connections to integrate two FPGAs together on a circuit board, stacked silicon interconnect technology provides over 100X the die-to-die connectivity bandwidth per watt, at one-fifth the latency, without consuming any high-speed serial or parallel I/O resources.
By having die sit adjacent to each other and interfaced to the ball-grid-array, Xilinx can avoid the thermal flux and design tool flow issues that would be introduced had a purely vertical die-stacking approach been taken. Xilinx's choice of 28nm HPL (high-performance, low-power) process technology for the base FPGA device provides a comfortable power budget in the package for integrating FPGA die.
Xilinx stacked silicon interconnect technology serves the most demanding FPGA applications at the heart of next generation electronic systems. The technology's ultra high-bandwidth, low-latency and low-power interconnect allows customers to implement applications applying the same approaches used for large monolithic FPGA devices, using the software's built-in auto partitioning capabilities for push-button ease-of use, or hierarchical and team-based design techniques for the highest performance and productivity.
"The Virtex-7 2000T FPGA using stacked silicon interconnect technology is a significant step in FPGA evolution and will enable ARM to implement the latest cores and platform solutions within a single FPGA. This will reduce our development effort, reduce power, and improve performance compared to a multi-FPGA approach," said John Cornish, EVP and general manager, System Design Division, ARM. "We have been a long time user of the Virtex FPGA technology in the ARM Versatile Express SoC prototyping solutions and this will surely extend our strong position."
"The availability of proven TSV technology along with low-latency interposer structures is being used effectively by Xilinx to expand the capabilities of their FPGA products," said Dr. Handel H. Jones founder and CEO of IBS Inc.
"The technologies used by Xilinx have been used in the high-volume manufacturing environment, with the expectation that the quality and reliability of the finished products will be high, where customer risks are very low."
Aligned with silicon progress is a robust supply chain that is in place with leading foundry and outsourced assembly and test partners, including TSMC. Software support will be available in ISE Design Suite 13.1, which is currently available to beta customers. Initial devices will be available in the 2nd half of 2011.
Cadence unveils holistic approach to silicon realization
USA: Cadence Design Systems Inc. has introduced a new holistic approach to Silicon Realization that moves chip development beyond a patchwork of point tools to a streamlined end-to-end path of integrated technology, tools, and methodology.
This approach represents a stark turn from the discreet and compartmentalized ways semiconductor and systems companies have traditionally achieved Silicon Realization, the term that refers to all the steps required for bringing a design to silicon and a key component of the EDA360 initiative.
The new Cadence approach is focused on offering products and technologies that deliver on the three requirements for a deterministic path to silicon: unified design intent, design abstraction and design convergence.
A design flow that meets these three requirements can deliver significant and measurable productivity, predictability, and profitability boosts to chip and systems makers facing today’s greatest technology and business challenges: mixed signal, low power, giga-gates/gigahertz, verification, SiP and co-design, and global productivity and metrics.
With new technology introduced today across the company’s Silicon Realization portfolio, Cadence has made further advancements to ensure its current and upcoming products meet these three key requirements and can be incorporated into a holistic flow.
In the area of intent, new capabilities enable analog, physical and electrical constraints to drive digital content into mixed-signal flows and vice versa. For abstraction, design teams now can create a die abstract for system-in-package and 3D IC designs, bringing full interoperability between package and silicon design.
For design convergence, Cadence introduced new physical, electrical and functional links between logic design, verification and implementation, providing greater convergence in the design flow and allowing rapid ECOs. For more detailed information, a Silicon Realization white paper is available for download at http://www.cadence.com/downloads/rl/wp/silicon_realization_wp.pdf.
“This approach reflects the best Cadence I’ve dealt with,” said Gary Smith, chief analyst for Gary Smith EDA. “Cadence continues to define its strategy, has brought in good people and has tied their performance to its strategic EDA360 goals. The intent is to tear down the silos and have all of the company’s divisions working with each other. They are attempting to do what many other EDA companies have tried and failed.”
“ In today’s climate of complex designs and market pressures, chip developers are in dire need of dramatic boosts in productivity and profitability, and they simply can’t get there by stitching together tools from a dozen different vendors,” said Chi-Ping Hsu, Cadence senior vice president, research and development, Silicon Realization Group.
“Cadence’s industry-leading, advanced low-power solution first demonstrated our R&D teams’ focus on building tools that meet the requirements of unified design intent, abstraction and convergence, and our future product releases will continue to deliver on these core elements. Ultimately, we expect to offer a number of seamless end-to-end design flows whose built-in efficiencies will give customers a meaningful market advantage.”
This approach represents a stark turn from the discreet and compartmentalized ways semiconductor and systems companies have traditionally achieved Silicon Realization, the term that refers to all the steps required for bringing a design to silicon and a key component of the EDA360 initiative.
The new Cadence approach is focused on offering products and technologies that deliver on the three requirements for a deterministic path to silicon: unified design intent, design abstraction and design convergence.
A design flow that meets these three requirements can deliver significant and measurable productivity, predictability, and profitability boosts to chip and systems makers facing today’s greatest technology and business challenges: mixed signal, low power, giga-gates/gigahertz, verification, SiP and co-design, and global productivity and metrics.
With new technology introduced today across the company’s Silicon Realization portfolio, Cadence has made further advancements to ensure its current and upcoming products meet these three key requirements and can be incorporated into a holistic flow.
In the area of intent, new capabilities enable analog, physical and electrical constraints to drive digital content into mixed-signal flows and vice versa. For abstraction, design teams now can create a die abstract for system-in-package and 3D IC designs, bringing full interoperability between package and silicon design.
For design convergence, Cadence introduced new physical, electrical and functional links between logic design, verification and implementation, providing greater convergence in the design flow and allowing rapid ECOs. For more detailed information, a Silicon Realization white paper is available for download at http://www.cadence.com/downloads/rl/wp/silicon_realization_wp.pdf.
“This approach reflects the best Cadence I’ve dealt with,” said Gary Smith, chief analyst for Gary Smith EDA. “Cadence continues to define its strategy, has brought in good people and has tied their performance to its strategic EDA360 goals. The intent is to tear down the silos and have all of the company’s divisions working with each other. They are attempting to do what many other EDA companies have tried and failed.”
“ In today’s climate of complex designs and market pressures, chip developers are in dire need of dramatic boosts in productivity and profitability, and they simply can’t get there by stitching together tools from a dozen different vendors,” said Chi-Ping Hsu, Cadence senior vice president, research and development, Silicon Realization Group.
“Cadence’s industry-leading, advanced low-power solution first demonstrated our R&D teams’ focus on building tools that meet the requirements of unified design intent, abstraction and convergence, and our future product releases will continue to deliver on these core elements. Ultimately, we expect to offer a number of seamless end-to-end design flows whose built-in efficiencies will give customers a meaningful market advantage.”
Synopsys power-aware test speeds time to volume production at Realtek
MOUNTAIN VIEW, USA: Synopsys Inc. announced that Realtek Semiconductor Corp. one of the world's leading network and multimedia IC providers, deployed Synopsys power-aware test to avoid power issues during test and accelerate production testing of its new digital media processor.
Excessive power consumption during manufacturing test leads to overheating, IR drop, and other effects that can cause devices to fail, impacting profitability and delaying production ramp.
Designers at Realtek avoided these issues by reducing the device power consumption at test time using advanced power-aware capabilities in Synopsys' DFTMAX compression and TetraMAX ATPG tools, integral components of the Galaxy Implementation Platform. As a result, Realtek delivered high-quality parts in volume quantities weeks earlier and at lower cost than previously possible.
"Our product teams can ramp-up to volume testing faster with Synopsys power-aware test because we spend less time debugging power-related issues," said Realtek's vice president and spokesman, Jessy Chen. "An added benefit is that we can test our products across a much wider range of operating environments, including lower supply voltage conditions."
Synopsys power-aware test employs a variety of synthesis-based design-for-test (DFT) and automatic test pattern generation (ATPG) techniques that reduce power consumption during test while minimizing the impact test logic has on design timing, area, power and congestion.
This approach eliminates time-consuming iterations between RTL synthesis, test and physical implementation, helping designers converge on both test and design goals faster. DFTMAX compression and TetraMAX ATPG work in tandem to keep the device power during test at the same level as normal system operation, preventing false rejections due to IR drop. By also substantially reducing average power to circumvent over-heating, the test program can execute faster, thereby reducing total test time and cost.
"Fully-functional silicon can be erroneously rejected at test time due to power issues associated with the testing process itself," said Bijan Kiani, vice president of product marketing at Synopsys. "Customers such as Realtek are addressing these issues in the design phase by using Synopsys power-aware test to maintain high gross margins and avoid costly production delays while meeting their defect coverage and cost goals."
Excessive power consumption during manufacturing test leads to overheating, IR drop, and other effects that can cause devices to fail, impacting profitability and delaying production ramp.
Designers at Realtek avoided these issues by reducing the device power consumption at test time using advanced power-aware capabilities in Synopsys' DFTMAX compression and TetraMAX ATPG tools, integral components of the Galaxy Implementation Platform. As a result, Realtek delivered high-quality parts in volume quantities weeks earlier and at lower cost than previously possible.
"Our product teams can ramp-up to volume testing faster with Synopsys power-aware test because we spend less time debugging power-related issues," said Realtek's vice president and spokesman, Jessy Chen. "An added benefit is that we can test our products across a much wider range of operating environments, including lower supply voltage conditions."
Synopsys power-aware test employs a variety of synthesis-based design-for-test (DFT) and automatic test pattern generation (ATPG) techniques that reduce power consumption during test while minimizing the impact test logic has on design timing, area, power and congestion.
This approach eliminates time-consuming iterations between RTL synthesis, test and physical implementation, helping designers converge on both test and design goals faster. DFTMAX compression and TetraMAX ATPG work in tandem to keep the device power during test at the same level as normal system operation, preventing false rejections due to IR drop. By also substantially reducing average power to circumvent over-heating, the test program can execute faster, thereby reducing total test time and cost.
"Fully-functional silicon can be erroneously rejected at test time due to power issues associated with the testing process itself," said Bijan Kiani, vice president of product marketing at Synopsys. "Customers such as Realtek are addressing these issues in the design phase by using Synopsys power-aware test to maintain high gross margins and avoid costly production delays while meeting their defect coverage and cost goals."
New technology to help improve sleep and quality of life
SINGAPORE: Millions of people worldwide, who suffer from the debilitating effects of sleep apnea, will benefit from a new device to treat the health condition, thanks to an innovative technology partnership between ResMed and STMicroelectronics.
Sleep apnea, a common but little-known disorder, affects 1 in 5 adults. It stems from closure of the airway during sleep which causes breathing to stop, sometimes for more than a minute; often leaving the person affected gasping for air. In severe cases, this can happen hundreds of times each night leading to serious health risks, including increased heart rate, higher blood pressure and potentially, heart attack and cardiovascular disease.
The symptoms of sleep apnea include fatigue, depression, poor concentration/memory and waking with a headache or dry sore throat. While many people perceive snoring as a common and harmless problem, it can be a clear symptom of this serious condition. Over 80 percent of sufferers with moderate to severe sleep apnea are thought to be undiagnosed and untreated.
Luckily, there are safe and effective treatments available which provide a new lease on life to many sleep apnea sufferers. Continuous Positive Airway Pressure (CPAP) therapy is recognized as the most effective non-invasive treatment for the majority of cases. With this therapy, a bedside device gently delivers pressurized air via a mask to keep the upper airway open and prevent obstruction.
“People with sleep apnea often find that their quality of life is severely reduced. The challenge in diagnosing sleep apnea is that many sufferers are unaware that they may have the disorder,” said Rob Douglas, COO, ResMed Asia Pacific.
“Although CPAP treatment acts on the relatively simple principle of blowing air into the airway, the latest technology behind ResMed CPAP devices, like the new S9 Series, is truly innovative.”
“By working with a partner like STMicroelectronics, one of the world’s leading semiconductor manufacturers, we have been able to take CPAP therapy to a new level of effectiveness, significantly enhancing the patient’s quality of life,” said Douglas.
With significant investment in R&D and a cross-functional team of industrial designers, mechanical, electrical, software and system engineers, ResMed’s multi-award winning S9 Series is now available globally. The device was developed from the ground-up; ResMed virtually customized and optimized everything with its technology partners in the early design phase.
An example of such collaboration is the S9 Series’ integrated microchip technology, provided by STMicroelectronics. The technology provides sensing support to help automatically control the air pressure needed by the patient; it also allows for extensive data logging, and a color LCD screen to help make the device easy-to-use.
“As a strategic technology partner for ResMed, the global leader in devices for treatment of sleep-disordered breathing, ST is building on its growing strengths and presence in the healthcare market,” said Francois Guibert, executive VP and president, Greater China & South Asia, STMicroelectronics. “I am very excited with our partnership going forward. Our shared roadmap will see even more innovative ST products powering future market-leading devices by ResMed.”
ResMed’s S9 Series offers the capabilities of a high-tech medical device, coupled with cutting-edge, yet easy-to-use design to ensure patients experience a healthy and restful night’s sleep. It was recently recognised internationally with a red dot design award, and is currently on display in Singapore’s red dot award museum.
Sleep apnea, a common but little-known disorder, affects 1 in 5 adults. It stems from closure of the airway during sleep which causes breathing to stop, sometimes for more than a minute; often leaving the person affected gasping for air. In severe cases, this can happen hundreds of times each night leading to serious health risks, including increased heart rate, higher blood pressure and potentially, heart attack and cardiovascular disease.
The symptoms of sleep apnea include fatigue, depression, poor concentration/memory and waking with a headache or dry sore throat. While many people perceive snoring as a common and harmless problem, it can be a clear symptom of this serious condition. Over 80 percent of sufferers with moderate to severe sleep apnea are thought to be undiagnosed and untreated.
Luckily, there are safe and effective treatments available which provide a new lease on life to many sleep apnea sufferers. Continuous Positive Airway Pressure (CPAP) therapy is recognized as the most effective non-invasive treatment for the majority of cases. With this therapy, a bedside device gently delivers pressurized air via a mask to keep the upper airway open and prevent obstruction.
“People with sleep apnea often find that their quality of life is severely reduced. The challenge in diagnosing sleep apnea is that many sufferers are unaware that they may have the disorder,” said Rob Douglas, COO, ResMed Asia Pacific.
“Although CPAP treatment acts on the relatively simple principle of blowing air into the airway, the latest technology behind ResMed CPAP devices, like the new S9 Series, is truly innovative.”
“By working with a partner like STMicroelectronics, one of the world’s leading semiconductor manufacturers, we have been able to take CPAP therapy to a new level of effectiveness, significantly enhancing the patient’s quality of life,” said Douglas.
With significant investment in R&D and a cross-functional team of industrial designers, mechanical, electrical, software and system engineers, ResMed’s multi-award winning S9 Series is now available globally. The device was developed from the ground-up; ResMed virtually customized and optimized everything with its technology partners in the early design phase.
An example of such collaboration is the S9 Series’ integrated microchip technology, provided by STMicroelectronics. The technology provides sensing support to help automatically control the air pressure needed by the patient; it also allows for extensive data logging, and a color LCD screen to help make the device easy-to-use.
“As a strategic technology partner for ResMed, the global leader in devices for treatment of sleep-disordered breathing, ST is building on its growing strengths and presence in the healthcare market,” said Francois Guibert, executive VP and president, Greater China & South Asia, STMicroelectronics. “I am very excited with our partnership going forward. Our shared roadmap will see even more innovative ST products powering future market-leading devices by ResMed.”
ResMed’s S9 Series offers the capabilities of a high-tech medical device, coupled with cutting-edge, yet easy-to-use design to ensure patients experience a healthy and restful night’s sleep. It was recently recognised internationally with a red dot design award, and is currently on display in Singapore’s red dot award museum.
Microchip's 16V op amps feature low quiescent current (135 microamperes)
BANGALORE, INDIA: Microchip Technology Inc., a leading provider of microcontroller, analog and Flash-IP solutions, has announced the MCP6H01 and MCP6H02 (MCP6H01/2) general-purpose operational amplifiers (op amps) with a gain-bandwidth product of 1.2 MHz and supply voltage from 3.5V to 16V.
These devices also feature low quiescent current of 135 microamperes (typ.), offset voltage of 3.5 mV (max.), Common Mode Rejection Ratio (CMRR) of 100 dB (typ.), and Power-Supply Rejection Ratio (PSRR) of 102 dB (typ.).
The MCP6H01/2 is targeted for applications that operate on voltages up to 16V, such as those in the medical (e.g. portable instrumentation, heart- and blood-pressure monitors), automotive (e.g. proximity, temperature or flow sensors), and industrial (e.g. high-side current sensing in power supplies) markets. These devices also offer high CMRR and PSRR for improved noise performance. Additionally, low current consumption combined with space-saving package offerings make the MCP6H01/2 ideal for portable applications.
"With their low power and wide operating voltage range, the MCP6H01/2 family is a significant addition to Microchip’s linear product portfolio," said Bryan J. Liddiard, vice president of marketing with Microchip's Analog and Interface Products Division. "The performance of the MCP6H01/2 family is expected to enable new markets and applications for Microchip."
Development support
PCB footprints and schematic symbols are available from Microchip's Web site. The downloads will be available in a neutral format that can be exported to the leading EDA CAD/CAE design tools using the Ultra Librarian Reader from Accelerated Designs Inc.
These devices also feature low quiescent current of 135 microamperes (typ.), offset voltage of 3.5 mV (max.), Common Mode Rejection Ratio (CMRR) of 100 dB (typ.), and Power-Supply Rejection Ratio (PSRR) of 102 dB (typ.).
The MCP6H01/2 is targeted for applications that operate on voltages up to 16V, such as those in the medical (e.g. portable instrumentation, heart- and blood-pressure monitors), automotive (e.g. proximity, temperature or flow sensors), and industrial (e.g. high-side current sensing in power supplies) markets. These devices also offer high CMRR and PSRR for improved noise performance. Additionally, low current consumption combined with space-saving package offerings make the MCP6H01/2 ideal for portable applications.
"With their low power and wide operating voltage range, the MCP6H01/2 family is a significant addition to Microchip’s linear product portfolio," said Bryan J. Liddiard, vice president of marketing with Microchip's Analog and Interface Products Division. "The performance of the MCP6H01/2 family is expected to enable new markets and applications for Microchip."
Development support
PCB footprints and schematic symbols are available from Microchip's Web site. The downloads will be available in a neutral format that can be exported to the leading EDA CAD/CAE design tools using the Ultra Librarian Reader from Accelerated Designs Inc.
TowerJazz raises $100 million in debentures offering
MIGDAL-HAEMEK, ISRAEL: TowerJazz announced the completion of its previously announced fundraising in Israel, following a public tender executed today resulting in excess demand of 150 percent.
TowerJazz raised an aggregate of approximately NIS 380 million through the issuance of new Series F debentures. The debentures were issued at 96 percent of par value.
The series F convertible debentures are linked to the US dollar, bear interest of 7.8 percent per annum, payable semi-annually on June 30 and on December 31 of each year through 2016, commencing December 31, 2010, and are convertible into the Company’s ordinary shares commencing September 2012 at about 20 percent premium over the company’s ordinary shares.
The placement agents acted in the transaction were Leader Issuances (1993) Ltd., Clal Finance Underwriting Ltd, Leumi Partners Underwriters Ltd., Apax Underwriting Management and Issuances Ltd., Poalim I.B.I – Underwriting and Issuances Ltd. and Barak Capital Underwriting Ltd.
Russell Ellwanger, TowerJazz CEO, stated: “With this $100 million fund raising, we completed the comprehensive debt restructure carried out over the past several months. This restructure comprised the extension of the $45 million Wells-Fargo credit lines, $80 million Jazz level bonds exchange to bonds due in 2015, $50 million pay down and restructure of the remaining $160 million Israeli banks debt to a long term loan and this deal.
"The composite has created a new balance sheet with zero bank loans’ principal due during the coming three years, servable debt ratios and a cash balance which will enable quick execution on synergistic business opportunities. I am extremely excited that sophisticated investors have expressed such strong confidence in our business model and belief in our future success by investing $100 million in newly issued long-term debentures.
"We received extreme positive feedback from the many investors who we met during the recent road show. With the new balance sheet, debt ratios, cash balance and $500 million annualized quarterly revenue run rate, we are in a financial and business position unlike any in our company's history and are fully focused to fulfill our corporate vision ‘to be the world leader in specialty foundry solutions as measured by our customers, employees and investors’.”
TowerJazz thanks its counsel, David Schapiro, a partner of the Law Firm of Yigal Arnon & Co. and Rami Chalaf, a partner of the Accounting Firm of Deloitte Brightman Almagor Zohar.
TowerJazz raised an aggregate of approximately NIS 380 million through the issuance of new Series F debentures. The debentures were issued at 96 percent of par value.
The series F convertible debentures are linked to the US dollar, bear interest of 7.8 percent per annum, payable semi-annually on June 30 and on December 31 of each year through 2016, commencing December 31, 2010, and are convertible into the Company’s ordinary shares commencing September 2012 at about 20 percent premium over the company’s ordinary shares.
The placement agents acted in the transaction were Leader Issuances (1993) Ltd., Clal Finance Underwriting Ltd, Leumi Partners Underwriters Ltd., Apax Underwriting Management and Issuances Ltd., Poalim I.B.I – Underwriting and Issuances Ltd. and Barak Capital Underwriting Ltd.
Russell Ellwanger, TowerJazz CEO, stated: “With this $100 million fund raising, we completed the comprehensive debt restructure carried out over the past several months. This restructure comprised the extension of the $45 million Wells-Fargo credit lines, $80 million Jazz level bonds exchange to bonds due in 2015, $50 million pay down and restructure of the remaining $160 million Israeli banks debt to a long term loan and this deal.
"The composite has created a new balance sheet with zero bank loans’ principal due during the coming three years, servable debt ratios and a cash balance which will enable quick execution on synergistic business opportunities. I am extremely excited that sophisticated investors have expressed such strong confidence in our business model and belief in our future success by investing $100 million in newly issued long-term debentures.
"We received extreme positive feedback from the many investors who we met during the recent road show. With the new balance sheet, debt ratios, cash balance and $500 million annualized quarterly revenue run rate, we are in a financial and business position unlike any in our company's history and are fully focused to fulfill our corporate vision ‘to be the world leader in specialty foundry solutions as measured by our customers, employees and investors’.”
TowerJazz thanks its counsel, David Schapiro, a partner of the Law Firm of Yigal Arnon & Co. and Rami Chalaf, a partner of the Accounting Firm of Deloitte Brightman Almagor Zohar.
TI intros nine 36V precision op amps for industrial market
DALLAS, USA: Texas Instruments Inc. (TI) has introduced three new families of 36-V single, dual and quad operational amplifiers (op amp) with industrial precision.
The OPAx140 JFET input op amp series features rail-to-rail output, as well as the lowest noise and widest supply range in its class. The OPAx209 precision op amp series combines rail-to-rail output and very low voltage noise density with wide gain bandwidth.
The general-purpose OPAx171 family features the industry's smallest packages – up to 90 percent smaller than industry-standard packaging to reduce board space.
The OPAx140 JFET input op amp series features rail-to-rail output, as well as the lowest noise and widest supply range in its class. The OPAx209 precision op amp series combines rail-to-rail output and very low voltage noise density with wide gain bandwidth.
The general-purpose OPAx171 family features the industry's smallest packages – up to 90 percent smaller than industry-standard packaging to reduce board space.
K-micro initiates development of IEEE 1901 compliant PLC LSI
SAN JOSE, USA: K-micro (Kawasaki Microelectronics America Inc.), a leader in advanced ASICs, announced that it is developing a PLC (power line communication) LSI that is compliant with the recently approved IEEE1901 standard.
K-micro, a member of the HD-PLC Alliance, has licensed the HD-PLC technology used as the basis for the chip from Panasonic Co., Ltd. and Panasonic System Networks Co., Ltd. The K-micro HD-PLC LSI, will feature:
PHY rate: 240Mbps (15% higher than the current LSI).
Wavelet OFDM methodology for low power (550mW in full operation).
IEEE1901 compliance (with ISP support for coexistence).
Backward compatibility with existing HD-PLC LSI products.
The PLC technology jointly proposed by Panasonic Co. Ltd and Panasonic System Networks Co. Ltd was approved by the IEEE Standard Association as a base technology in the IEEE1901 standard.
The PLC technology is Wavelet OFDM, which is used in products that adopt Panasonic's HD-PLC high-speed power line communication technology. This technology features the environmentally friendly capability to realize lower power consumption and lower costs through highly efficient data transmission.
"K-micro is developing products for comprehensive offerings of power line communications devices for various applications," said Koichi Akeyama, president of K-micro. "These new chips will enable low power consumption and high performance for multimedia home networking, smart grid systems and solar panels. The HD-PLC LSI chip will expand our current HD-PLC product line."
At the present time, K-micro is providing an Analog Front End (AFE) IC "KHN11121" for HD-PLC applications. "When the PLC LSI is combined with the KHN11121, the chip set will provide high performance and low power solutions," added Akeyama. "The high performance is needed to support multimedia home networking, video distribution, IPTV set-top boxes and home gateways. Samples of the chipset will be available in Q2 2011, and volume production will begin Q3 2011."
In addition, K-micro has plans to release an HD-PLC LSI targeted for smart grid applications in 2012. This new chip will operate at significantly lower power and at data rates consistent with smart grid requirements.
The lower speed devices are targeted at the smart grid system applications such as energy management, solar panels systems, etc. K-micro is developing solutions to enable power line communications to be used for a wide range of applications.
K-micro, a member of the HD-PLC Alliance, has licensed the HD-PLC technology used as the basis for the chip from Panasonic Co., Ltd. and Panasonic System Networks Co., Ltd. The K-micro HD-PLC LSI, will feature:
PHY rate: 240Mbps (15% higher than the current LSI).
Wavelet OFDM methodology for low power (550mW in full operation).
IEEE1901 compliance (with ISP support for coexistence).
Backward compatibility with existing HD-PLC LSI products.
The PLC technology jointly proposed by Panasonic Co. Ltd and Panasonic System Networks Co. Ltd was approved by the IEEE Standard Association as a base technology in the IEEE1901 standard.
The PLC technology is Wavelet OFDM, which is used in products that adopt Panasonic's HD-PLC high-speed power line communication technology. This technology features the environmentally friendly capability to realize lower power consumption and lower costs through highly efficient data transmission.
"K-micro is developing products for comprehensive offerings of power line communications devices for various applications," said Koichi Akeyama, president of K-micro. "These new chips will enable low power consumption and high performance for multimedia home networking, smart grid systems and solar panels. The HD-PLC LSI chip will expand our current HD-PLC product line."
At the present time, K-micro is providing an Analog Front End (AFE) IC "KHN11121" for HD-PLC applications. "When the PLC LSI is combined with the KHN11121, the chip set will provide high performance and low power solutions," added Akeyama. "The high performance is needed to support multimedia home networking, video distribution, IPTV set-top boxes and home gateways. Samples of the chipset will be available in Q2 2011, and volume production will begin Q3 2011."
In addition, K-micro has plans to release an HD-PLC LSI targeted for smart grid applications in 2012. This new chip will operate at significantly lower power and at data rates consistent with smart grid requirements.
The lower speed devices are targeted at the smart grid system applications such as energy management, solar panels systems, etc. K-micro is developing solutions to enable power line communications to be used for a wide range of applications.
Lattice announces PAC-Designer design software v6.0
HILLSBORO, USA: Lattice Semiconductor Corp. announced that its new PAC-Designer design software version 6.0, which enables analog and board designers to integrate a circuit board’s power management and digital board management functions into the newly announced Platform Manager device family.
With PAC-Designer 6.0, designers can use a simple, easy to learn, push-button design methodology to implement designs into the FPGA portion of the Platform Manager devices. Three new IP cores, which provide correct-by-construction application solutions, have also been announced.
Simultaneously, Lattice is announcing the new ispLEVER® 8.1 SP1 Starter software, which also supports the digital design portion of Platform Manager devices. This capability can be used for more complex digital designs targeted to the FPGA section of the Platform Manager device.
“PAC-Designer software’s point and click, intuitive, error-free syntax LogiBuilder utility has revolutionized power management design methodology for integrating various power management functions into a single chip,” said Gordon Hands, Director of Marketing for Lattice Low density and Mixed Signal Solutions. “Now this same design methodology can also be used to integrate digital board management functions into the Platform Manager’s FPGA.”
Platform manager devices provide programmable analog, CPLD and FPGA blocks to integrate a circuit board’s power management and digital management functions. The PAC-Designer 6.0 software provides a GUI-based design methodology for analog engineers using
intuitive dialog boxes to configure analog sections; the LogiBuilder design methodology to integrate power management functions into the on-chip CPLD; and the LogiBuilder or VHDL or Verilog design methodology to integrate digital board management functions into the FPGA section of the Platform Manager devices.
The PAC-Designer 6.0 software also provides three free correct-by-construction IP cores to implement functions such as closed-loop margining with Voltage ID (VID) Support, I2C/SPI slave interface and non-volatile fault logging into external SPI memory. Digital designers can also use ispLEVER 8.1 software to integrate other board management functions into the on-chip FPGA section using standard digital design methods.
Lattice's PAC-Designer software and companion ispLEVER Starter for Windows are available now for free download from the Lattice website,
With PAC-Designer 6.0, designers can use a simple, easy to learn, push-button design methodology to implement designs into the FPGA portion of the Platform Manager devices. Three new IP cores, which provide correct-by-construction application solutions, have also been announced.
Simultaneously, Lattice is announcing the new ispLEVER® 8.1 SP1 Starter software, which also supports the digital design portion of Platform Manager devices. This capability can be used for more complex digital designs targeted to the FPGA section of the Platform Manager device.
“PAC-Designer software’s point and click, intuitive, error-free syntax LogiBuilder utility has revolutionized power management design methodology for integrating various power management functions into a single chip,” said Gordon Hands, Director of Marketing for Lattice Low density and Mixed Signal Solutions. “Now this same design methodology can also be used to integrate digital board management functions into the Platform Manager’s FPGA.”
Platform manager devices provide programmable analog, CPLD and FPGA blocks to integrate a circuit board’s power management and digital management functions. The PAC-Designer 6.0 software provides a GUI-based design methodology for analog engineers using
intuitive dialog boxes to configure analog sections; the LogiBuilder design methodology to integrate power management functions into the on-chip CPLD; and the LogiBuilder or VHDL or Verilog design methodology to integrate digital board management functions into the FPGA section of the Platform Manager devices.
The PAC-Designer 6.0 software also provides three free correct-by-construction IP cores to implement functions such as closed-loop margining with Voltage ID (VID) Support, I2C/SPI slave interface and non-volatile fault logging into external SPI memory. Digital designers can also use ispLEVER 8.1 software to integrate other board management functions into the on-chip FPGA section using standard digital design methods.
Lattice's PAC-Designer software and companion ispLEVER Starter for Windows are available now for free download from the Lattice website,
Open-Silicon expands ASIC architecture and RTL design team to support derivative SoC solutions
MILPITAS, USA: Open-Silicon Inc. has opened an office in the Research Triangle Park (RTP), centrally located between Raleigh, Chapel Hill and Durham, North Carolina, to meet the increasing demand for derivative SoC solutions.
The new engineering center will focus on ASIC architecture, RTL design and design verification as a part of the company's existing derivatives design offering first launched several years ago with the development of an NXP chip in a record-breaking timeframe.
Located near cutting edge universities and several large technology companies, the new development center provides Open-Silicon with an additional global facility to support its growing customer base with experienced system design engineers.
As a collaborative engineering partner, Open-Silicon offers the complex architecture, RTL design and design verification solutions required to enable turnkey and derivative SoC development. This allows customers to add revenue to an existing IC product line through modifications to that design without pulling the engineering team from its next generation core product roadmap focus. The net result is a greater return on the overall product line investment.
With the previously announced 2009 acquisition of Silicon Logic Engineering (SLE), Open-Silicon grew the company's solutions offering from physical design and manufacturing to include the complex architecture and RTL design required to build complex SoCs in vertical markets such as networking, telecom, storage and computing.
The company's expanded in-house engineering teams work with Open-Silicon's existing design partners to meet the specific needs of each customer and design.
"Last year, when SLE joined Open-Silicon, we knew we had found a great front-end design team to compliment our comprehensive physical design team and design partners. Our customer response has been extremely positive to the integration of the derivatives design capabilities into our solutions offering," said Scott Houghton, VP marketing and business development at Open-Silicon.
"Adding this new facility for front end design, in a location with ready access to top tier talent, will help us continue to meet our customers' needs."
The new engineering center will focus on ASIC architecture, RTL design and design verification as a part of the company's existing derivatives design offering first launched several years ago with the development of an NXP chip in a record-breaking timeframe.
Located near cutting edge universities and several large technology companies, the new development center provides Open-Silicon with an additional global facility to support its growing customer base with experienced system design engineers.
As a collaborative engineering partner, Open-Silicon offers the complex architecture, RTL design and design verification solutions required to enable turnkey and derivative SoC development. This allows customers to add revenue to an existing IC product line through modifications to that design without pulling the engineering team from its next generation core product roadmap focus. The net result is a greater return on the overall product line investment.
With the previously announced 2009 acquisition of Silicon Logic Engineering (SLE), Open-Silicon grew the company's solutions offering from physical design and manufacturing to include the complex architecture and RTL design required to build complex SoCs in vertical markets such as networking, telecom, storage and computing.
The company's expanded in-house engineering teams work with Open-Silicon's existing design partners to meet the specific needs of each customer and design.
"Last year, when SLE joined Open-Silicon, we knew we had found a great front-end design team to compliment our comprehensive physical design team and design partners. Our customer response has been extremely positive to the integration of the derivatives design capabilities into our solutions offering," said Scott Houghton, VP marketing and business development at Open-Silicon.
"Adding this new facility for front end design, in a location with ready access to top tier talent, will help us continue to meet our customers' needs."
EquipIC supply chain expands presence in the Americas
HAARLEM, THE NETHERLANDS: EquipIC supply chain, a leading provider of ASIC supply chain solutions for fabless start up companies and system houses, is expanding its USA-based operations by forming a division of the company called EquipIC supply chain, LLC, and appointed Douglas McArthur VP and GM.
McArthur previously held senior management positions at Fingerprint Biometrics (Fujitsu Microelectronics America) and Philips Research Labs, Sunnyvale, California. Doug will oversee all aspects of EquipIC supply chain business in the Americas including development activities and the expansion of its customer support, marketing and sales teams.
“Our new division based in the heart of Silicon Valley will enable us to increase local support for customers throughout the Americas, and will play a key role in our strategy to grow revenues from over $8 million in 2010 to more than $15 million by 2012” said Geert Jan Davids, CEO of EquipIC supply chain. “I am extremely pleased to appoint Doug as VP and General Manager. He has a proven track record and customers in the region.”
“I am excited for this opportunity to lead this new division of EquipIC supply chain in the Americas market, and look forward to offering EquipIC’s unique supply chain methodologies to our customers.” said Doug McArthur.
McArthur previously held senior management positions at Fingerprint Biometrics (Fujitsu Microelectronics America) and Philips Research Labs, Sunnyvale, California. Doug will oversee all aspects of EquipIC supply chain business in the Americas including development activities and the expansion of its customer support, marketing and sales teams.
“Our new division based in the heart of Silicon Valley will enable us to increase local support for customers throughout the Americas, and will play a key role in our strategy to grow revenues from over $8 million in 2010 to more than $15 million by 2012” said Geert Jan Davids, CEO of EquipIC supply chain. “I am extremely pleased to appoint Doug as VP and General Manager. He has a proven track record and customers in the region.”
“I am excited for this opportunity to lead this new division of EquipIC supply chain in the Americas market, and look forward to offering EquipIC’s unique supply chain methodologies to our customers.” said Doug McArthur.
Subscribe to:
Posts (Atom)
