Denali announces state-of-the-art GHz DDR PHY technology

SUNNYVALE, USA: Denali Software Inc., a leading provider of EDA software and IP, has revealed a new phase PHY technology for DDR SDRAM physical interfaces, delivering memory system performance up to 1066 MHz clock speeds (or DDR-2133 data rates) on 65-nanometer foundry process nodes or lower.

Denali's phase PHY technology applies a high-speed oversampling architecture paired with per-bit data capture and calibration mechanism to achieve GHz clock rates. This third-generation DDR PHY technology is delivered as a fully-synchronous design which benefits design teams with the configurability needed to satisfy their physical implementation requirements.

As DDR SDRAM devices reach 2133 Mbps data rates, bit-to-bit skews within the data lanes become significant fractions of the data window. Denali's oversampling architecture employs an 8- or 16-phase lock loop (PLL) and performs pattern matching to determine the correct data sample points for DDR data for each transaction.

By managing the data capture on a per-bit basis (rather than on a per-byte basis), Denali's PHY reliably closes timing at 1066 MHz clock rates. Furthermore, differences in the routing of data and data strobe signals are calibrated in the silicon eliminating the need for time-consuming hand layout.

The fully-synchronous design provides flexibility for floorplanning, pin placement, and power routing and uses standard EDA toolsets to easily realize a reliable implementation.

"The continued demand for increased bandwidth in various internet and electronic applications is driving the need for DDR3 technology and for the ability to support data rates up to 2133 Mbp/s," states Mike McKeon, director of PHY IP at Denali. "Our DDR phase PHY is cutting-edge technology, delivering effective management of GHz clock speeds and a perfect match for our customers' specific design implementation needs."